An optimized Snubber Design for Three Level Inverter Systems

An optimized Snubber Design for Three Level Inverter Systems

HEROLD Gerhard

An Optimized Snubber Design for Three Level Inverter Systems Al-Nasseir J, Weindl Ch., Herold G., INSTITUTE OF ELECTRICAL POWER SYSTEMS University of Erlangen-Nürnberg Erlangen, Germany Tel.: +49 / (9131) – 8529514 Fax: +49 / (9131) – 8529541 E-Mail :[email protected], [email protected], [email protected] URL: http://www.eev.eei.uni-erlangen.de

Keywords Converter circuit, FACTS, Voltage source converter, Power semiconductor device, Protection device

Abstract Abstract - In this paper a new circuit design for the protection of e.g. multi level converters is presented. The so-called ‘optimized snubber design’ still comprises most of the positive features as a low number of components, improved efficiency due to the low snubber element and power semiconductor losses, reduced over-voltage across the semiconductor devices and no balancing problems. With these advantages, the new proposed snubber circuits can be used for high power inverters as well as the socalled Flexible AC Transmission Systems (FACTS). The presented snubber circuit has been analyzed and confronted with different existing converter designs using a simulation environment. The simulation results are compared with the output of a standardized three level converter system to verify the advantages of the new snubber design.

Introduction At present very large-sourced inverters are designed for the application in high voltage equipments, like transmission systems and FACTS equipment (Flexible AC Transmission Systems). These inverters have a power rating of 100 MVA or greater. The inverters require specialized high power gate-controlled valves due to their high MVA rating. At present, the gate turn-off Thyristor (GTO) is still one of the most important switching devices available for the use in this high power circuit designs (6000-V, 6000-A GTO’s are presently commercially available). The use of power semiconductors opens up the ability to control the interrelated parameters that govern the operation of transmission systems including series impedance, shunt impedance, current, voltage, phase angel and damping of oscillation at various frequencies below the rated frequency. In many cases the necessary new facilities depend on power semiconductor devices (GTO’s, IGBT’s, IGCT’s, etc) which build up the main parts e.g. in voltage and current source inverters. Of course the high power semiconductor switches need very specific protection systems (snubber circuits), which reduce the switching stresses to safe levels by: [1], [2] • • • •

Limiting the voltage during turn-off transients / limiting the current during turn-on transients. Limiting the rate-of-rise of (di/dt) current through the semiconductor device at device turn-on. Limiting the rate-of-rise of (dv /dt) voltage across the semiconductor device at device turn-off. Shaping the switching trajectory of the device as it turns on/off.

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An optimized Snubber Design for Three Level Inverter Systems

HEROLD Gerhard

The snubber circuits are divided to three classes: Unpolarized series RC snubbers are used to protect diodes and thyristors by limiting the maximum voltage and dv/dt at reverse-recovery. Polarized RCD snubbers are applied to shape the turn-off portion of the switching trajectory of controllable switches, to clamp voltage applied to the devices to safe levels or to limit dv/dt during device turn-off. Polarized RLD snubbers are used to shape the turn-on switching trajectory of controllable switches and/or to limit di/dt during device turn-on.

Common snubber circuit for power semiconductor devices (PSSD): Generally RCD snubber circuits are used to overcome the resulting over-voltage during the switch-off process of the semiconductor devices. RLD snubber circuits are implemented to limit the current and its increase during the turn-on process [2], [3], [4]. Both snubbers have to be integrated into the structural design of the more level inverter systems, the stray inductances in the switching paths and the different pulse patterns and load conditions. Additionally the total losses of each single component and the entire circuit have to be taken into account. Especially in high voltage or high power installations this yields to a multi-dimensional optimization criterion which can’t be solved using standard snubber designs based on a turn-off and turn on-snubber circuit as shown e.g. in figure 1. In principle turn-off snubbers shall provide a zero voltage across the switching device while the current turns off. The turn-on snubbers are used to reduce the turn-on switching losses at high switching frequencies and for the limitation of the maximum diode reverse recovery current [1]. Additionally the voltage across the switching device is reduced as the current builds up. The goal is to operate the switching device always inside the SOA (safety operating area). There are different snubber circuits proposed by W. McMurray [3], and Undeland [4], [5], which consist of RCD and RLD snubbers protecting the power semiconductor switching device. The first proposed circuit consists of a RLD (turn-on snubber circuit) and a RCD (turn-off snubber circuit) (as shown in figure 1).The values of the snubber circuit could be calculated by using the following equations [2]: Turn-on snubber equations: RON =∆VCE/IO. LS = (∆VCE * tri)/IO ∆VCE = 10% UN

(1) (2) (3)

Turn-off snubber equations: RS = 5*Vd/IO CS = (IO* tfi) / (2*Vd)

(4) (5)

Over voltage snubber equation COV = 200*K*CS ROV= RS

(6) (7)

The second proposed circuit (fig. 2) is made up of a combination of RCD and RLD snubber circuits. It consists of the following elements: CS (turn-off capacitor, limitation dv/dt), LS (turn-on inductor, di/dt limitation), COV (over voltage clamping), RS (resetting snubber inductor and capacity RS = RON), DS1; DS2: polarized diodes. The values of the elements can also be calculated with the above equations. With:

∆VCE: LS (or LON): RS : RON:

The voltage drop across the switch during turn-on. Turn-on inductive Turn-off resistor Turn-on resistor

C S: COV: tri : tfi : K:

Turn-off capacity Over-voltage capacity The current rise time The current fall time 10% Vd

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An optimized Snubber Design for Three Level Inverter Systems

HEROLD Gerhard

+

RON LON

Rs

Turn-on Snubber

Lon DS2

DS1

DON Vd

Cs Cd

DS Df

Df1

Cov

RS

Df2

GTO CS

GTO1

Turn-off Snubber

Fig. 1. Common turn-off and turn-on snubber circuits.

GTO 2

-

Fig. 2. Snubber circuit with off-, on- and overvoltage-snubber.

Common three level converters Normally RCD and RLD snubber are used to protect the semiconductor-switching device (all thyristor and transistor types) from electrical stresses in voltage-sourced inverters [2]. Figure 3 shows the resulting snubber circuit design for a single phase partial network of a three level converter. The different snubber elements are integrated into two separate sub-circuits. According to Fig. 1 two separate on-snubbers limiting the di/dt (inductor with discharge resistor and diode) can easily be identified. Additionally four off-snubbers, consisting of one discharge-resistor a charge capacitance and a polarizing diode, are used to protect the switching device from the over-voltage and the high dv/dt during turn-off.

Simple snubber configuration The simple snubber configuration was proposed by Joonmi Oh, Jinhwan Jung and Kwanhee Nam in [6], to protect the power semiconductor switching device during the turn-on and turn-off processes with a rather simple snubber circuit with less elements. It can be used only for two or three level inverters. The proposed snubber configuration consists of one resistor, two diodes, four capacitors and one mid-point inductance for each arm; those elements are connected in a much more integral approach than in the common snubber depicted in figure. 3. Figure 4 shows the proposed snubber circuit for a single phase of a three level converter system. The great advantage of this simple snubber configuration is the fewer number of snubber elements, which is less than number of elements used in the common snubber circuit. Therefore, the manufacturing cost, losses, and complexity will be reduced.

Optimized snubber design for three level inverters The new optimized snubber design consists of a centre-tapped inductor (LON1, LON2) a damping resistor (RON), four diodes (DON1, DON2, DS1, DS2), four capacitors (CS1, CS2, CS3, CS4), and three resistors (RS1, RS2) for each arm of the three-phase inverter system. Table I compares the number of components for the common snubber circuit (RLD/RCD), the simple snubber configuration and the new optimized snubber design. The new optimized design includes three resistors, while the common snubber needs six resistors. Additionally the new design allows leaving out two diodes. The optimized snubber design has the following advantages:

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An optimized Snubber Design for Three Level Inverter Systems

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LON1 DS1 RON1

DON1

Df1

RS1 CS1

GTO1

Df1

GTO2

Df2

Ed

CS1

Ed

GTO1

C1

C1

DS2 DC1

Df2

CS2

DC1

RS2 RD

GTO2

DS1

CS2

RD

LON1

VD

0

0

RS1

The Load VD

DS3 Df3 Ed

LON2

RS3

DC2

GTO3

To The Load

DS2

Ed

DC2

CS3

C2

CS3

GTO3

Df3

GTO4

Df4

C2 DS4 DON2

RON2

Df4

RS4

GTO4

CS4

CS4 LNO2

Fig.4. One phase of a three level converter with a simple snubber configuration

Fig. 3. Single phase of a three level converter (common snubber circuit). •

Inverters based on the optimized snubber design are suitable for high voltage applications (like FACTS equipments and HVDC systems) since the voltage sharing between serially connected power devices is guaranteed. • The number of elements, which are necessary for the optimized snubber design, is less than those, which are needed for the conventional circuit. • The manufacturing cost, the complexity and also the converter size can be reduced. • The performance of the optimized snubber design in the direction of the over-voltage protection of the power semiconductors is better than that of conventional snubber circuits. • There are only two resistors used to discharge the capacitors, so the total losses are lower than those of the conventional design. Because of the fewer elements in the snubber circuit the theoretic reliability will be higher. Therefore the implementation of the optimized snubber design is favorable especially in cases when the optimization of losses and/or over-voltages is of highest interest.

Table I: Total number of snubber elements for different snubber designs Components RLD/RCD Snubber Simple Snubber Configuration Optimized snubber design

Capacitors 4 4 4

Diodes 6 4 2

Inductors 2 2 2

Resistors 6 1 3

To analyze the physical background of the protection performance, some of the basics of the different switching operations have to be discussed. Therefore the possible switching states of a single phase of a

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An optimized Snubber Design for Three Level Inverter Systems

HEROLD Gerhard

three level inverter system are listed in table.3. Due to the symmetry, it is sufficient to consider only a complete cycle of communication process: S0→ S1→ S0→ S-1 assuming that the load current is flowing out. There is an important assumption which simplifies the analysis of the snubber design. It is that the Thyristor current changes linearly in time with a constant di/dt (the load current is constant), which is only dictated by the GTO-Thyristor current and its base driver’s circuit. Therefore, the di/dt, which may be different for the turn-on and the turn-off processes, is assumed not to be effected by adding the snubber circuits. Also, it is assumed, that the time constant of the load (milliseconds) is much larger than the switching time (in the microsecond range), so the load current IL remains almost constant during the switching period. Based on these premises the relevant transition or commutation phases will be closer analyzed in the following.

Table II. Three Switching States Switching states GTO1 GTO2 GTO3 GTO4

S1 ON ON OFF OFF

S0 OFF ON ON OFF

S-1 OFF OFF ON ON

Commutation from S0 to S1

The current transition in this phase is defined by the turning-off of GTO3. After a defined dead time GTO1 is turned on. During that period the load current is flowing through the clamping diode DC1 and GTO2. The snubber capacitors CS1 and CS4 are charged up to Ed and CS2, CS3 are totally discharged. Phase 1: The semiconductor switching device GTO1 starts turning on, so the current flowing through it begins to increase and the current through the clamping diode DC1 starts to decreases. The energy, which is stored in LON2 will be dissipated through the loop DON2, RON, DON1, LON1. Phase 2: In this step, the current through GTO1 continues to increase during the current rise time. As soon as the clamping diode DC1 ceases to conduct, the load terminal voltage goes up charging CS2 and CS3 and discharging CS1. The CS1 discharging loop is formed through GTO1 and RS. At the end of this step the capacitor CS1 is completely discharged and DS1 is conducting.

Commutation from S1 to S0

During this phase GTO1 is turned off and GTO3 is turned on after the necessary dead time. The initial condition for this period is the final state of the previous commutation. During the turn-off period of GTO1 the load current is absorbed by CS1. Phase 1: In Phase 1, iGTO1 decreases linearly from ILOAD to zero during the current fall time period. This step ends when iGTO1 reduces to zero. Phase 2: In Phase 2 the load current ILOAD charges CS1 through the turn-off diode DS1. Finally the complete load current flows through the clamping diode DC1. After that, GTO3 begins to turn-on after a suitable dead time. In this case the commutation process is completed.

Commutation from S0 to S−1

During this phase GTO2 is turned off and GTO4 is turned on after the corresponding dead time. The initial conditions are the following: CS1 and CS4 are completely charged up to Ed; CS2 and CS3 are completely discharged and the load current flows through the free wheeling diodes DF3 and DF4.

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An optimized Snubber Design for Three Level Inverter Systems

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Phase 1: When GTO2 is turned off the load current will be absorbed by CS2 charging it. During GTO2 is turned off, the voltage drop across GTO1 remains Ed, while the voltage drop across GTO2 is increasing. iGTO2 decreases linearly from ILOAD to zero during the current fall time. This step ends when iGTO2 reached zero. Phase 2: The voltage over GTO2 continues to rise; this step ends when VCS2 reaches Ed.

DS1 DF1

RS1

GTO1

CS1 Turn-Off Snubber

C1 Ed DC1

DF2

GTO2

CS2 DON1 Over-voltage Snubber

RD LON1

To The Load

0 VD

RON LNO2

DON2 DC2

DF3

GTO3

DF4

GTO4

Ed

Turn-On Snubber CS3

C2

RS2

CS4

DS4

Fig.5.Single phase of a three level GTO inverter with an optimized snubber design.

Performance of the optimized snubber design The main advantage of the optimized snubber design is, that the three snubber circuits (turn-on, turn-off, and over-voltage) are used in combination and that the number of the required elements is less than those, which are necessary for the common snubber circuit. The operation of the power semiconductor switching devices still remains in the SOA (safety operation area) and additionally the converter size, its cost, and the losses can be reduced. Figure 5 shows a three level inverter with the corresponding optimized snubber design. • The turn-off snubber circuit protects the power switching semiconductor device from the overvoltage, which appears during the turn-off process, because of the high current change rate (di/dt). Therefore the circuit wiring inductance can cause a high turn-off surge voltage. The charging process takes place as in the common snubber circuit, through the turn-off diode. The discharging process occurs through the power semiconductor switching device, the turn-on resistor, and the mid-point inductance for the second and third GTO. The charging and discharging of GTO1 and GTO4 is realized in the ‘normal’ way by DS1/DS4 and RS1/RS2 respectively. • The turn-on snubber’s circuits limits the di/dt during turning on and reducing the voltage across the power semiconductor switching device due to the voltage drop across the inductance when the current builds up. During the on-state of the power semiconductor switching device, the load

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An optimized Snubber Design for Three Level Inverter Systems

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HEROLD Gerhard

current flows through the turn-on inductance. When the power semiconductor switching device is turned off, the stored energy in the snubber inductance will be dissipated in the resistor RON. The over-voltage snubber circuit minimizes the over-voltage, which is caused by the stray- and turn-on inductance across the power semiconductor switching device to safe levels. The energy stored in LON1 gets transferred to the turn-off capacitor CS2 through the diode DON1. So there is no over-voltage across the power semiconductor switching device, because it will be limited to Ed through the resistor RON. This snubber circuits consist of the following elements: CS2, CS3, RON, DON1, and DON2.

Simulation results The simulation is based on a detailed Matlab©/Simulink™ model. The analyzed model comprises a single phase of an MV three level inverter. The load and source data are given by Ed = 6000 V, IL = 5000 A. The power factor of the load was set to Pf = 0.8. The parameters of the snubber circuit were taken according the data sheet of the used GTO semiconductor devices (RS = 5Ω, CS = 1µF). The current fall time of the GTOs was set to tfi = 5 µs. For the proposed circuit the values of the snubber elements were set to: RS = 5Ω, CS = 1 µF. The GTO internal parameters are given by the default values of the Simulation System as follows: LON = 1 µH Vf = 1 V (forward-voltage) tfi = 5 µs (current fall time) RON = 0.001Ω

Comparison between the common and the optimized snubber design In the first simulation a comparison of the common snubber circuit and the optimized snubber design will be done. The element parameters were chosen as in the data sheet of the used GTO power semiconductor switching device (RS = 5Ω, CS = 1µF). The load scenario was chosen suitable to a modern MV converter system Ed = 6000 V, IL = 5000 A. In the second simulation, all the parameters of the two configuration circuits were chosen in the same way. Only the value of the capacitor CS was reduced to 0.1 µF, while this reduction improves the performance of the optimized snubber design in the direction of reduced losses and the over-voltage across the power semiconductor switching device [1], [6]. In the following figures the stress for different semiconductor devices (GTOs and diodes) will be analyzed. The figures 6 and 7 show, that the over-voltages across GTO1 and GTO2 are limited in a better way by the optimized snubber than the common snubber design during the turn-off process.

Fig. 6. Voltage over GTO1 in the common and optimized snubber design (Ed= 6000 V and IL= 5000 A, CS = 1µF).

Fig. 7. Voltage over GTO2 in the common and optimized snubber design (Ed= 6000 V and IL= 5000 A, CS = 1µF).

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An optimized Snubber Design for Three Level Inverter Systems

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The current spikes are also much smaller than those in the common snubber circuit as shown in fig. 8. The figures 9 and 10 show the current in the freewheel diodes and in the turn-off diode. It can easily be seen, that the currents resulting from the optimized snubber design are more adequate than those simulated for the common snubber circuit. The over-voltage across DS1 is also less in the optimized snubber design than those in the common snubber circuit (see figure 11).

Fig.9. Current in DS1 in the common and the optimized snubber configuration. (Ed= 6000 V and IL= 5000 A, CS = 1µF).

Fig. 8. Current in GTO2 in the common and optimized snubber design (Ed= 6000 V and IL= 5000 A, CS = 1µF).

Fig.10. Current in Df2 in the common and the optimized snubber configuration. (Ed= 6000 V and IL= 5000 A, CS = 1µF).

Fig.11. Voltage across Ds1 in the common and the optimized snubber configuration. (Ed= 6000 V and IL= 5000 A, CS = 1µF).

Figs.12 shows the total losses in the circuit (GTO, diode and snubber element losses) for the two different snubber designs (conventional snubber circuit and optimized snubber design). The losses are shown as an energy function over three cycles of the fundamental frequency. As indicated, the lost energy in converters based on the optimized snubber design is much lower than that dissipated in the common snubber design. The next figures (13, 14 and 15) show the voltage and the current resulting in GTO1,2. The over-voltage shown in the figures 13 and 14 across GTO1 and GTO2 in the optimized snubber design is more limited than it is in the common snubber design and the current spikes through GTO2 are much smaller (see figure 15). The current through the freewheel diode and the turn-off diode is more improved by the optimized snubber design than by the common snubber circuit (figures 16 and 17). The over-voltage across the turn-off diode in the optimized snubber design becomes more acceptable than the same voltage in the common snubber circuit (see figure 18). The total losses in the optimized snubber design and the common snubber circuit are compared as an energy function over two cycles of the fundamental frequency in fig. 19. As mentioned before, the total lost energy in the optimized snubber design in this

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An optimized Snubber Design for Three Level Inverter Systems

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simulation is much lower than in the common snubber circuit. One of the reasons therefore is that the losses are related to the capacitors CS. Also the losses in the GTOs itself are less for the optimized snubber design but the difference here is not so much.

Fig. 12 Comparison of the total losses in the analyzed three level inverters (energy function) (Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF).

Fig. 13 Voltage over GTO1 in the common and optimized snubber design (Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF).

Fig. 14. Voltage over GTO2 in the common and optimized snubber design (Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF).

Fig.15. Current in GTO2 in the common and optimized snubber design (Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF).

Fig.16. Current in Df1 in the common and the optimized snubber configuration (Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF).

Fig 17 Current in DS1 in the common and the optimized snubber configuration(Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF)

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Fig.18.Voltage across DS1 in the common and the optimized snubber configuration (Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF).

Fig. 19 Comparison of the total losses in the analyzed three level inverters (energy function, Ed= 6000 V and IL= 5000 A, CS-Opt = 0.1µF))

Conclusion In this paper an optimized snubber design is proposed to be used in high voltage and high power morelevel converter systems and partially FACTS devices. The optimized snubber design is based on a new and simple structured snubber, which depends on passive elements. As a result, the number of required components is reduced, and the reliability increases distinctly. The presented optimized snubber design provides several additional advantages: It increases the optional performance of the three level converters due to the lower clamping over-voltages across the switching devices, it improves the efficiency because of the lower snubber and total losses, its suitable structure can be extended to energy recovery snubbers and there is no unbalance problem. Additionally, the manufacturing costs, the complexity and therefore the converter size can be reduced. The simulation results were carried out using a Matlab/SimulinkTM model, which is based on a single-phase of a MV three level inverter system. The results show the advantages of the optimized snubber design especially for the operation close to the limits of the SOA (safety operating area).

References [1] Jamal Alnasseir, Christian Weindl, Gerhard Herold, “Calculation of Over-voltage and Losses in Three Level Converters with Double Snubber Circuit”. EPE-PEMC 2004. 11th International Power Electronic and Motion Control Conference. Sep, 2-4 Riga, Latvia 2004. [2] Ned Mohan, Tore M. Undeland, William P. Robins, Power electronic; second edition, John Wiley & Sons Inc New York, USA, 1955. [3] W. McMurray “Efficient snubbers for voltage-source inverters, “IEEE Trans., Power Electronics”. Vol. PE-2, no 3, pp 264-274 July 1987. [4] Tore M. Undeland, “Switching Stress Reduction in Power Transistor Inverter”, IEEE Industrial, 1976. [5] Tore M. Undeland, F. Jensen, A. Steinbakk, T. Rogne, and M. Hernes,“ A snubber configuration for both power transistor and GTO PWM Inverter;” IEEE Power Electronics Specialist Conf. Rec ., Gaithersberg, MD , June 1821,1984,pp. 42-53. [6] Joonmi OH, Jinhwang Jung and Kwanghee Nam,” A simple snubber configuration for three level voltage source GTO inverters”, 0-7803-3008-0/95$4.00 ©1995 IEEE.

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