Chapter 13: Verification - Wiley

Chapter 13: Verification

Chapter 13: Verification Prof. Ming-Bo Lin

Department of Electronic Engineering National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Syllabus ™ ™ ™ ™ ™ ™

Objectives Function verification Simulation Test bench design Dynamic timing analysis Static timing analysis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Objectives After completing this chapter, you will be able to: ™ Describe the importance and essential of verification ™ Understand the essential of timing and functional verification ™ Describe the essential issues of simulators ™ Understand the essential principles of test bench designs ™ Understand the principle of dynamic timing analysis ™ Understand the principle of static timing analysis ™ Understand issues of coverage analysis ™ Describe the ISE design flow and related issues

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Syllabus ™ Objectives ™ Functional verification ƒ Introduction ƒ Functional verification ƒ Simulation-based verification

™ ™ ™ ™

Simulation Test bench design Dynamic timing analysis Static timing analysis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Verification ™ The goal of verification ƒ To ensure 100% correct in functionality and timing ƒ Spend 50 ~ 70% of time to verify a design

™ Functional verification ƒ Simulation ƒ Formal proof

™ Timing verification ƒ Dynamic timing simulation (DTS) ƒ Static timing analysis (STA)

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Syllabus ™ Objectives ™ Verification ƒ Introduction ƒ Functional verification ƒ Simulation-based verification

™ ™ ™ ™

Simulation Test bench design Dynamic timing analysis Static timing analysis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Functional Verification ™ Simulated-based functional verification ƒ A test bench ƒ Input stimuli ƒ Output analysis

™ Formal verification ƒ ƒ ƒ ƒ

A protocol An assertion A property A design rule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Models of Design under Test ™ Black box model ™ White box model ™ Gray box model

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Types of Assertion ™ Static assertion ™ Temporal assertion

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Syllabus ™ Objectives ™ Verification ƒ Introduction ƒ Functional verification ƒ Simulation-based verification

™ ™ ™ ™

Simulation Test bench design Dynamic timing analysis Static timing analysis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Simulation-Based Verification

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Hierarchy of Functional Verification ™ ™ ™ ™

Designer level (or block-level) Unit level Core level Chip level

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

A Verification Test Set ™ Verification test set includes at least ƒ ƒ ƒ ƒ ƒ ƒ

Compliance tests Corner case tests Random tests Real code tests Regression tests Property check

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Formal Verification ™ Uses mathematical techniques ™ Proves a design property

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Syllabus ™ Objectives ™ Verification ™ Simulation ƒ Types of simulations and simulators ƒ Architecture of HDL simulators

™ Test bench design ™ Dynamic timing analysis ™ Static timing analysis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Types of Simulations ™ ™ ™ ™ ™

Behavioral simulation Functional simulation Gate-level (logic) simulation Switch-level simulation Circuit-level (transistor-level) simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Variations of Simulations ™ Software simulation ™ Hardware acceleration ™ Hardware emulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Syllabus ™ Objectives ™ Verification ™ Simulation ƒ Types of simulations and simulators ƒ Architecture of HDL simulators

™ Test bench design ™ Dynamic timing analysis ™ Static timing analysis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

An Architecture of HDL Simulators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Verilog HDL Simulators ™ Interpreted simulators ƒ Cadence Verilog-XL simulator

™ Compiled code simulators ƒ Synopsys VCS simulator

™ Native code simulators ƒ Cadence Verilog-NC simulator

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Event-Driven/Cycle-Based Simulators ™ Event-driven simulators ƒ Triggered by events

™ Cycle-based simulators ƒ On a cycle-by-cycle basis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

An Event-Driven Simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Syllabus ™ ™ ™ ™

Objectives Verification Simulation Test bench designs ƒ ƒ ƒ ƒ

Test bench design Clock signal generation Reset signal generation Verification coverage

™ Dynamic timing analysis ™ Static timing analysis Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Test Bench Design Principles ™ Functions of a test bench ƒ generates stimuli ƒ checks responses in terms of test cases ƒ employs reusable verification components

™ Two types of test benches ƒ deterministic ƒ self-checking

™ Options of choosing test vectors ƒ Exhaustive test ƒ Random test ƒ Verification vector files Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Test Bench Design Principles ™ Two basic choices of stimulus generation ƒ Deterministic versus random stimulus generation ƒ Pregenerated test case versus on-the-fly test case generation

™ Types of result checking ƒ on-the-fly checking ƒ end-of-test checking

™ Result analysis ƒ Waveform viewers ƒ Log files Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Types of Automated Response Checking ™ Golden vectors ™ Reference model ™ Transaction-based model

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 13: Verification

Test Bench Designs --- A Trivial Example // test bench design example 1: exhaustive test. `timescale 1 ns / 100 ps … nbit_adder_for UUT (.x(x), .y(y), .c_in(c_in), .sum(sum), .c_out(c_out)); reg [2*n-1:0] i; initial for (i = 0; i