Rotate registers. • Counters. • Implementations of these components can use
state machines, but, it is often easier to think of them without the complication of a
...
INTRO. TO COMP. ENG. CHAPTER IX-1
•CHAPTER IX
REGISTER BLOCKS
CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS READ PAGES 249-275 FROM MANO AND KIME
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG. CHAPTER IX-2 REGISTER BLOCKS •
REGISTER BLOCKS
•REGISTER BLOCKS -INTRODUCTION
INTRODUCTION
Like combinational building blocks, we can also develop some simple building blocks using registers. These include: • Shift registers • Rotate registers • Counters
•
Implementations of these components can use state machines, but, it is often easier to think of them without the complication of a state machine.
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG. CHAPTER IX-3
SHIFT REGISTERS
REGISTER BLOCKS •
•REGISTER BLOCKS -INTRODUCTION
INTRODUCTION
Logical shift registers take the bits stored and move them up a significant bit or down a significant bit. MSB LOGICAL SHIFT RIGHT (LSR)
0 Cout
Sign bit ARITHMETIC SHIFT RIGHT replication (ASR) LOGICAL SHIFT LEFT (LSL) ARITHMETIC SHIFT LEFT (ASL) •
Cout 0
Cout 0 Cout
Notice that logical and arithmetic shift lefts are the same.
R.M. Dansereau; v.1.0
LSB
SHIFT REGISTERS
INTRO. TO COMP. ENG. CHAPTER IX-4
LSR SAMPLE
REGISTER BLOCKS •
•REGISTER BLOCKS •SHIFT REGISTERS -INTRODUCTION
A simple implementation of a logical right shift register might look like the following.
0
MSB D
LSB D
Q
D Q
D Q
Q
Shift? CLK zn – 1
R.M. Dansereau; v.1.0
zn – 2
zn – 3
z0
SHIFT REGISTERS
INTRO. TO COMP. ENG. CHAPTER IX-5
ASR SAMPLE
REGISTER BLOCKS •
•REGISTER BLOCKS •SHIFT REGISTERS -INTRODUCTION -LSR SAMPLE
An arithmetic right shift register might look like the following.
MSB D
LSB D
Q
D Q
D Q
Q
Shift? CLK zn – 1
R.M. Dansereau; v.1.0
zn – 2
zn – 3
z0
SHIFT REGISTERS
INTRO. TO COMP. ENG. CHAPTER IX-6
4-BIT BIDIRECTIONAL
REGISTER BLOCKS •
•SHIFT REGISTERS -INTRODUCTION -LSR SAMPLE -ASR SAMPLE
The following is a 4-bit bidirectional shift register with parallel load. x3 x2 x1 x0
xl
xr 3 2 1 0 4x1 MUX
3 2 1 0 4x1 MUX
3 2 1 0 4x1 MUX
3 2 1 0 4x1 MUX
D
D
D
D
c0 c1
Q CLK R.M. Dansereau; v.1.0
z3
Q z2
Q z1
Q z0
INTRO. TO COMP. ENG. CHAPTER IX-7
SHIFT REGISTERS CASCADING (1)
REGISTER BLOCKS •
•SHIFT REGISTERS -LSR SAMPLE -ASR SAMPLE -4-BIT BIDIRECTIONAL
Cascading of shift registers can also be done if the discarded bit is used to shift into another shift register module.
•
For instance, the 4-bit bidirectional shift register previously presented can be easily cascaded using the • x r (right shift data input) and • x l (left shift data input)
c0 c1
R.M. Dansereau; v.1.0
x3
x2
x1
x0
4-bit bidirectional shift register z3 z2 z1 z0
xl xr
INTRO. TO COMP. ENG. CHAPTER IX-8
SHIFT REGISTERS
REGISTER BLOCKS •
CASCADING (2)
•SHIFT REGISTERS -ASR SAMPLE -4-BIT BIDIRECTIONAL -CASCADING
For example, an 8-bit bidirectional shift register with parallel load can be formed as follows. x7 x6 x5 x4 c0 c1 c0 c1
x3 x2 x1 x0 4-bit bidirectional shift register
z3 z2 z1 z0
z7 z6 z5 z4
R.M. Dansereau; v.1.0
x3 x2 x1 x0
xr
xl
c0
xr
c1
x3 x2 x1 x0 4-bit bidirectional shift register
z3 z2 z1 z0
z3 z2 z1 z0
xl
xl xr
INTRO. TO COMP. ENG. CHAPTER IX-9 REGISTER BLOCKS •
ROTATE REGISTERS INTRODUCTION
•SHIFT REGISTERS -ASR SAMPLE -4-BIT BIDIRECTIONAL -CASCADING
A rotate register is the same as a logical shift register except that the discarded bit is fed back into the empty space from the shift. MSB
LSB
ROTATE RIGHT
ROTATE RIGHT WITH CARRY C ROTATE LEFT
ROTATE LEFT WITH CARRY C R.M. Dansereau; v.1.0
ROTATE REGISTERS
INTRO. TO COMP. ENG. CHAPTER IX-10
USING SHIFT REGISTERS
REGISTER BLOCKS •
•SHIFT REGISTERS •ROTATE REGISTERS -INTRODUCTION
Rotate registers can actually be implemented using shift registers that have serial data inputs (such as the 4-bit bidirectional shift register discussed).
•
For example, a 4-bit rotate register can be formed as follows. x3 x2 x1 x0 c0
c0
c1
c1
x3 x2 x1 x0 4-bit bidirectional shift register
z3 z2 z1 z0
z3 z2 z1 z0
R.M. Dansereau; v.1.0
xl xr
INTRO. TO COMP. ENG. CHAPTER IX-11 REGISTER BLOCKS •
COUNTERS INTRODUCTION
•SHIFT REGISTERS •ROTATE REGISTERS -INTRODUCTION -USING SHIFT REGISTERS
A counter is a register that on each clock pulse counts up or down, usually in binary.
•
Types of counters • ripple counters • synchronous counters • binary counters • BCD counters • Gray-code counters • Ring counters (a 1 moves in a ring from one flip-flop to the next) • up/down counters (ability to increment or decrement) • counters with a parallel load (load in starting value with parallel input)
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG. CHAPTER IX-12 REGISTER BLOCKS •
COUNTERS MODULO-P COUNTERS
•SHIFT REGISTERS •ROTATE REGISTERS •COUNTERS -INTRODUCTION
A modulo-p counter is defined by the following equation. S ( t + 1 ) = ( S ( t ) + x ) mod p
•
The state diagram for the modulo-p counter is as follows. 1
S0 ⁄ 0
0
R.M. Dansereau; v.1.0
1
S1 ⁄ 1
0
1
S2 ⁄ 2
0
1
Sp – 1 p–1 0
INTRO. TO COMP. ENG. CHAPTER IX-13 REGISTER BLOCKS •
COUNTERS RIPPLE AND SYNCHRONOUS
•ROTATE REGISTERS •COUNTERS -INTRODUCTION -MODULO-P COUNTERS
An n-bit binary counter consists of n flip-flops and can count in binary from 0 through 2 n – 1 . • This can be formed with a modulo-p counter where p = 2 n .
•
Two main categories exist for counters: • Ripple counters • One flip-flop transition serves to trigger other flip-flops. • The clock pulse is usually only sent to the first flip-flop. • This requires a memory cell that can complement its value. • The JK flip-flip would be one approach (we have not studied this!) • Synchronous counters • Change of state is determined from the present state. • Clock pulse sent to all flip-flops.
R.M. Dansereau; v.1.0
COUNTERS
INTRO. TO COMP. ENG. CHAPTER IX-14
TOGGLE CELL
REGISTER BLOCKS •
•COUNTERS -INTRODUCTION -MODULO-P COUNTERS -RIPPLE & SYNCHRONOUS
A toggle cell will be useful for implementing counters.
CE (Count Enable)
CLEAR Present CE Latch Value X X 0 0 1 0 0 1 1 1 R.M. Dansereau; v.1.0
CLEAR 0 1 1 1 1
Transparent Latch
Transparent Latch
φ1
φ2
Next OUT Latch Value 0 ? 0 0 1 1 1 0 0 1
OUT
Toggle cell CE OUT CLEAR
φ1 φ2
COUNTERS
INTRO. TO COMP. ENG. CHAPTER IX-15
•COUNTERS -MODULO-P COUNTERS -RIPPLE & SYNCHRONOUS -TOGGLE CELL
RIPPLE COUNTER
REGISTER BLOCKS
The toggle cell can be used as follows to form a ripple counter. CE (Count Toggle cell Toggle cell Toggle cell Toggle cell Enable) CE CE CE CE
•
φ1
OUT CLEAR
OUT CLEAR
OUT CLEAR
OUT CLEAR
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
φ2 CLEAR z0
z1
z2
z3
• Notice that the previous toggle cell is connected to the clock input of the next cell. This causes the bits to ripple through the counter. R.M. Dansereau; v.1.0
COUNTERS
INTRO. TO COMP. ENG. CHAPTER IX-16
SYNCHRONOUS COUNTER
REGISTER BLOCKS •
•COUNTERS -RIPPLE & SYNCHRONOUS -TOGGLE CELL -RIPPLE COUNTER
Below is an example 4-bit synchronous counter using toggle cells.
Toggle cell CE (Count Enable)
Toggle cell
CE
Toggle cell
CE OUT
CE OUT
CLEAR
Toggle cell CE
OUT
CLEAR
OUT
CLEAR
CLEAR
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
CLEAR z0
z1
z2
• Notice that clock is sent to all toggle cells. • A simplified form is in Figure 5-11, pp. 269 of Mano & Kime. R.M. Dansereau; v.1.0
z3
COUNTERS
INTRO. TO COMP. ENG. CHAPTER IX-17
MORE ON MODULO-P
REGISTER BLOCKS
•
•COUNTERS -TOGGLE CELL -RIPPLE COUNTER -SYNCHRONOUS COUNT.
Notice that the counters developed so far can count from 0 to 2 n – 1 for n toggle cells. • Therefore, for module-p counting, the p is currently limited to 2 n .
•
How about if we wish p to be a non-power of 2? • Need to build what can be referred to as a divide by counter. • Given the following counter block, a general modulo-p counter can be constructed by clearing the counter after the desired maximum value. CE
4-bit counter
CLEAR z3
R.M. Dansereau; v.1.0
z2
z1
z0
φ1 φ2
INTRO. TO COMP. ENG. CHAPTER IX-18 REGISTER BLOCKS •
COUNTERS BCD COUNTER (MODULO-10)
•COUNTERS -RIPPLE COUNTER -SYNCHRONOUS COUNT. -MORE ON MODULO-P
To illustrate general modulo-p counters, consider the following implementation of a single digit decimal counter using BCD. CE
CE
4-bit binary counter CLEAR z3 z2 z1 z0
φ1
φ1
φ2
φ2
CLEAR
TC Terminal Count Output • Notice that the counter is cleared after a value of 9 (1001). R.M. Dansereau; v.1.0
z3 z2 z1 z0
INTRO. TO COMP. ENG. CHAPTER IX-19 REGISTER BLOCKS •
COUNTERS
•COUNTERS -SYNCHRONOUS COUNT. -MORE ON MODULO-P -BCD COUNTER
TERMINAL COUNT (TC)
The previous BCD counter was built by deriving a terminal count (TC) output signal.
•
A terminal count output signal for any counter can be useful, so, we will be included in general block diagram for a binary counter.
CE 4-bit binary CLEAR counter TC z 3 z 2 z 1 z 0
φ1 φ2
Notice TC output • In this 4-bit binary counter example, TC=1 only when the output is 1111. R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG. CHAPTER IX-20 REGISTER BLOCKS •
COUNTERS
•COUNTERS -MORE ON MODULO-P -BCD COUNTER -TERMINAL COUNT
CASCADING COUNTERS
With a terminal count output (TC), counters can be easily cascaded together to form larger counters. • For instance, an 8-bit binary counter can be formed as follows. CLEAR CE CE CLEAR TC
4-bit binary counter
z3 z2 z1 z0
z7 z6 z5 z4 R.M. Dansereau; v.1.0
φ1 φ1
CE
φ2 φ2
CLEAR TC
4-bit binary counter
z3 z2 z1 z0
z3 z2 z1 z0
φ1 φ1 φ2 φ2
