Current Source & Bias Circuits - Department of Computer Science ...
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Current Source & Bias Circuits - Department of Computer Science ...
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CSE 577 Spring 2011
Current Source & Bias Circuits
Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Pennsylvania State University
Introduction
Required Features of Current Source
High Rout Wide Operation Range Constant Current Source Low PVT (Process, Voltage, Temperature) Sensitivity
Required Features of Bias Circuit
Low Rout Low PVT Sensitivity
2/22/2011
Insoo Kim
Current Source
• • •
Basic Current Source Wilson Current Mirror Cascode Current Mirror
Ideal vs. Actual Current Source
2/22/2011
Insoo Kim
Simple NMOS Current Source
What’s the bad feature of this? 2/22/2011
Insoo Kim
Cascode Current Source
What’s the bad feature of this? 2/22/2011
Insoo Kim
Basic Current Mirror
What’s the bad feature of this? 2/22/2011
Insoo Kim
Wilson Current Mirror
• I out = I ref ⋅
g m1 (W / L)1 = I ref ⋅ g m2 (W / L) 2
What’s the drawback of this circuit?
2/22/2011
Insoo Kim
Cascode Current Mirror
But, it still has limited output swing problem.
2/22/2011
Insoo Kim
Wide Swing Cascode Current Mirror
2/22/2011
Insoo Kim
Bias Circuits
• • •
Self Bias Circuits PTAT Bias Circuits Band gap Reference
How do we generate Iref independent of the supply voltage?
2/22/2011
Insoo Kim
Self Biasing Circuit
What’s role of Rs?
What’s the advantage of these circuits? What’s the problem of these circuits? 2/22/2011
Insoo Kim
Improved Self Biasing Circuit
Improved Circuit with Start-up Circuit Improved Circuit eliminating Body Effect
2/22/2011
* This Circuit is practical only if
Insoo Kim
A Simple Temperature Compensation Concept 0℃ ℃ VDD
VDD
90℃ ℃
M1(Ids) Negative TC
v
Positive TC ZTC (Zero Temperature Coefficient)
vr0 M1 R1
Self Bias Circuit
2/22/2011
M1(Vgs) 1. R1 is a conductor which has positive TC 2. M1 has negative TC below ZTC point (Semiconductor) 3. If we control Vr0 below ZTC point, Vr0 become less sensitive to temperature due to opposite TC of M1 and R1
Insoo Kim
Case Study (I) – Self Bias Circuit in DRAM starter
ⓐ
ⓑ
For Temp. Compensation
pmos diode
Vext
ⓑ vref ⓐ What’s the drawback of these circuits? 2/22/2011
Insoo Kim
Case Study (II) – Self Bias Circuit in DRAM Why does this circuit need the voltage buffer? Why are PMOS current mirrors stacked in the reference bias circuit? Voltage Buffer
vr1 ⓐ
starter
For Temp. Compensation
ⓐ
2/22/2011
Insoo Kim
VBE Referenced CMOS SelfSelf-bias Circuit
How do we fabricate BJT in CMOS Process Technology? 2/22/2011
* Temperature Sensitivity ~ - 4000 ppm/C
Insoo Kim
Realization of pnp BJT in CMOS Technology
2/22/2011
Insoo Kim
Vth Referenced CMOS SelfSelf-Bias Circuit
2/22/2011
Insoo Kim
Thermal Voltage Referenced CMOS SelfSelf-Bias Circuit
2/22/2011
Insoo Kim
Thermal Voltage Referenced CMOS SelfSelf-Bias Circuit
* Temp. Sensitivity ~ +3300 ppm/C 2/22/2011
Insoo Kim
CMOS Band gap Reference
What’s the problem? 2/22/2011
Insoo Kim
(cont’d) CMOS Band gap Reference
Actual Implementation of CMOS Band Gap Reference
2/22/2011
Insoo Kim
Actual Implementation of CMOS Band gap Reference
2/22/2011
Insoo Kim
Design Lab. – Self Bias Circuit with Temp. Compensation
Schematics
* AMIS 0.5um Tech
(a) Basic Schematic 2/22/2011
(b) actual implementation Insoo Kim
Design Lab. – Self Bias Circuit with Temp. Compensation
Simulation Results
VDD Vr0b
Vr0 (a)
Vr0 (b)
2/22/2011
Insoo Kim
Design Lab. – Self Bias Circuit with Temp. Compensation
Simulation Results – Temp. Compensation 90C 90C
25C 25C
-10C
(a)
(a) -10C (b)
(b)
Vr0 2/22/2011
Current Insoo Kim
Design Lab. – Self Bias Circuit with Temp. Compensation
Zero Temperature Coefficient Point
90C
25C
-10C 0.82V
2/22/2011
Insoo Kim
References
Joongho Choi, “CMOS analog IC Design,” IDEC Lecture Note, Mar. 1999. B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001. Hongjun Park, “CMOS Analog Integrated Circuits Design,” Sigma Press, 1999.
