Current Testable Design of Resistor String DACs Masaki Hashizume†, Tomomi Nishida†, Hiroyuki Yotsuyanagi†, Takeomi Tamesada†, Yukiya Miura‡ ̐:Faculty of Engineering, ‡:Faculty of System Design, The Univ. of Tokushima Tokyo Metropolitan Univ. {tume,yanagi4,tamesada}@ee.tokushima-u.ac.jp,
[email protected]
Abstract In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string Digital/Analog converter(DAC). The results show that all of the shorts and the opens are detected by supply current testing, while opens of the MOS switches are not detected. A DFT method for resistor string DACs is proposed in this paper to detect the opens by supply current testing. Also, testability of a resistor string DAC designed with the DFT method is examined. It is shown that all of the targeted shorts and opens in the testable designed DAC are detected by supply current testing.
1. Introduction DA converters are core elements in mixed signal ICs. Many DA converters have been used to implement AD converters and tested as tests of the AD converters. Until now, many kinds of AD converter test methods have been proposed[1,2]. Also, various kinds of DFT and BIST methods for AD converters have been proposed[3-8]. For example, an ADC and a DAC in an IC are tested simultaneously by connecting the output terminal of the DAC to the input one of the ADC. By providing a digital value to the DAC, the output signal from the DAC is converted with the ADC. By comparing the converted digital value to the input digital one, both the DAC and the ADC are tested[4,5]. However, there are many ICs in which only DACs are implemented without ADCs. In the ICs, tests of DACs are indispensable. Many mixed signal ICs including DACs have been implemented with an SoC technology. Shorts and opens have often occurred in the ICs. However, many DACs have been tested by examining the functionality by a classical test method[2]. It has been difficult to test DACs in the ICs by the test method owing to the
low observability of signals. Furthermore, shorts and opens may not be detected with high coverage by the test method. On the other hand, it has been shown that current testing is useful for detecting shorts in CMOS logic ICs. It is expected that shorts in DACs implemented in an IC are detected easily by current testing like in the tests of CMOS logic ICs. Thus, we attempted to examine testability of shorts and opens in a DAC in order to check the feasibility of DAC testing based on supply current. In our testability analysis, we select a resistor string DAC as a targeted one, since resistor string DACs had been used in many ICs. Furthermore, we attempted to develop a DFT method for such DACs. In this paper, we show testability analysis results of current testing in a conventional resistor string DAC. Also, we propose a DFT method of such DACs for supply current testing. In Section 2, we show the testability analysis results for the conventional DAC. In Section 3, we propose our DFT method and describe the testability analysis results of a testable DAC designed by our DFT method.
2. Supply current tests of resistor string DACs Resistor string DACs have been often used in mixed signal ICs. A resistor string DAC is made of a resistor string and MOS switches. Besides them, an operational amplifier and inverter gates are added to the DAC. An example of the DAC is shown in Figure 1. The DAC is a 3 bit one. Each of the MOS transistors in a DAC acts as a switch. By providing logic values to the primary input terminals, nMOSs are turned on whose gate voltage is H level. Output voltage of the DAC depends on which nMOSs turn on. For example, when B0=B1=B2=H and Rop=RF, the output voltage, VDAO, is defined by Eq.(1). VDAO=(VDD/8Ri)*7Ri (1)
Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA’06) 0-7695-2500-8/05 $20.00 © 2005
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where Ri is the resistance of R1, 㨯 㨯 㨯 , R7 and R8. Output voltage of a resistor string DAC depends on input logical vectors. Moreover, in a defect-free n bit DAC, quiescent supply current, IDDQn, flows from VDD to GND, which is defined by Eq.(2). (2) IDDQn=VDD/(2n*Ri) Since shorts and opens have often occurred in an SoC, we select shorts and opens as targeted faults. In this paper, we assume that the defects occur at resistors in the resistor string and the nMOSs in a targeted DAC. The followings are our targeted defects: a short and an open at a resistor in the resistor string, a short between a drain terminal and a source one in each MOS, opens at a drain terminal and a source one in each MOS. An open may occur at the gate terminal of a MOS. However, they are not included as our targeted defects in this paper, since they will generate various kinds of faulty effects and the faulty effects have not been apparent fully. In our tests, quiescent supply current is measured to detect the defects. If Eq.(3) is satisfied for any test vectors, we determine that a defect occurs in the DAC to be tested. | IDDQC(j) - IDDQn(j) | Ith(j) (3) where IDDQC(j) and IDDQn(j) are the quiescent supply current of a DAC under test and the one of defect-free DACs measured in the j-th test vector application, respectively. Also, Ith(j) is a threshold value, which is used for determining whether the IC is faulty, or not. If Eq.(3) is not satisfied for all of the test vectors, we determine that the IC is fault-free. IDDQn(j) will flow in the defect-free DAC. When a short occurs between terminals of a resistor in the resistor string, larger quiescent supply current will flow
Figure 1. 3 bit resistor string DAC.
than IDDQn(j). Thus, the defect will be detected by Eq.(3). Also, when a short occurs between a source terminal and a drain one in a MOS, a new current path will appear owing to the short in the circuit. For example, when a short occurs between the drain and the source terminals of M10, a current path, Path#3, will appear as shown in Figure 2 and larger supply current will flow than the defect-free DAC. When an open occurs in the resistor string, no supply current will flow. Thus, the open will be detected by Eq.(3). On the other hand, even if an open occurs in a MOS switch, the open will not be detected by Eq.(3), since almost zero current flows into the input terminal of the operational amplifier through the MOS switch in the defect-free DACs. In order to evaluate the feasibility of the current testing experimentally, we designed a layout of a 3-bit resistor string DAC with ES2 0.6μm CMOS process technology. Ri in the resistor string is 625ȍ and VDD is 5V. We converted the layout into a Spice file and derived IDDQn(i) and IDDQC(i) with PSpice. In our experiments, a short is inserted between targeted terminals by adding a resistor of 0.1ȍ between them in the Spice file of the defect-free circuit. An open is inserted to a targeted terminal by adding a resistor of 10 Gȍ to the SPICE file. The results are shown in Table 1. Ith of Eq.(3) used in the experiments is 10% of the quiescent supply current of the defect-free DAC for the j-th test vector application, IDDQn(j). 2 kinds of test vector sets are provided in the experiments. The one is a test set consisting of exhausted test vectors, whose number of
Figure 2. Additional supply current path generated by a short in M10.
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test vectors is 23. The other is a test set consisting of the following 2 vectors: B0=B1=B2=H and B0=B1= B2=L. Table 1. Defect coverage of DAC in Figure 1.
As shown in Table 1, all of the targeted shorts are detected by Eq.(3). Also, the number of defects detected by only the two test vectors is the same as the one of defects detected by the exhausted test vectors. It means that test time can be reduced regardless of bit length of targeted DACs. Also, it is found out from the table that current testing may be effective in tests of DACs. However, opens in the MOS switches are not detected, since almost zero current flows into the input terminal of the operational amplifier. Also, as long as the following equation is satisfied, the shorts will be detected. However, as the bit length of targeted DACs becomes large, all of the shorts may not be detected. VDD[1/(2nRi)-1/{(2n-1)Ri}] Ith(j) (4)
3. DFT of DACs for current testing As shown in Table 1, shorts in DACs will be detected, but opens in MOS switches will not be detected by the current testing based on Eq.(3). It stems that almost zero current will flow through the MOS switches in defect-free DACs and faulty DACs having opens. In order to detect opens in MOS switches of DACs by current testing, we attempted to develop a DFT method for resistor string DACs. Our developed DAC is shown in Figure 3. In our design, a transfer gate, an inverter gate and a resistor, Rp, are added to the conventional DAC. In the normal mode, Tst is H. In the test mode, Tst is L and current through Rp is measured. If the measured quiescent current IRpQC(j) satisfies Eq.(5), the DAC is determined as faulty. | IRpQC(j) - IRpQn(j) | Ithr(j) (5) where IRpQn(j) is current supplied from VDD1 in defect free DACs when the j-th test vector is provided, and Ithr(j) is a threshold value, which is determined from the variation of IRpQn(j). 2 kinds of supply current paths, Path#1 and Path#4, are shown in Figure 3 that appear when B2=B1=B0=Tst=H. If an open occurs in the paths as shown in Figure 4(a), some change in IRpQC(j) will appear and the defect will be detected by Eq.(5).
Figure 3. Our proposed DAC. Similarly, if a short occurs between the drain and the source terminals of M10, a current path appears that is different from the one of the defect-free DACs as shown in Figure 4(b) and the short is detected by Eq.(5). Exhausted test vectors should be provided in tests of the testable designed DAC shown in Figure 3. Because, in order to detect the opens of MOSs, current should be made flow through all of the MOS switches. It results that exhausted test vectors should be provided in tests of our testable DACs. In order to evaluate the testability of our testable DACs, we designed a 3-bit resistor string DAC with ES2 0.6μm CMOS process technology, whose layout design result is shown in Figure 5. The layout is converted into a Spice file and IRpQC(j) is derived for each test vector with PSpice. Opens and shorts are inserted in the same way as in the experiments for the circuit shown in Figure 1. Ithr(j) used in the experiments is 10% of IRpQn(j). The results are shown in Table 2. As shown in Table 2, all of the targeted shorts and opens are detected by Eq.(5). In the case of the testable designed DAC, exhausted test vector application is indispensable for detecting all of the targeted opens. However, by the exhausted test vector application, shorts will be detected even if bit length of targeted DACs becomes large, since both IDDQC(j) and IRpQC(j) flows in the tests and faulty effects in IRpQC(j) caused by a short is enhanced.
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It is our future works to develop how to realize test vector reduction.
Figure 5. Layout of our testable DAC. (a)Open at drain at M9
Table 2. Defect coverage of our testable DAC.
Acknowledgement This research is supported in part by Japan Society for the Promotion of Scientific under Grant in-Aid for Scientific Research(C)(2)(No.15500041).
References
(b)Short between source and drain of M10 Figure 4. Current paths in faulty DACs.
4. Conclusion In this paper, we have examined current testability of shorts and opens in a conventional resister string DAC with a circuit simulator. The results show that defects other than opens in MOS switches may be detected by only 2 test vectors. However, opens in MOS switches will not be detected by current testing. In order to detect them by current testing, we have proposed a DFT method for register string DACs. It is shown experimentally that all of the opens and shorts will be detected in resistor string DACs designed by using the DFT method. Exhausted test vector application is required in tests of the testable designed DAC. It leads to long test time and some restriction in application of the DFT method.
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Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA’06) 0-7695-2500-8/05 $20.00 © 2005
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