A Voltage Mode Integer Divider for Fast A/D Conversion Nikos Petrellis, Michael Birbas, John Kikidis and Alexios Birbas Analogies SA, Patras Science Park, Greece
[email protected]
Abstract- An analog circuit capable of implementing an integer division by a constant number is presented in this paper. The quotient and the residue of the division are generated concurrently by a circuit operating in voltage mode that can be used in various A/D Conversion (ADC) architectures like subrange ADCs as well as signal processing units, neural networks, fuzzy controllers etc. A comparison with an integer divider that was implemented in current mode by the authors shows that the voltage mode implementation leads to higher speed operation due to a better equalization of the quotient and residue path delays of the divider. A fast, low area and power 8bit subrange ADC that has been designed based on the voltage mode integer division architecture is presented as a case study. The comparison of this 8-bit subrange ADC with other similar resolution ADCs shows the advantages of the proposed integer division architecture.
I.
INTRODUCTION
The floating point division is a problem that has been addressed by employing several analog circuit techniques. An interesting approach presented in [1] uses a successive approximation algorithm in conjunction with Analog-toDigital and Digital-to-Analog circuits to achieve a multiplier/divider with 9-bits accuracy. The transistor drain or collector current behavior in various operating regions is also exploited for the implementation of floating point division. Other techniques are based on the inversion of a multiplier operation or the insertion of a multiplier in the feedback path of an inverting amplifier. The analog multipliers that are often based on the Gilbert cell [2] play an important role for the implementation of the floating point division as well. In [3], differential amplifiers and MOS transistors that operate in saturation mode are employed for the implementation of a floating point division by using three identical blocks that add two input voltages and subtract a third one. The input signal range and bandwidth is [0..1V] and 0.5MHz respectively. A two quadrant divider based on transistors operating in weak inversion is presented by the same authors in [4]. A floating point divider that is based on the variable trans-resistance of an operational amplifier and operates at 100MHz input bandwidth has been presented in [5]. This specific divider operates in current mode at ±1.5V voltage supply and consumes 0.22mW. In [6], operational amplifiers and MOS transistors in linear region are used in a configurable multiplier/divider. The translinear principle of the transistors [7] has also been used for the implementation
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of floating point division although these techniques do not produce accurate results if the transistor’s behavior deviates from square law model. To our knowledge the first circuit that implements the integer division of a floating point input by a constant integer was presented by the authors in [8]. The current mode circuit described in this paper generates the quotient and the residue of the division and can be used in an A/D Conversion architecture with binary tree structure that leads to ultra low area and power ADCs. The generated quotient is subtracted by the divider input in order to estimate the residue. The proposed divider architecture can also be used to implement custom ladder-like transfer functions. The current mode operation offers simplified implementation of the arithmetic functions required (addition, subtraction, multiplication/division by a constant) but the resulting implementation has a relatively slow input bandwidth (1MHz full scale input signal). Moreover, the quotient exhibits a certain amount of delay compared to the input signal thus decreasing the residue accuracy since the input signal path delay cannot be increased in current mode operation. A voltage mode implementation of the integer divider that aims to overcome the aforementioned restrictions is presented in this paper. In voltage mode operation it is more difficult to implement arithmetic operations since special purpose operational amplifiers have to be designed with appropriate gain, impedance as well as input range and frequency response. Three differential amplifier alternative designs have been used for the realization of the comparators, the addition and the subtraction required by the integer divider. The gain from the increased complexity is the higher input bandwidth since a 50MHz full-scale input signal can be converted without any missing codes by using a modulo-16 divider. The high speed is owed to the fact that the path delays can be equalized optimally in voltage mode since a signal can be delayed by RC components in this case. This could not be easily accomplished in current mode. The area and the power consumption of the voltage mode integer divider is 0.03mm2 and 9mW respectively. A two-stage 8-bit subrage ADC is briefly described as a case study which consists of two 4-bit flash ADCs that are driven by the quotient and the residue respectively of the integer divider in order to demonstrate its efficiency. A brief description of the current mode integer divider architecture presented in [8] is discussed in Section 2. The voltage mode alternative implementation of the integer
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difference between the divider input and output is a current that is driven into a NMOS current mirror load [8]. If the number of comparators N of Fig. 1 gets too high, the large number of components required can be avoided by substituting a modulo-N divider with a modulo-N1 and modulo-N2 divider connected in series where N=N1xN2. The circuit simplicity is the main advantage of the current mode operation that leads to low area implementation. Moreover, the achieved accuracy and speed can be optimized through a trial and error procedure where the size of the transistors participating in the current mirrors is scaled appropriately. High mismatch immunity can also be achieved if transistors with large channel length and size are used with the cost of slower operation and larger area. The delay needed by the quotient to settle exceeds 10ns if the size of the transistors is large and also depends on the speed of the current comparators used. A more significant problem concerns the residue estimation by equation (4) since the two signals used in the subtraction are not synchronized: the divider output is always delayed compared to the divider input. The difficulty in delay compensation in current mode analog signals results in slower performance of the ADC that employs this type of divider since several invalid transient codes appear at its output.
Vcc
Iref
Iref
Iref Iin 2Iref Iin
( N-1)Iref Iin
Iout
Fig. 1. The current mode integer divider.
divider that is proposed in this paper is described in Section 3. Finally, a subrange ADC based on an integer modulo-16 divider is presented as a case study in Section 4.
II.
CURRENT MODE INTEGER DIVIDER ARCHITECTURE
III.
VOLTAGE MODE INTEGER DIVIDER
The integer divider can be implemented with current mode circuits [8] as shown in Fig. 1. The input current Iin is concurrently compared to the references Iref, 2Iref,…, (N-1)Iref. If
An integer divider implemented in voltage mode has been developed in order to overcome the speed limitations described in the previous section without increasing the required area and power consumption. A voltage mode qI ref ≤ I in < (q + 1) I ref (1) integer divider can be based on the weighted voltage summation configuration presented in Fig. 2. The output of then q comparator outputs force the current of equal current this configuration is [9]: sources to be added at the output. Thus, the output current is Vo = −(V 0 Rf / R 0 + V 1Rf / R1 + ...V N −1 Rf / R N −1 ) (5) I out = qI ref (2) If R0=R1=…=RN-1=Rp and the same voltage Vcom is applied to the input of all these resistors (V0=V1=…=VN-1) representing the quotient q of the division: then (5) becomes: q = I in I ref (3) Vo = − NVcom Rf / Rp (6)
The Iref current sources are implemented using current mirrors while MOS transistors can be used to implement the switches of Fig. 1. The addition of the q reference currents Iref is simply realized by connecting together the switches to the divider output. The residue Ir of the division can be estimated as: I r = I in − qI ref
V0
R1 V1
VN-1
RN-1
Vo
+
(4)
A PMOS current mirror duplicates the input current Iin and a NMOS mirror the divider output. The outputs of these mirrors are connected in order to perform the subtraction. The
Rf
R0
Fig. 2. A weighted summation circuit.
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If
N = ⎣− Vin / Vref
resistors in parallel at the input of the simple differential (7) amplifier shown in Fig. 5. Rptot in this figure represents the total resistance of the parallel Rp resistors of Fig. 3. (8)
⎦
and Vref = Vcom Rf / Rp then Vo = NV ref
(9)
4Vu
Using equation (9) and assuming that N is related to an input voltage Vin as defined in equation (10), then the output Vo represents the integer quotient of the division Vin/Vref. in multiples of Vref. NVref ≤ −Vin < ( N + 1)Vref
3Vu 2Vu Vu
(10)
The circuit that connects the correct number q of parallel Rp resistors according to Vin as dictated by relation (10) appears at Fig. 3. The input voltage -Vin is compared to Vref, 2Vref,…, (N-1)Vref and the q comparator outputs that are high, connect q resistors Rp in parallel. If the output should be the quotient of the division Vin/Vref instead of –Vin/Vref, the inverted comparator outputs should control the switches. An ideal output of such a divider is shown in Fig. 4.
0
Vref
Rp
3Vref
Vcc
R1
Vcom Rp
2Vref
Fig. 4. Ideal divider output (quotient).
I1
I2
R1
R2
Rp
Vo I2'
Vref -Vin
+ R2
Vo-
I1' R3
Rptot
2Vref
Vcom
-Vin
Vcom
(N-1)Vref
Icom
-Vin
R1 Fig. 5. The common mode voltage differential amplifier.
-
Vo
+
Fig. 3. Voltage Mode Integer Divider.
A more accurate large signal analysis can be applied to the circuit of Fig. 5 in order to decide the exact values of the resistors that should be connected in parallel forming Rptot in order to determine the desired relation between the output voltage Vo=Vo+-Vo- and the quotient q that in turn depends on the input Vin. The following relations can be derived if the laws of Ohm and Kirchoff are applied to the circuit of Fig. 5:
The voltage mode integer divider described above uses single ended signals and equations (5) and (6) require ideal operational amplifier to be valid. At the implementation level, a differential input has been applied to differential comparators at the input of the implemented voltage divider. The comparator outputs control the switches that connect the
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I com = ( I1 − I1' ) + ( I 2 − I 2' ) Vcc = Vcom + I1' ( R 2 + R3) + I1R1 Vcc = Vcom + I 2' ( R 2 + R ptot ) + I 2 R1
(11) (12) (13)
Vo = Vcc − I1R1 − (Vcc − I 2 R1) = R1( I 2 − I1)
(14)
Vo = Vcom + I1' ( R 2 + R3) − (Vcom + I 2' ( R 2 + R ptot )) =
The designed ADC consists of a modulo-16 divider at the (15) input, a 4-LSB Flash ADC that is driven by the residue of the I1' ( R 2 + R3) − I 2' ( R 2 + R ptot ) divider and a thermometer to binary encoder that is connected directly to the comparator outputs of the integer divider (Fig. A predetermined output voltage Vo should be generated 7). It should be noted that a full 4-MSB flash ADC could when the input voltage Vin changes in such a way the have been used, driven by the integer divider quotient but this relations (9) and (10) are satisfied. This is achieved by solution would introduce unnecessary redundancy (e.g., 16 connecting a new resistor Rp in parallel (see Fig. 3) and thus more comparators) as well as distortion and latency and modifying Rptot accordingly. In order to define what should be would increase the area and power consumption of the the value of Rp and consequently the value of Rptot for getting system. Vo at the output, the system of equations (12)-(16) can be solved considering as unknown variables the currents I1, I1’, Vcom R3’ I2, I2’ and Rptot. When the value of Rptot is estimated, the value of the resistor Rp that should be connected in parallel Vref is: Vin
Rp = R ptot R 'ptot /( R 'ptot − R ptot )
(16)
2Vref Thermo meter to Binary Encoder
Vin
The parameter R’ptot is the previous value of Rptot (i.e., before connecting Rp in parallel). For example, the levels of Vo can be selected as 400mV, 410mV, 420mV,…, for quotient equal to 0, 1, 2,… respectively (Vref=10mV). These example values are used at the place of Vo in successively solving equations (11)-(16) for the estimation of the resistors Rp. Notice, that Icom, R1, R2 and R3 values should be selected in such a way that negative Rp values should be avoided for the desired Vo output levels. The simulated differential output Vo of such a modulo-16 divider is shown in Fig. 6. IV.
CASE STUDY: A SUBRANGE ADC
15Vref Vin
4 Most Significant Bits
16Vref Vin Common Mode Differential Amplifier Stage of the Integer Divider
Integer Divider (/16)
Quotient Vin/Vref Level Shifter + Delay
Subtr actor
+
4-LSB Flash
ADC Residue of Vin/Vref
Vin
Fig. 7. The 8-bit subrange ADC based on the integer divider.
The described voltage mode integer divider architecture was used for the design of an 8-bit subrange ADC that does not require intermediate track and hold circuits and DACs.
Vcc
quotient input
To subtractor
Vb1 Tcao
Vb2
Fig. 8. The level shifter. Fig. 6. The differential output of the voltage mode modulo-16 divider.
The quotient output of the integer divider should be subtracted from the divider input in order to estimate the residue and drive it to the 4-LSB Flash ADC. A level shifter is used to adjust properly the levels and synchronize the
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divider input and quotient before subtraction. The input signal should be delayed in order to be synchronized with the quotient before the subtraction. The level shifter can be implemented by the circuit shown in Fig. 8. The biasing of the transistors (Vb1 and Vb2) may be subject to calibration for real time level shifting while the NMOS-capacitor Tcap could also be calibrated to ensure the correct synchronization of the divider input and output for different input signal frequencies. The maximum frequency, in order to avoid missing quotient levels, of the full scale sawtooth input signal that the modulo-16 divider developed for this subrange ADC can accept as input is 50MHz instead of 1MHz that was the case for the current mode ADC implementation of [8]. This (maximum) frequency depends on the speed of the voltage comparators used. The supply voltage of this divider is 1.2V and the dissipated power less than 9mW while the current mode divider implementation of [8] dissipated 13-19mW. The area occupied by the voltage mode divider is 0.03mm2 where the corresponding current mode divider occupied 0.022mm2. The mismatch and process variation effects are more severe in the voltage mode implementation due to the fact that the current sources used in the differential amplifiers are implemented with transistors biased at a precise voltage level. A slight variation in these transistor sizes or a temperature change results in a large difference regarding the current that they dissipate. This problem can be handled in real time by a calibration method that controls the biasing of the transistor implementing the current source Icom of the Common Mode Differential Amplifier of Fig. 5. The features of the developed 8-bit ADC are presented in Table 1 along with some other ADCs of similar resolution for comparison reasons. As it can be seen from this table, the developed ADC requires an order of magnitude lower die area and dissipates the lowest power from all the referenced ADCs. TABLE I 8-BIT ADC COMPARISON Ref.
Resolution 8-bit
Sampling Speed >1GS/s
Power mW 20
Area mm2 0.04
This Work [10] [11]
8-bit 8.9(ENoB)
71MS/s 320MHz
205 32
? 0.44
[12] [13] [14]
8 8 8
125MHz 250MS/s 100MHz
? 57 150
0.32 0.12 ?
V.
SNDR 32dB @20MHz ? 54dB @10MHz ? ? ?
CONCLUSIONS
for the development of an 8-bit ADC that achieved a very low area and power consumption compared to other ADCs with similar resolution. Future work will focus on developing ADCs with higher resolution based on the presented integer divider architecture. Moreover, appropriate real time calibration techniques will be developed for handling the mismatch and process variation problems. ACKNOWLEDGMENT This work was supported by Analogies S.A. and is patent pending (Application No. PCT/GB2009/051101). REFERENCES [1] I. Baturone, S. Sanchez-Solano and J. Huertas, “CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers,” Analog Integrated Circuits and Signal Processing 23, Kluwer Academic Publishers, pp. 199-210, 2000. [2] B. Gilbert, “A precision four-quadrant multiplier with nanosecond response,’’ IEEE Journal on Solid-State Circuits, vol. SC-3, pp. 353365, Dec. 1968. [3] S. I. Liu and C. C. Chang, “CMOS Analog Divider and Four-Quadrant Multiplier Using Pool Circuits,” IEEE Journal of Solid State Circuits, Vol. 30, No. 9, pp. 1025-1029, Sep. 1995. [4] C. C. Chang and S. J. Liu, “Weak Inversion Four-Quadrant Multipler and Two Quadrant Divider,” Electronic Letters, Vol. 34, Oct. 1998. [5] W. Liu, S. I. Liu and S. K. Wei, “CMOS Current-Mode Divider and Its Applications,” IEEE Transactions on Circuits and Systems-II Express Briefs, Vol. 52, No. 3, pp. 145-148, Mar. 2005. [6] M. Ismail, R. Brannen, S. Takagi, N. Fujii, N. Khachab, R. Khan and O. Aaserud, “Configurable CMOS Multipler/Divider Circuit for Analog VLSI,” Analog Integrated Circuits and Signal Processing 5, Kluwer Academic Publishers, pp. 219-234, 1994. [7] A. Lopez-Martin and A. Carlosena, “Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle,” Analog Integrated Circuits and Signal Processing 28, Kluwer Academic Publishers, pp. 265-278, 2001. [8] N. Petrellis, M. Birbas, J. Kikidis and A. Birbas, “Analog Current Quantizer Architectures for Implementing Integer Division-Like Functions”, Proceedings of the IEEE DSP’09, July 7, 2009, Santorini, Greece. [9] A. Sedra and K. Smith, “Microelectronic Circuits,” 5th Edition”, Oxford University Press. [10] C.Y. Wu and Y.Y. Liow, “New Current-Mode Wave-Pipelined Architectures for High-Speed Analog-to-Digital Converters,” IEEE Transactions on Circuits and Systems I, Vol. 51, No. 1, pp. 25-37, 2004. [11] J. Arias, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D. Bisbal, J. S. Pablo, L. Quintanilla, and J. Barbolla, “A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers,” IEEE Journal of Solid State Circuits, Vol. 41, No. 2, pp. 339-351, 2006. [12] X. Guo, C. Chen and J. Ren, “An 8-bit 125MHz Folding and Interpolating ADC,” Proceedings of the 4th International IEEE ASIC Conference, pp. 293-295, 2001. [13] K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, “A 20GS/s 8b ADC with a 1MB Memory in 0.18µm CMOS,” Proceedings of the IEEE International Solid-State Circuits Conference, 2003. [14] H. Dinc and F. Maloberti, “An 8-bit Current Mode, Ripple Folding ADC,” Proceedings of the IEEE ISCAS’03 Conference, pp. I981-I984, 2003.
A voltage mode implementation of an analog divider by a constant number was presented in this paper showing a better performance in terms of speed, power consumption and die area, compared to the current mode implementation that was presented by the authors in [8]. This integer divider was used
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