Decoupled Carrier and Bit Clock Synchronizing ... - Semantic Scholar

LOZHKIN : DECOUPLED AND BIT CLOCK SYNCHRONIZING SUBSYSTEMS IEICE TRANS. COMMUN.,CARRIER VOL. E82-B, NO. 9 SEPTEMBER 1999 1459

PAPER

Decoupled Carrier and Bit Clock Synchronizing Subsystems for the Coherent MSK/GMSK Receiver Alexander N. LOZHKIN†, Student Member

SUMMARY In digital modulation for mobile radio telephone services frequency modulation with continuous phase with small modulation indices (MSK/GMSK) is sometimes used. Extension of the synchronization subsystems’ pulling band in a coherent receiver and reducing synchronization delay is important for the mobile communication. At this moment there are only two possible synchronization schemes for the coherent MSK/GMSK receiver: Costas and de Buda’s. This paper presents a new method (a possible alternative to both of them) where the frequency discriminator with decoupled carrier and bit synchronizing subsystem are combined to handle the task. For comparison, this paper also describes performances of the Costas carrier recovery scheme, which is widely employed for MSK/GMSK coherent demodulation. Discrimination and fluctuation characteristics for frequency, phase, and symbol delay synchronization subsystems are shown and the BER degradation from the conventional Costas scheme is calculated. This paper demonstrates with simulation results that the proposed scheme improves RF carrier acquisition performances, and at the same time, for large signal-to-noise ratios (SNR’s) provides similar or better tracking performances than the Costas one. While limited to higher SNR ratios, the proposed synchronization scheme is suitable for many applications and can be implemented with simpler circuitry, well suited to integrated circuit implementation. key words: MSK/GMSK modulation, coheren FM receiver, frequency/phase detector

1. Introduction There are various radio systems for the short-wave (SW) and ultra short-wave (USW) ranges that employ mainly analog FM for mobile radio communication. However, in order to provide highly secure and high-speed data transmission by the use of IC/LSI transceivers, digital mobile radio transmission is currently being studied [1], [2]. While digital transmission can surely bring many advantages, some technical problems must be solved. This paper is concerned with a coherent MSK/GMSK digital demodulator designed especially for mobile radio communication. When realizing such an orthogonal coherent detector, one of the most important and difficult problems is how to recover the reference carrier and bit-clock. In this paper, the time interval analysis between the quadratures sign changes is proposed as an effective method for the carrier frequency, phase errors and bit clock delay calculation; and discriminators’ noise performances are analyzed with the aid of machine computation. This paper comprises six sections. First, problems with bit-clock coupled synchronizing systems are addressed, and relationships beManuscript received June 4, 1998. Manuscript revised November 11, 1998. † The author is with the MECC Co. Ltd. Japan, Ogori-shi, 838-0137 Japan.

tween RF carrier frequency error, phase error, bit-clock error and MSK/GMSK-signal’s quadrature components are made clear. Then constructions of the coherent demodulator’s frequency (FD), phase (PD) and bit clock discriminators (BCD) are discussed, and noise performance evaluation of the proposed scheme is made with comparison to the Costas loop. Finally, the BER degradation performance from the conventional Costas scheme is calculated, and the required SNR range, where the proposed scheme provides performance which is similar or better than the Costas scheme, is shown. 2. Conventional Systems and Their Problems For coherent signal detection it is necessary to calculate the error signals in the carrier frequency Zω and phase Zϕ , and information data delay Zτ relative to the bit-synchronizing instants, formed by the reference oscillator in order to synchronize the demodulator. The most typical method for the carrier and bit clock recovery is de Buda’s [1]. In his method, the reference carrier is recovered by dividing the sum of the two discrete frequencies contained in the frequency doubler output by four, and the bit clock is directly recovered by their difference. Major shortcomings of the demodulator [1] have some difficulties in realizing such schemes as frequency doublers, PLL and mixers, using conventional digital logic or LSI. The modified de Buda’s method based on the well-known Costas loop as a carrier recovery circuit can easily be implemented by conventional digital logic circuits. This configuration is considered to be especially suitable for the mobile radio unit which must be simplified, miniaturized and economized [2]. It has been shown [1], [2] that recovering the reference carrier and timing clock for MSK/GMSK signal coherent demodulation can be provided by using de Buda’s method, or by using demodulators with coupled carrier and bit-clock synchronization subsystems (modified Costas loop) (Fig. 1(a)). Those circuits have substantial shortcomings: a narrow pulling bandwidth in the FM demodulator when there is a frequency offset between the receiving signal, and the reference and long delays in the initial synchronizing to the carrier and bit clock synchronization. For example, in the case of de Buda’s method, it is necessary to find some compromise between PLL’s bandwidth, reference oscillation quality and time consumption for initial synchronization [1]. In the case of the more popular modified Costas loop [2], such problems become more serious because of a coupled carrier and

IEICE TRANS. COMMUN., VOL. E82-B, NO. 9 SEPTEMBER 1460

bit clock PLL implementation in Fig. 1(a). Even if there are no errors in bit synchronization, a PLL system for the frequency search and locking can be of low performance, particularly with frequency differences larger than the noise bandwidth of PLL [3]. The example of Fig. 1(b) illustrates how an average modified Costas PD’s output signal (MSK-modulation, SNR=10, wideband input BPF) depends on the bit-clock signal error from the “Clock Recovery” circuit (Fig. 1(a)) for bit-clock delays τ = 0; T / 4; T / 8 and T / 2 (T is the information symbol duration), indicating that modified Costas PD’s gain changed approximately by 10 times or by 10 dB. In [3] it is shown that for a high-gain loop, the pull-in time is 2 defined by a phase detector gain K p d as 1 / K p d . Bit synchronization errors during entry to synchronism are inevitable, And entry to synchronism in frequency and phase may be significantly delayed. Since the bit synchronization errors distort the discrimination characteristic in the carrier tracking loop, if the errors in the bit synchronizing subsystem are large, there may even be a change in the sign of the error signal at the carrier phase discriminator. The pull-in can be a painfully slow process in a narrowband loop. If the input signal-to-noise ratio is large enough, a frequency discriminator can be used in a conventional PLL to bring the VCO fre-

(a)

< Zϕ >

quency close to that of the signal. Pull-in time is reduced substantially, but there has been little practical application of this technique, because of the required extra circuitry and difficulties in digital realization [3], [4]. Another problem, which is due to synchronization in the coherent demodulator [2], is spurious locking. The carrier phase error signal is Zϕ = X ( t ) ⋅ Y( t ) ⋅ R( t ) , in which X (t ) is the sign of the inphase signal, while Y (t ) is the sign of the quadrature signal, and R( t ) is the half-bit clock frequency. If there is a phase error ∆ϕ , the mean value of the error signal < Zϕ > will be proportional to ∆ϕ only in cases where the error in the bit clock tracking loop is zero. The mean value of the < Zϕ > error signal is calculated in the “Loop Filter” in the carrier tracking loop (Fig. 1). If there is a frequency difference ∆ω , the frequency pulling is provided by the same phase tracking loop. If the loop has second-order, fr equency differences such as ∆ω = n ⋅ R(t ), (n = 1, 2, 3... integer) result in the mean value of the error signal < Zϕ > becoming zero, as a product of multiplication by R( t ) . This is the cause of spurious locking. To eliminate the latter, constraints must be imposed on the frequency differences [4]. These shortcomings become more important when such demodulators are used for mobile communication, and are characteristic of any system that has coupled carrier and bit synchronizing subsystems. One should decouple these subsystems. At the moment, there are two possible synchronization schemes for the coherent MSK/GMSK receiver: Costas’s [1] and de Buda’s [2]. This paper describes a possible alternative to both of them. We briefly reported the idea of the decoupling carrier and bit-clock synchronization subsystem for coherent MSK/GMSK-signals demodulator in [5]. This paper presents a detailed description of the system and its noise performance, including the RF carrier and the bit clock discriminators constructions; FD, PD and BCD noise performance; the evaluation of those performances with comparison to the modified Costas Loop; as well as the BER degradation feature.

Delay =0

3. The Receiving Signal Model

Delay=T/8

The digital FM demodulator was designed for MSK/GMSKsignals coherent demodulation. The input RF signal s( t ) at the coherent FM receiver’s input is the FM signal with the continuous phase described by:

WideBand BPF SNR=10.0

Delay=T/4 Delay=T/2

∆ϕ deg. (b) Fig. 1 (a) Modified costas loop. (b) Modified costas PD characteristics with bit-clock delay as a parameter.

(

t

s(t ) = A ⋅ cos ω 0t + ∫ Ω / 4 ⋅ D(t )dt + ϕ 0 0

)

where A is the amplitude. ω 0 is the carrier frequency. Ω = 2π ⋅ FT . FT = 1/ T is the bit frequency, T is the duration of the cycle, which is equal to the length of information symbol. D( t ) is a sequence of information symbols with a square waveform and length T , whose amplitude takes the value + 1 or – 1. ϕ 0 is the initial phase. An excellent way to view the situation is to draw a phasor

LOZHKIN : DECOUPLED CARRIER AND BIT CLOCK SYNCHRONIZING SUBSYSTEMS 1461

diagram in the rotating plane with an angular speed ω 0 as in Fig. 2. A harmonic signal with angular frequency ω 0 and constant phase is represented in this plane as an stationary vector (Fig. 2). That vector rotates when the phase or frequency changes. In Fig. 2 additional axes v and w are introduced. These axes will be specified later during the frequency and phase error calculation section. With frequency modulation with modulation index 0.5 (MSK-signal), the phase shift during an information symbol (duration T ), is precisely equal to ± π / 2 (the sign is governed by the sign of the modulating information symbol). If the modulating signal is represented by a sequence of pulses having the same sign, the vector, that represents the MSK signal, rotates with an angular frequency of π / 2T . In the GMSK-modulation case, the output voltage from the Gaussian LPF-filter is constant for a modulating signal as a series of pulses of the same sign [2]. Here the GMSK-signal does not differ in any way from the MSK one. The difference between

GMSK and MSK appears during the modulation by signvarying data. Figure 3 shows the vector diagrams and corresponding projections for the MSK and GMSK signals (without noise). The MSK-signal vector, for zero initial phase, oscillates around the axis v if the data sequence has the form +1,–1,+1,–1... . The GMSK-signal vector also oscillates, but with a scale (aperture) less than for MSK. In these diagrams, the point, corresponding to the vector’s end, moves in general around in a circle, but to display the motion in time, a spiral motion is used. The later positions correspond to larger radii. The position of the moving point is uniquely defined by X and Y . Those quadrature components in the case of the GMSK-signal are smoothed, which reflects the fact that the level of high-frequency components in a GMSK-signal is lower than in an MSK-signal. Correspondingly the radiation outside the sideband is also lower. The MSK- and GMSK-signals in the receiver pass through BPF, in which the high-frequency components are suppressed. Then the quadrature components for MSK at the output from the bandpass amplifier are smoothed, and the smoothing is most pronounced if the quadrature filters are matched. There is a marked similarity between the MSK and GMSK signals after filtering in the receiver, which is the basis for using the same receiver for MSK and GMSK signals. This is the reason why the same receiver is assumed for both MSK and GMSK signals. 4. Discriminators for the Coherent Demodulator

Fig. 2 Phasor diaphragm (x,y,v,w-plane).

Fig. 3

MSK and GMSK signals quadrature components.

For coherent signal detection it is necessary to calculate the error signals in the RF carrier (frequency Zω and phase Zϕ errors), and information data delay Zτ relative to the bit-synchronizing instants, formed by the reference oscillator. We can use a time interval analysis between the axes intersection in order to detect error signals. Figure 4(a) shows the coherent demodulator which has an independent subsystem for carrier and bit synchronization. The demodulator consists of input BPF, Quadrature Converters (QC1 and QC2), reference generator, Logical Signals Analyzer (LSA), Time Interval Gauge (TIG), Carrier PLL (VCO and LPF), Frequency Detector (FD), Phase Detector (PD), Bit Clock Delay discriminators (BCD), bit clock PLL and Symbols Demodulator that regenerate the information signals. Figures 4(b) and 4(c) show the QC1, QC2 and Symbols Demodulator structures. The Symbols Demodulator, QC1, QC2 and Bit Clock PLL are similar to the ones in the coherent MSK/GMSK detector reported in [2]. Additional mutually orthogonal reference carriers v , w are introduced in Fig. 4. These references become shifted corresponding to the x and y by π / 4 , and can be generated by the use of additional D flip-flops. The VCO center frequency is then set equal to eight times the carrier center frequency [2], [3].

x = cos(ω 0 t + ϕ 1 ) v = cos(ω 0 t + ϕ 1 + π / 4)

IEICE TRANS. COMMUN., VOL. E82-B, NO. 9 SEPTEMBER 1462

(a) D

Q

X or V

X

D

Q XOR

T

T

Data XOR

s^(t)+n^(t) D

Q

Y or W

Y

T

Q

T

x or v

y or w

(b) Fig. 4

D

FT / 2 (c)

(a) Coherent MSK/GMSK demodulator. (b) QC1 and QC2. (c) Symbol demodulator. (d) Logical signals analyzer output signals (without noise).

y = sin(ω 0 t + ϕ 1 ) w = sin(ω 0 t + ϕ 1 + π / 4) where ω 0 is the local oscillator carrier frequency. ϕ1 is the local oscillator initial phase. The additive mixture of the input signal s( t ) and white Gaussian noise n( t ) passes through BPF to the QC1 and QC2, which produce the quadrature components X , Y , V and W .

X = sign[( s^ (t ) + n ^ (t )) ⋅ cos(ω 0 t + ϕ 1 )] V = sign[( s^ ( t ) + n ^ ( t )) ⋅ cos(ω 0 t + ϕ 1 + π / 4)] Y = sign[( s^ (t ) + n ^ (t )) ⋅ sin(ω 0 t + ϕ 1 )] W = sign[( s^ ( t ) + n ^ ( t )) ⋅ sin(ω 0 t + ϕ 1 + π / 4)] Here sign[x ] - is the sign function, which takes the values 1 and 0 in accordance with the sign of the argument and s^ ( t ) + n ^ (t ) represents the additive mixture of the input

signal s( t ) and white Gaussian noise n( t ) at the the receiver BPF output (Fig. 4(a)). When frequency, phase and bit-clock errors are near zero (RF carrier and bit-clock PLLs are in the tracking mode), the Symbol Demodulator (Fig. 4(c)) is able to detect information data. Here the coherent MSK/GMSK demodulator (Fig. 4(a)) and its operation are not different in any way from the MSK/GMSK demodulator reported in [2]. The difference is in the way frequency, phase and bit-clock errors are calculated. For frequency error signal Zω , phase error signal Zϕ and bit clock error signal Zτ detection we have decided to use a signal vector movement analysis, and a time interval measurement between the two axis intersections. For signal vector position and its movement description, we chose a set of four logical signals: “Intersection Axes,” “Axis x,y/v,w,” “Adjacent Axes” and “Clockwise movement.” This set is produced by the LSA (Fig. 4(a)) by means of quadrature components sign logical analysis in time.

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MSK-signal quadrature components X,Y,V and W smoothed in the matched filter

X

Y V W Intersection Axis TIG Content Adjacent Axis Axis xy/vw Counter Clockwise movement 0

T

2T 3T 4T 5T 6T 8T 9T

etc.

time

t

(d) Fig. 4

4.1

Logical Signals Analyzer (LSA)

Logical signal “Intersection Axes” assert high every time the quadrature components X , Y , V or W change sign, i.e. when the input signal vector intersects some axis. For example, recalling Fig. 3, if the W quadrature component changed sign, it meant that the v axis was intersected, and so on. Logical signal “Axis x,y/v,w” defined which axis system (x , y ) or (v , w ) was intersected. This signal assert high for the v , w axis and low for the x , y . Logical signals “Adjacent Axes” and “Counter Clockwise movement” reflect the input signal vector rotation. Under “Adjacent Axes” we assumed the axis which is adjacent to the last intersected one. For example, if the v axis was intersected, x , y axis are became “Adjacent Axes” to the v . This signal reflects a signal vector movement (rotation or oscillation) and can be generated by the use of two adjacent “Axes Intersection” signals logical analysis. The “Adjacent Axes” signal asserts high every time the adjacent is axis intersected. For example, if the same quadrature component changes back to its original sign, it means that the same axis was intersected again. In this case, the input signal vector oscillates around the same axis and the “Adjacent Axes” signal asserts to the low level. Logical signal “Counter Clockwise Movement” reflects the input signal vector rotation direction. This signal asserted high for the input signal vector’s counter clockwise movement and low for the clockwise movement. If at the first, for example, the W quadrature component changes sign, and then the X quadrature component changes sign, it means that the

(Continued)

input signal vector has moved in counter clockwise direction. Figure 4(d) represents a screen hardcopy during simulation (without noise). It illustrates the logical signal analyzer’s output signals, and their relationship with quadrature components X , Y , V and W , in the case when information data sequence has the form “–1+1+1–1–1+1–1.” All mentioned above logical analysis can be generated by the use of modern LSI or FPGA. 4.2

The Frequency Discriminator

As was mentioned before, the major shortcomings of the demodulator [2] are long synchronization times and spurious locking, which are due to the use of coupled carrier-phase tracking synchronization loops. The method of affecting RF carrier acquisition in the narrow band PLL is to add an FD to the traditional PLL PD in the manner described in [6]. With a large initial frequency error, the PD output has essentially a zero dc output. In this case, FD generates a voltage proportional to the frequency difference between input and reference, driving that difference to zero. The PD takes over when the frequency difference is small, completing the acquisition. When the PLL is in-lock, the FD output will have at least zero mean, automatically allowing the PD and its loop filter to govern the loop dynamics. For frequency error signal Zω detection, we have decided to use a time interval analysis between two successive intersections. The modulating signal is represented by a sequence of pulses, having the same sign, for example +1. In this case, input signal frequency will be equal to ω 0 + π / 2T

IEICE TRANS. COMMUN., VOL. E82-B, NO. 9 SEPTEMBER 1464

and the vector s( t ) will rotate in the vector diagram Fig. 5 in a counter clockwise direction, with a nominal angular frequency π / 2T (Fig. 5). If there is no frequency error, the time between two successive intersections of adjacent axes ∆Tadj = t *2 − t1* can be found from Ω ⋅ ∆Tadj = π / 4 and will be exactly T / 2 . For time measurements between intersections of adjacent axes, the counter shown in Fig. 6 can be applied. This is a convenient counter with “Clear” and “Count” inputs. This counter provides the time interval measurement between the intersections of the axes (Fig. 5). When the axes are intersected, an “Intersection Axes” signal asserts high and provides a counter reset to zero (Figs. 4(d), 6). Additional mutually orthogonal reference carriers v , w are introduced in Fig. 4. These references become shifted corresponding to the x and y by π / 4 , and can be generated by the use of additional D flip-flops. The VCO center frequency is then set equal to eight times the carrier center frequency [2], [3].

x = cos(ω 0 t + ϕ 1 )

v = cos(ω 0 t + ϕ 1 + π / 4) y = sin(ω 0 t + ϕ 1 )

w = sin(ω 0 t + ϕ 1 + π / 4) where ω 0 is the local oscillator carrier frequency.

ϕ1 is the local oscillator initial phase. The number in the counter N i , just before this moment, is proportional to the time duration between axes intersections, i.e. t1* − t2* , t2* − t3* . If there is no frequency discrepancy, the output value w

t N3 t

* 3

ω0

y

N2

v

t

* 2

* 4

N4

s(t )

N1

N T t1*

t 5*

x

∆Tadj Fig. 5

from counter N i , i = 1, 2, 3... will be equal to N T / 2 , where N T = T ⋅ Fclock is the number of pulses that the TIG counter will count for the time interval T , which is equal to the information symbol duration, while Fclock is the frequency of the TIG clock oscillator. If there is some frequency error ∆ω , the input signal vector s( t ) will rotate in the vector diagram (Fig. 5) with an angular frequency of π / 2T +∆ω . Depending on the frequency error sign, time between two successive * adjacent axes intersections ∆Tadj now will differ from T / 2 * (for ∆ω > 0 , ∆Tadj < T / 2 - signal vector angular speed is greater than nominal π / 2T and the vector rotates faster; for * > T / 2 - signal vector angular speed is less ∆ω < 0 , ∆Tadj than nominal π / 2T and the vector rotates slowly). Consequently, the value at the TIG counter output will be less (more) than N T / 2 . Because of the linear relationship between vector angular speed and angular path on the phasor diagram (Fig. 5), the difference Zω = N i − N T / 2 will be proportional to the frequency error ∆ω . If the modulating signal is represented by a sequence of negative pulses –1, the input signal frequency will be equal ω 0 − π / 2T , and the vector s( t ) will rotate in the vector diagram (Fig. 5) in a clockwise direction, with an angular frequency of –π / 2T . If there is a frequency error, the time * between two successive axes intersections ∆Tadj will differ * from T / 2 (for ∆ω < 0 ,∆Tadj < T / 2 and for ∆ω > 0 , * ∆Tadj > T / 2 ). Note that in contrast to the positive pulse modulation, for the negative pulse modulation, positive fre* quency error ∆ω > 0 increases ∆Tadj ; meanwhile, the negative ∆ω < 0 decreases. In both cases, the difference Zω = N i − N T / 2 is still proportional to the frequency error ∆ω value. The difference between the two cases is in the signal vector rotation direction. For the positive modulation, positive frequency error ∆ω > 0 will increase the signal vector angular speed, while in the case of negative modulation, it will decrease. For the correct frequency error calculations, it is necessary to change the sign of the difference Zω = N i − N T / 2 to the opposite for the negative pulse * < T / 2 will modulation. After such sign correction, ∆Tadj correspond to the positive frequency error ∆ω > 0 , and * ∆Tadj > T / 2 to the ∆ω < 0 , as it was in the positive pulse modulation case. Such correction can be done by examining the input signal s( t ) rotation direction. If the rotation direction is counter clockwise, no correction for the sign is re-

Frequency error calculation. Counter Output

Ni Counter

Intersection Axes Clear

Ni

Output Count

CLOCK

t

Intersection Axes

t

Clock

Fclock t

t1* Fig. 6 Time interval gauge (TIG).

t 2*

t 3*

t 4*

LOZHKIN : DECOUPLED CARRIER AND BIT CLOCK SYNCHRONIZING SUBSYSTEMS 1465

quired. If the rotation is clockwise — the sign Zω = N i − N T / 2 should be inverted. Figure 7 shows the frequency discriminator block diagram. The value Ni (the numbers of the pulses from the TIG counter, i = 1, 2, 3, ...) from the TIG output is written to the memory cell when “Intersection Axes” signal is asserted high (time moments t1* , t2* , t3* , t4* , t5* at the Fig. 5). The sub-tractor calculates the difference ∆N = Nj − NT / 2. The difference ∆N is passed through the controlled invertor. At this point, the sign of the ∆N is changed to the opposite, if the signal “Counter-Clockwise movement” is asserted low (clockwise signal vector rotation). This procedure provides the above mentioned sign correction for the frequency error signal. If the signal “Adjacent Axis” is asserted high (signal vector rotation at the vector diagram with an angular frequency of ±π / 2T + ∆ω ) and condition ∆N < N TH (where N TH is the comparator threshold level) is true, the frequency error signal Zω which has a corrected sign, passes through the switch to the frequency discriminator output. The condition ∆N < NTH restricts operation of the FD to a subset of the frequency errors values. This subset can be unambiguously identified in the face of rotation. For example, for the MSKsignal, restriction to the N T , for example, selection NTH = N T , which was assumed during simulation, corresponds to the frequency error operation range ∆ω restricted by FT / 4, or 25% of Bit-Clock frequency. All frequency discriminator elements can be made without the use of expensive analog RF/IF circuitry. The FD is characterized by mean value Zω at its output, since the mean value serves to charge or discharge the integrating capacitor in the loop filter [6]. Figures 8(a), (b) and 9 show the machine-computed discrimination (the mean value of the frequency error signal Zω at the discriminator output) and the fluctuation (the variance D[Zω ] of the error signal at the discriminator output) characteristics for various SNR (the ratio of signal power to noise power at the BPF output) values. At the simulation, the MSK matched filters were assumed (Fig. 4(d)), F clock = 64 ⋅ FT and thereby NT = 64. Because BPF matched filter is used, SNR at the sampling instant equals to Eb / N0 where Eb / N0 is the en-

ergy-per-bit to noise spectral density ratio [7]. The fluctuation and discrimination characteristics are presented for the same normalizing factor N T / 2. As shown in Figs. 8 and 9, the FD output has a mean of zero for the ∆ω = 0, which automatically allows the PD and its loop filter to govern the loop dynamics. At the same time, it provides a non-zero slope for ∆ω ≠ 0, even for small values of SNR. There is no restriction for frequency deviations ∆ω that should be used for a conventional modified Costas loop or

SNR=10 SNR=5

Zω SNR=0.5 SNR=1

∆ω / Ω (a)

N TH = N T

N TH = 2 ⋅ N T SNR=10

Zω N TH = N T / 2

∆ω / Ω (b) Fig. 8 (a) Frequency discriminator. Discrimination characteristic. (b) Frequency discriminator. Discrimination characteristic with comparator threshold as parameter. SNR=0.5 SNR=5

SNR=1

D[Zω ] SNR=10

∆ω / Ω Fig. 7 Frequency discriminator.

Fig. 9 Frequency discriminator. Fluctuation characteristic.

IEICE TRANS. COMMUN., VOL. E82-B, NO. 9 SEPTEMBER 1466

Rotation Frequency Detector due to spurious locking [4], [6]. The FD’s frequency acquisition region can be selected and adjusted by setting threshold value N TH at the second comparator input (Fig. 7). Such selection affects the FD gain factor and the frequency acquisition region (Fig. 8(b)). During simulation, the value N TH = N T was assumed. This demodulator was especially designed for FDMA system. A frequency acquisition region wider than F T / 4 may lead to locking onto an adjacent channel. This selection is very flexible, and frequency acquisition region and FD’s gain factor can be adjusted by choosing a value NTH which is different from N T . As an illustration, Fig. 8(b) represents an FD discrimination characteristic for N TH which is equal to NT / 2, N T and 2N T respectively. All characteristics have been constructed for frequency deviations ∆ω that are less than half of the information symbol frequency Ω = 2πFT, but generally, the above described FD is able to detect frequency deviations exceeding half the information symbol frequency. 4.3

Phase Detector

The above described time interval analysis can be applied to the carrier phase error signal calculation. Assume that the modulation by sign-varying data is given...+1–1+1–1... . In this case the input MSK-signal vector s( t ) for zero initial phase will oscillate around the v axis (from 0 to π / 2 and back again). The GMSK vector also oscillates, but with a scale less than for MSK (Fig. 3). If there is no phase error, i.e. ∆ϕ = 0, the time between * * two successive intersections of the same axis ∆Ts = t2 − t1 , * * t3 − t2 , etc. can be found from ∆T s = π / 2Ω, and will be exactly T (the nominal value). Now consider what happens if there is some phase discrepancy: the input signal vector will continue to oscillate around the same axis, but the oscillation center (dashed line in Fig. 10) will shift on ∆ϕ in coherence with v axis. Figure 10 shows that the difference in * * * * the duration= t2 − t1 ( N1 ) and t3 − t2 ( N 2 ) contains information on the phase error ∆ϕ (strictly pertaining to the modules of the phase error), provided that the same axis is always intersected. For the time interval measurements, the TIG scheme shown in Fig. 6 can be successfully applied. From Fig. 10 the phase error can be determined no matter whether there is an error at the bit clock synchronization or not (the bit clock instants are not necessary for the time interval measurements). This leads to the carrier phase tracking loop which is decoupled with the bit clock. The sign of the phase difference between the received and reference signals can be determined by the logical examination of the sequence of signs of the X, Y, V, W quadrature components. The sign of the phase error is taken as the direction (clockwise or counter clockwise) in which the same axis is intersected (the v axis here in Fig. 10). In the synchronous mode, the intersection is for either the v or w axis, not x and y; therefore the sign of the phase error signal is generated on the basis of the axis system feature: plus (+) if the v or w axes are intersected, and minus (–) if x and y. Figure 11 shows the phase discriminator block diagram.

The phase discriminator structure (Fig. 11) is similar to the frequency discriminator structure (Fig. 7). The main difference is that the discriminator output signal Zϕ passes through the switch to the discriminator output if the same axis is intersected a second time (input signal vector oscillates around the same axis as shown in the Fig. 10) and if condition * * is true. During simulation, NTH = 2 NT was as∆ N < NTH sumed. The last condition (as it was for the frequency discriminator) guarantees that time interval between the same axes intersection does not exceed 2T. Such restrictions let us avoid abnormal errors in the carrier PLL loop. The PD is characterized by mean value Zϕ at its output. The PD’s noise output is defined by PD’s output signal variation D [Zϕ ] [3]. The proposed PD performance has been evaluated by computer simulation. The modified Costas scheme has also been examined for comparison. Figures 12 and 13 show the machine-computed discrimination Zϕ and the fluctuation D [Zϕ ] characteristics for various values of SNR for both PDs. On these plots, results obtained for the modified Costas PD are properly scaled to the proposed PD gain factor (such that both PDs have the same gain factor), and plotted against proposed PD fluctuation and discrimination characteristics. The fluctuation and discrimination characteristics for both PDs

Fig. 10 Phase error calculation. Adjacent Clockwise Axis movement Invertor

Axis x,y/v,w

Intersection N From Time Axes Interval Gauge

Logic circuit Memory Cell

N

Memory Cell

N *TH

sign correction Controlled Invertor

Comparator

∆N < N

* TH

∆N

Memory Cell

AND Gate

NT switch

Zϕ

Fig. 11 Phase discriminator.

LOZHKIN : DECOUPLED CARRIER AND BIT CLOCK SYNCHRONIZING SUBSYSTEMS 1467

are presented for the same normalizing factor N T . These characteristics are drawn in the case when tracking errors at the bit clock subsystem are zero. The points that correspond to the different delays in the bit clock tracking loop for the same phase error value are not shown on plots Figs. 12 and 13, because (if the statistical tolerance can be neglected) the exact same data for the different delays in bit clock tracking loop were obtained for the proposed PD. The results of the simulation show that, in contrast to the modified Costas scheme (Fig. 1(b)), the proposed PD provides a constant gain factor which only depends on the input SNR. There is no discrimination characteristic shape distortion in the phase tracking loop, even if the errors in the bit clock synchronization subsystem are large (more than 25% from symbol duration). Therefore, the pull-in time, especially for initial synchronization, can be considerably reduced. When accompanied by the frequency discriminator, the spurious locking problem can be solved as well. The above described phase discriminator provides a non-zero slope even in cases of low

Modified Costas

Zϕ

Proposed PD

SNR ratios, e.g. SNR=1 (0 dB). For comparison, the PD’s performance loss A[dB] can be plotted for the proposed and modified Costas PDs. Expression of A for the proposed and modified Costas scheme is:

A [dB] = 10 log( Dproposed [ Zϕ ] / DCostas [ Zϕ ])

ϕ =0

where D is the PD’s output signal variation for the proposed and modified Costas schemes respectively. The parameter A represents the SNR (in dB) which is required for the proposed PD to overcome the discriminator’s output signal variation, in order to provide the same signal variation level at the PD’s output as the modified Costas scheme. Figure 14 represents A PD’s SNR loss curve for both schemes. Broken line and solid line in Fig. 14 correspond to modified Costas scheme and purposed PD, respectively. From this curve it is seen that the modified Costas scheme requires a substantially lower SNR to produce the same output signal variation as the proposed PD for low SNR values. Such behavior reflects the fact that for low input SNR, the proposed PD gain factor strongly depends on input SNR level, while the modified Costas PD gain factor is about the same. However, when input SNR is large enough (SNR =10), the proposed scheme provides a small yield (about 1 dB) against the Costas. These results indicate the improved performance of the proposed PD compared with the modified Costas scheme. Such improvement is mainly due to a higher proposed PD gain factor for the same input SNR and output signal variation, or put another way, a lower output signal level variation for the same PD’s gain factor.

SNR=10

4.4 SNR=5

The described above time interval analysis can be applied to the bit clock error signal Zτ calculation. Recall again Fig. 10. Figure 10 shows the vector diagram, which demonstrates that the bit-synchronizing instants in the signal t i lie exactly half-way between the moments of intersection for the same axis t *i . Consequently, the information symbol delay can be determined no matter whether there is a phase error or not (and vice versa). The same TIG can be used for the bit clock error signal calculations. It is only necessary to assert the pulses at the instants between two adjacent TIG counter resets. This can be done by dividing the TIG counter content by 2 (Fig. 15). The time points in Fig. 15 correspond to the

SNR=0.5

∆ ϕ [deg. ]

Fig. 12

Bit Synchronization System

SNR=1.0

Phase discriminator. Discrimination characteristic.

The same performance A [dB]

SNR

Fig. 13 Phase detector. Fluctuation characteristic.

Fig. 14 PD’s Losses as function of input SNR.

IEICE TRANS. COMMUN., VOL. E82-B, NO. 9 SEPTEMBER 1468

time points in Fig. 10. If the sequence of the bit clock synchronizing instants in the signal t i is available (the sequence of pulses that correspond to the bit-synchronizing instants in Fig. 15), the bit clock reference oscillator can easily be synchronized by means of convenient digital PLL, for example the circuits described in [2], [3]. Figures 16 and 17 show the machine-computed discrimination Zτ and the fluctuation D[ Zτ ] characteristics for various values of SNR. The fluctuation and discrimination characteristics are presented for the same normalizing factor N T . During simulation, the different phase errors were introduced to the receiver carrier synchronization subsystem. As it was

done for the phase discriminator characteristics, the points that correspond to the different phase errors at the carrier tracking loop for the same delay error values are not shown on the plots Figs. 16 and 17. This is because (if the statistical tolerance can be neglected) the exact same data for the different phase errors at the carrier tracking loop was obtained. The results of the simulation show (as was expected) that the slope (gain factor) of the above described bit clock discriminator is free from the carrier tracking loop errors and only depends on the SNR. During the simulation, it was assumed that the minimal delay step τ is equal T / 64 . This bit clock discriminator can provide a non-zero slope even in cases of low SNR=1 (or 0 dB). 4.5

Bit Error Degradation

In order to estimate E b / N 0 degradation due to noisy reference, performance loss L was introduced in [8]. This performance loss for coherent detection represents the E b / N 0 required to overcome the noisy phase reference effect on BER. Figures 18(a), (b) represent detection loss curves for the proposed and modified Costas schemes for error rates Perr 10−3 and 10−5 respectively. These curves incorporate the data depicted in Fig. 14. It can be seen that for SNR < 8 the pro-

Fig. 15 Bit clock error calculation.

Proposed Scheme

SNR=1

L[dB] SNR=0.5

Zτ

Conventional Modified Costas SNR=5 SNR=10

Phase Reference SNR [dB]

(a)

− NT / 2 Fig. 16

τ

NT / 2 Proposed Scheme

Bit clock discriminator. Discrimination characteristic. SNR=1

SNR=0.5 L[dB]

SNR=5

Conventional Modified Costas

SNR=10

D[Zτ ]

Phase Reference SNR [dB]

(b)

− NT / 2

τ

NT / 2

Fig. 17 Bit clock discriminator. Fluctuation characteristic.

Fig. 18

Perr Perr

(a) Detection losses as function of phase reference SNR, = 10 −3 . (b) Detection losses as function of phase reference SNR, = 10 −5 .

LOZHKIN : DECOUPLED CARRIER AND BIT CLOCK SYNCHRONIZING SUBSYSTEMS 1469

posed scheme required a higher SNR to obtain the same BER as the Costas scheme. However, for large values of SNR (SNR > 8), the proposed scheme outperforms Costas. For a phase reference SNR = 8 both systems have the same performance, while for a phase reference SNR = 10, the proposed system requires a phase reference SNR of about 0.5 dB smaller than the modified Costas. These results indicate the small improved performance of the proposed scheme compared with the conventional Costas loop for large SNR levels. The proposed system is also advantageous from the viewpoint of dynamical tracking. In practical systems, the PLL’s reference SNR is limited by loop bandwidth which must be sufficiently large to permit tracking of frequency variation in the receiver carrier. The proposed scheme can operate with a wider loop bandwidth than the Costas scheme, and provides a reference signal of the same quality. Figure 18 indicates that the proposed scheme exhibits a lower loss for large PLL’s SNR than conventional modified Costas. These results indicate the improved BER performance of the proposed synchronizing system compared with conventional MSK/GMSK demodulator [2].

References [1] R.de Buda, “Coherent demodulation of frequency shift,” IEEE Trans. Commun., vol.COM-20, no.6, pp.429-435, June 1972. [2] K.Murota and K.Hirade, “GMSK modulation for digital mobile radio telephony,” IEEE Trans. Commun., vol.COM-29, no.7, pp.1044-1050, July 1981. [3] F.M.Gardner, Phaselock Techniques, Second edition, John Wiley & Sons, 1979. [4] B.Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE Press, 1996. [5] P.P.Zagnetov, V.M.Tamarkin, A.N.Lozhkin, and S.V.Kostyaev, “A new method of synchronizing a coherent FM receiver,” Radioelectronics and Communications Systems, no.9, 1991. [6] D.G.Messerchmitt, “Frequency detectors for PLL acquisition in timing and carrier recovery,” IEEE Trans. Commun., vol.COM-27, no.9, pp.1288-1295, Sept. 1979. [7] Y. Akaiwa, Introduction to Digital Mobile Communication, John Wiley & Sons, 1997. [8] R.Matyas, “Effect of references on detection of FFSK signals,” IEEE Trans. Commun., vol.COM-26, no.6, pp.807-815, June 1978.

5. Conclusion The independent synchronizing subsystems for the coherent MSK/GMSK demodulator were designed and investigated. Through the simulation tests, it has been shown that it is possible to define carrier frequency and phase errors independently from the information symbols delay, and at the same time provide BER similar to the conventional scheme. The independent synchronization subsystems greatly increase the usable frequency difference range, as there may be a Doppler frequency from the relative motion of transmitter and demodulator, which is particularly important for all mobile communication. The synchronizing subsystems pulling band is up to half the bandwidth of the IFA. The synchronizing subsystems PD is free from spurious locking, provides a constant PD gain factor and does not needs a bit-clock signal. Because of constant PD gain factor, the time consumption for the initial synchronization can also be reduced considerably. For probabilities of error 10−3 and 10−5 the proposed system required a phase reference SNR of about 0.5 dB smaller than conventional Costas loop. While limited to higher SNR ratios, the proposed system is suitable for many applications and can be realized with simpler circuitry well suited for IC implementation. Acknowledgment The author is indebted to Prof. Yoshihiko Akaiwa (Kyushu University) and Dr. Peter P. Zagnetov (Moscow Aviation Institute) for reading and commenting on this manuscript, and participating in helpful discussions. I must also express my gratitude to the management of MECC Co., Ltd, Japan, especially president Toshio Yanagihara, for his encouragement, support and tolerance, and to my coworkers for the same.

Alexander N. Lozhkin was born in Moscow, Russia on July 9, 1963. He received Radio-Engineering qualification and MS EE degrees from Moscow Aviation Institute, Moscow in 1986 and 1991, respectively. Since 1992, he has been with MECC Co., Ltd, Fukuoka, Japan. Now he is researching digital communication systems. He is a staff engineer of the L.B. Laboratory of the MECC Co., Ltd., Japan. He is currently working towards Ph.D. EE degree at the Department of Intelligent Systems, Kyushu University, Japan. His current research interests are high-speed communication systems and digital signal processing. Mr. Lozhkin is a member of the IEEE Communication Society.