Design and FPGA-implementation of an improved

Ain Shams Engineering Journal (2014) xxx, xxx–xxx

Ain Shams University

Ain Shams Engineering Journal www.elsevier.com/locate/asej www.sciencedirect.com

ELECTRICAL ENGINEERING

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control E.A. Ramadan *, M. El-bardini, M.A. Fkirin Department of Industrial Electronics and Control Eng., Faculty of Electronic Engineering- menof, Menofia University, PO Box 32952, Menof, Egypt Received 27 November 2013; revised 12 March 2014; accepted 9 April 2014

KEYWORDS Adaptive fuzzy logic control; PID adjusting mechanism; VHDL code software; FPGA; Spartan-3E starter kit

Abstract This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA) hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC) algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE) and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions. 2014 Production and hosting by Elsevier B.V. on behalf of Ain Shams University.

1. Introduction DC motors are one of the most used electrical machines, which are used in many industrial applications such as robots, welding and roll processes. Therefore, developing new control tools become very important to enhance the performance as well as the intelligence of such electro-mechanical systems [1,2]. Many intelligent control techniques [3–5], such as artificial neural networks, and AFLC methods, have been developed * Corresponding author. E-mail addresses: [email protected] (E.A. Ramadan), [email protected] (M. El-bardini), [email protected] (M.A. Fkirin). Peer review under responsibility of Ain Shams University.

Production and hosting by Elsevier

and applied to control the speed of permanent magnet DC motor, in order to obtain high operating performance [6,7]. Moreover, the development of AFLCs can be used to cope some of important complex control problems such as stabilization and tracking process output signals, the presence of nonlinearity and/or the disturbance. Adaptive systems are generally used to control systems which include unknown and/or time-varying parameters [8]. AFLCs require many computations. Hence, implementations of these highly complex control algorithms depend on the personal computer systems in most studies. FPGAs provide a possible solution to this issue [9,10]. Due to the progress of very large scale integrated circuits (VLSI) technology, the FPGA has brought more attention before. The advantages of the FPGA can be summarized as, programmable hardwired feature, fast time-to-market, shorter design cycle, embedding processor, low power consumption and higher density for the implementation of the digital system [6,11]. FPGAs also provide a compromise between the special-purpose

2090-4479 2014 Production and hosting by Elsevier B.V. on behalf of Ain Shams University. http://dx.doi.org/10.1016/j.asej.2014.04.002 Please cite this article in press as: Ramadan EA et al., Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control, Ain Shams Eng J (2014), http://dx.doi.org/10.1016/j.asej.2014.04.002

2

E.A. Ramadan et al.

Figure 4 Figure 1

New sub-block diagram of adjusting mechanism.

DC motor equivalence circuit.

the designed digital system to reduce the development time and to enhance the system performance [9,12]. In this paper, an improved AFLC system is presented to estimate and control the speed of a separately excited DC motor. The major goal is to reduce the computational complexity of different sets of an adaptive fuzzy algorithm. This design is coded in VHDL software and Xilinx ISE, which are used for synthesis and implementation of controller on the Spartan-3E FPGA starter kit. 2. Modeling of DC motor

Figure 2 system.

Block diagram representing the nonlinear DC motor

application-specified integrated-circuit hardware and general purpose processors [4]. Embedded processor can now be developed in a simple way, allowing the user to design and mix hardware and software in one chip of the FPGA. Complicated control algorithms with heavy computation can be realized by software in FPGA. The results of the software/hardware co-design function increase the programmable, flexibility of

Figure 3

A schematic diagram of an armature controlled DC motor is given in Fig. 1. Equations of a DC motor based on the Kirchoff’s voltage law combined with the Newton’s moment law can be written as [10,13]: dia þ R a ia þ V b dt ! 1 dxm 1 Jm þ 2 J‘ þ 2 bt xm dt Kg Kg

Va ¼ La

ð1Þ

Tm ¼

ð2Þ

Tm ¼ KT ia

ð3Þ

Block diagram of the AFLC.

Please cite this article in press as: Ramadan EA et al., Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control, Ain Shams Eng J (2014), http://dx.doi.org/10.1016/j.asej.2014.04.002

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

3

Rules data dase

Active Rules Generators

Active MF Labels for Input

Crisp Input

Rules Inference Defuzzification

Fuzzification

Active MF values for Inputs

Figure 5

Crisp Output

Aggregation

FLC architecture.

Proportional Error Integration

Change of Error

Output

derivative

Figure 6

Figure 8

PID architecture.

Spartan-3E starter kit.

The DC motor symbols and variables are shown in Table 3. Although high-quality DC motors are largely described by linear models, their performance is often limited by nonlinear phenomena such as friction, dead zone and saturation [14]. It is well established that the friction torque is a function of the angular velocity as shown in Fig. 2. In the classical friction model there is a constant friction torque opposing the motion when x‘ equal zero. A general mathematical model of the friction torque is [15]: Tf ¼ a0 sgnðx‘ Þ þ a1 ea2 jx‘ j sgnðx‘ Þ

ð6Þ

where Tf is the nonlinear friction torque and Td is the load disturbance, the constants ai > 0, i = 0, 1, 2. The linear model is capable of supplying the required robustness property when the DC motor rotates in a single direction. In other words, as long as the rotational speed span of the system excludes the zero speed point, the linear model can be safely used in representing the system behavior for control design purposes [16]. Figure 7

Spartan-3E layout.

3. Adaptive fuzzy logic controller Vb ¼ Kb xm

ð4Þ

In addition, the transfer function from input Va to output x‘ is given by: x‘ ðsÞ Kg KT ¼ 2 Va ðsÞ La Jeq S þ ðLa bt þ Ra Jeq ÞS þ Ra bt þ K2g KT Kb where Jeq ¼ ðK2g Jm þ J‘ Þ and Kg ¼ xxm‘ .

ð5Þ

A direct adaptive controller uses a fuzzy logic system (FLS) as a controller and it incorporates linguistic fuzzy control rules directly into the controller [17]. In this section, we have used a direct adaptive fuzzy control scheme that consists of a fuzzy logic control (FLC), a reference model and an adjusting mechanism as shown in Fig. 3. The detailed description is as follows:


4

E.A. Ramadan et al. Table 1

Comparison results between AFLC and AFLC-PIDAM.

Control strategies The synthesis ISE Report (Utilization) Slices used (%) Flip Flop used (%) 4 input LUTs used (%) Mult 18 · 18 SIOs used (%) AFLC AFLC-PIDAM

87 55

32 23

76 51

100 90

Pn i¼1 lðUi Þ:Ci Uf ¼ P n i¼1 lðUi Þ

3.1. FLC

ð12Þ

It is the main part of the controller in combination, and this part composed by some sections as follows Fuzzifcation, Active Rules Address Generator, Rule Inference and Center of Gravity Defuzzification. The tracking Error (e) and Change of Error (De) are defined by Eqs. (7) and (8) respectively as follows:

where l(Ui) is the values of membership function (MF) for output and Ci is the values of output MFs centers. Next this result is transferred to the DC motor.

eðkÞ ¼ xref x‘

ð7Þ

DeðkÞ ¼ eðkÞ eðk 1Þ

ð8Þ

It is used to specify the desired performance that satisfies design specifications for the overall system. Generally, this model can take any form. It can be a continuous or discrete system, variant or non-variant, linear or nonlinear etc. In the case of DC motor, a second order dynamical reference model was used, and it can be expressed as:

Instead of knowledge about the plant (DC motor) to design a FLC some knowledge about adequate plant control actions is used to design an initial control solution. The control knowledge can be provided for example by human knowledge, and is assumed to be expressed as a set of ‘‘m’’ fuzzy IF-THEN rules of the form: ð9Þ

IF e is Ai and De is Bi THEN Uf is Zi

where i = 1, 2, 3, . . ., m. There are seven fuzzy sets for each linguist value {Ai, Bi, Zi} and 49 fuzzy control rules are designed for two inputs and one output fuzzy system Uf. A maximum of four rules will be active at any time [18]. lZ ðUf Þ ¼ max minðminðlAj ðeÞ; lBj ðDeÞÞ; lZj ðUf ÞÞ

ð10Þ

lðUi Þ ¼ ðlAj ðeÞ lBj ðDeÞÞ

ð11Þ

ðj¼i;iþ1Þ

3.2. Reference model

GðsÞ ¼

x2n S þ 2nn xn S þ x2n

ð13Þ

2

where xn is natural frequency and n is damping ratio. Applying the bilinear transformation, the continuous model of Eq. (13) can be transformed to a discrete model by: ym ðkÞ a0 þ a1 z1 þ a2 z2 ¼ xref ðkÞ 1 þ b1 z1 þ b2 z2

ð14Þ

The z1 is back shift operator and a0, a1, b1 and b2 are the parameters of the discrete model. Furthermore, the difference equation is written as: ym ðkÞ ¼ b1 ym ðk 1Þ b2 ym ðk 2Þ þ a0 xref ðkÞ

After that, defuzzifier converts Eq. (9) into the following expression:

þ a1 xref ðk 1Þ þ a2 xref ðk 2Þ

ð15Þ

+5V

Triangle generator

220kΩ

PWM signal

470Ω

1uF 33kΩ 1kΩ

J1-Accessory Header

DAC Header (J5)

Figure 9

10kΩ

M Mechanical coupling

10kΩ

Control Signal

Kit

Same signal

+Vcc + -

FPGA Spartan-3E

+24V

Channel A

Optical encoder

Channel B Index

Block diagram of the DC motor speed control using FPGA.



5

(a)

(b)

Figure 10 Internal architecture of the FPGA-based speed control for DC motor. (a) Main components of the FPGA-based controller, (b) structure of the AFLC-PIDAM.

3.3. Adjusting mechanism The primary purpose of adjusting the parameters of the fuzzy controller so that the closed loop system (expressed through xref(k) and x‘(k)) behaves as the reference model (expressed by xref(k) and ym(k)). The adjusting mechanism

consists of two parts: a ‘‘fuzzy inverse model’’ and a ‘‘knowledge-base modifier’’. The out of the fuzzy inverse model is an adaptation factor p(k) which is necessary to force ye(k) to zero. The knowledge-base modifier adjusts the centers of the output MFs of the FLC in two stages [19]:


6

E.A. Ramadan et al. The centers of the output MFs, which were found in the active set of rules determined earlier, are adjusted. The centers of these MFs Ci at step ‘‘k’’ will have the following values:

Ci ðkÞ ¼ Ci ðk 1Þ pðkÞ

ð17Þ

The rules that are not in the active set, their output MFs are not modified. Figure 11 FPGA.

Real system of the DC motor speed control using

Find all the rules in the FLC whose premise certainty

li ðeðk 1Þ; Deðk 1ÞÞ > 0

ð16Þ

And call it the ‘‘active set’’ of the rules at time (k 1).

4. Structure of adaptive control with proportional integral derivative adjusting mechanism This section presents the structure of our developed AFLC. The main components of Adaptive Fuzzy Logic Control with Proportional Integral Derivative Adjusting Mechanism (AFLC-PIDAM) is the FLC with a reference model (no modifications); whereas the inverse fuzzy (adaptation part) is replaced by a new adaptation algorithm as shown in Fig. 4. This design is depending on the characteristics of PID-technique to minimize the error ye(k) between the DC motor speed

Speed control under AFLC

(a)

Motor speed

Step Command

Output of Reference Model

160

Speed (rpm)

140 120 100 80 60 40

0

10

20

30

40

50

60

50

60

time (sec) Control Signal under AFLC

(b) 1.8 1.6

Volt

1.4 1.2 1 0.8 0.6 0.4

0

10

20

30

40

time (sec)

Figure 12 Step response of motor speed and control effort operated at 50–150 rpm square wave command: (a) response under the AFLC, (b) control signal.



7

Speed control under AFLC-PIDAM

(a)

Motor speed

160

Output of Reference Model

Step Command

Speed (rpm)

140 120 100 80 60 40 0

10

20

30

40

50

60

50

60

time (sec) Control Signal under AFLC-PIDAM

(b)

2.4 2.2 2 1.8

Volt

1.6 1.4 1.2 1 0.8 0.6 0.4 0

10

20

30

40

time (sec)

Figure 13 Step response of motor speed and control effort operated at 50–150 rpm square wave command: (a) response under AFLCPIDAM, (b) control signal.

Table 2

Comparison between AFLC and improved AFLC-PIDAM.

Control strategies

Square command

Sine command

Settling time (sec)

Over shoot (rpm)

Rise time (sec)

Steady state error

RMSE

Max of tracking error (rpm)

AFLC AFLC-PIDAM

3.5 2.1

6.32 3.77

2.3620 0.92

0.2078 0.0425

6.0283 4.2012

±17 ±14

output xref(k) and the reference model output ym(k) as it represents in Eq. (18). ye ðkÞ ¼ ym ðkÞ x‘ ðkÞ

ð18Þ

In the proposed scheme, the error and the change of error measured between the motor speed and the output of a reference model are applied to a PID-adjusting mechanism. The adaptation output will be adjusting the center values of the output fuzzy sets. This replacement between two algorithms is suggested to minimize the number of stages of adaptation mechanism, and reduction of computational complexity of the different set of inverse fuzzy adaptation parameters, which consists of eight stages as shown in Fig. 5 [20].

In addition, the inverse fuzzy adaptation structure needs a large number of logical elements and large size on the chip of the FPGA. On the other side the PID-technique can be built as a complete parallelism implementation and at the same time, it has a simple structure as shown in Fig. 6. The design of the PID-technique requires specification of three parameters, which are proportional gain (Kp), integral gain (Ki) and derivative gain (Kd), respectively. The primary design goals are to obtain good adjusting of the center value performance of output fuzzy sets by minimizing the integral absolute tracking error. The improved adjusting mechanism can be summarized as:


8

E.A. Ramadan et al. Speed control under AFLC

(a) 140

Sine Command

Motor speed

120

Speed (rpm)

100 80 60 40 20 0 0

5

10

15

20

25

30

20

25

30

20

25

30

time (sec) Control Signal under AFLC

(b)

1.8 1.6 1.4

Volt

1.2 1 0.8 0.6 0.4 0.2 0 0

5

10

15

time (sec) Speed Error

Speed (rpm)

(c) 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -20 0

5

10

15

time (sec)

Figure 14

Frequency response of a 0.4 Hz sinusoid input: (a) response under AFLC, (b) control signal, (c) error speed.



9

Speed control under AFLC-PIDAM

(a) 140

Sine Command

Motor speed

120

Speed (rpm)

100 80 60 40 20 0

0

5

10

15

20

25

30

20

25

30

20

25

30

time (sec) Control Signal under AFLC-PIDAM

(b)

1.8 1.6 1.4

Volt

1.2 1 0.8 0.6 0.4 0.2 0

0

5

10

15

time (sec) Speed Error

Speed (rpm)

(c) 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -20 0

5

10

15

time (sec)

Figure 15

Frequency response of a 0.4 Hz sinusoid input: (a) response under AFLC-PIDAM (b) control signal, (c) error speed.


10 Table 3

E.A. Ramadan et al. Nomenclatures and DC motor drive parameters.

Symbol

Description

p(k) xm(t) ia(t) La Ra Va(t) Vb(t) z1 De Dye(k) ai n Kd a0, a1, b1 and b2 G(s) ye(k) Kg lA, lB, lZ Ki S Ai, Bi, Zi Td J‘ Ci l(Ui) Kb Jm Tm(t) KT xn Tf m k Uf UPID(k) Kp xref ym(k) bt x‘(t) e

Adaptation factor Armature angular velocity Armature current Armature inductance Armature resistance Armature voltage Back e.m.f Back shift operator Change of error Change of error ye(k) Constants i = 0, 1, 2 Damping ratio Derivative gain Discrete reference model parameters Dynamical reference model Error between the DC motor speed output and the reference model output Gear-box ratio Input and output membership function values Integral gain Laplace operator Linguist values Load disturbance Load inertia Membership function centers Membership function values Motor constant Motor inertia Motor torque Motor torque constant Natural frequency Nonlinear friction torque Number of fuzzy sets Number of step Output fuzzy system Output of the PID-adjusting mechanism Proportional gain Reference angular velocity (DC motor speed reference) Reference model output Rotational viscous friction Shaft angular velocity (DC motor speed output) Tracking error

Find the error ye(k) as in Eq. (18) and the change of error Dye(k): Dye ðkÞ ¼ ye ðkÞ ye ðk 1Þ

ð19Þ

The output of the PID-technique that depends on the kth step of ye(k) and Dye(k) can be obtained from:

UPID ðkÞ ¼ Kp ye ðkÞ þ Ki

k1 X

ye ðqÞ þ Kd Dye ðkÞ

ð20Þ

q¼0

The values of the PID-technique parameters are tuned by using Ziegler-Nichole method [21]. The output UPID(k) is considered as adaptation factor:

pðkÞ ¼ UPID ðkÞ

ð21Þ

The adaptation factor p(k) is used to adjust the centers Ci of the output MFs according to Eq. (17).

5. FPGA implementation The Spartan-3E FPGA is embedded with the 90 nm technology at the heart of its architecture. This reduces the die size and cost, increases manufacturing efficiency, and addresses a wider range of applications. The Spartan-3E diagram is shown in Fig. 7. It allows users to easily migrate to different densities across multiple packages and supports 18 different singleended and differential I/O standards [22,23].



11

Speed Control under AFLC with loads -20%

(a) 120

Speed (rpm)

100 80 60 40 20 0

0

5

10.35

15

20

25

time (sec)

(b)

Control Signal under AFLC with loads -20% 3 2.5

Volt

2 1.5 1 0.5 0

0

5

10.35

15

20

25

time (sec)

Figure 16

A regulatory response of AFLC under 20% load: (a) response under AFLC, (b) control signal.

In the proposed FPGA-based speed control, the current controllers are implemented by using Spartan-3E FPGA hardware. The AFLC and the AFLC-PIDAM are realized by using VHDL code software. The fuzzy controller in this study uses triangular fuzzifier, triangular MF, product-inference rule and central average defuzzifier method. The parameter adjustment mechanism is based on the PID-adjusting mechanism method [6]. The transfer function of the reference model in Fig. 3 is chosen by a second order system with the natural frequency of 4.08 rad/sec and the damping ratio of 1. After applying the bilinear transformation with a sampling frequency of 20 Hz, the parameters of the difference equation in Eq. (15) are obtained by: a0 = 0.00, a1 = 0.006, a2 = 5.48, b1 = 0.95061 and b2 = 0.00951227. The values of PIDtechnique parameters are found: Kp = 3.9, Ki = 6.67 and Kd = 0.57. The speed of the motor is measured by means of optical encoder and is given as an input to the expansion connectors on board (J1 6-pin Accessory Header) [24] in which the main feature is found. As shown in Fig. 8. The reference speed is assigned to motor internal configuration memory of the FPGA. To verify the performance

of the controller design on hardware, the VHDL code (Bit file) are downloaded into the target FPGA device (Spartan3E family XC3S500) using Xilinx ISE pack 11.1i. The inputs and outputs with the gate level details of the subsystem and the synthesis report, which is created from ISE WebPack program for two current controllers. It found that the PID components in adjusting mechanism used 2%, but the inverse fuzzy components used 48% from available Slices. The overall area of AFLC which used from the available Slices about 87% but AFLC-PIDAM used 55% as shown in Table 1. The complete experimental system consists of a DC motor which parameters Va, x‘, Ra, La, Kg, Jeq, bt, Kb and KT in Fig. 1 are set as 24 vdc, 300 rpm, 4.67 O, 170 mH, 0.16, 42.6e6 kg m2, 47.3e6 N m sec/rad, 14.7e3 V sec/rad and 14.7e6 N m/A, respectively, FPGA Kit, and the electrical circuits of (PWM driver and H-bridge) is shown in Fig. 9. The internal architecture of the proposed FPGA and the real system is shown in Figs. 10 and 11 respectively. Results of measurements confirmed again correct operation of the system. The time of system processing was sample period = 0.05 sec based on clock frequency 50 MHz.


12

E.A. Ramadan et al. Speed Control under AFLC-PIDAM with loads -20%

(a) 120

Speed (rpm)

100 80 60 40 20 0

0

5

10.35

15

20

25

time (sec)

(b)

Control Signal under AFLC-PIDAM with loads -20% 3.5 3

Volt

2.5 2 1.5 1 0.5 0 0

5

10.35

15

20

25

time (sec)

Figure 17

A regulatory response of AFLC-PIDAM under 20% load: (a) response under AFLC-PIDAM, (b) control signal.

6. Results and discussion The proposed controllers are implemented in FPGA for real time control of speed in the DC motor. The dynamic performance of DC motor drive is evaluated while the AFLC and the AFLC-PIDAM are applied in a speed control loop (see Fig. 10). The step response under two controller’s cases is first evaluated. The first case is a motor running under two controllers that the amplitude of speed command is 50– 150 rpm square wave as shown in Figs. 12 and 13 respectively. When the AFLC is applied, it reveals a slow tracking performance and lack of smooth transition between desired speed and speed command as it is shown in Fig. 12(a). However, there are some disadvantages of FLC, such as the response frequently suffers from ripples around desired speed due to firing of the rules at different proportion to MFs at every sampling instant. Depending on the operating point, each rule of FLC gives an output corresponding to the degree of membership of each input. It is difficult and almost impossible to design the accurate MFs, fuzzy rules, and scaling factors. Therefore, the control effort may be high in both accelerating and decelerating directions and causes ripples around the optimum desired speed effort, as shown in Fig. 12(a) [25]. However, when the proposed AFLC-PIDAM is presented in Fig. 13, its tracking results are highly improved and presented in Fig. 13(a), and the actual motor speed can get a good

following with the output of the reference model as shown in Table 2. Secondly, the sinusoid wave input is considered to evaluate the performance of the proposed controllers. A tested input signal of the sinusoidal wave with 70 ± 50 rpm amplitude and a frequency of 0.4 Hz are provided. In this design, the frequency tracking response and the tracking error of the DC motor speed are shown in Figs. 14 and 15 respectively. In the case of AFLC-PIDAM, it reveals that the RMSE for the amplitude tracking error is equal 4.2012, which is better than the RMSE of the AFLC tracking error, it is equal to 6.0283 as its show in Fig. 15 and Table 2. Therefore, the experimental results shown in Figs. 12–15 demonstrate that the proposed FPGA-based speed control for DC motor drive is effective. When the experimental system is with an external 20% load connection at instant 10.35 sec, the step response under two controllers is evaluated. It reveals a bad tracking result with an AFLC as shown in Fig. 16. However, when the proposed AFLC-PIDAM is presented in Fig. 17, its tracking results are improved. It is obvious that although the dynamic is presented, the centers of MF are changing and updating. After the load is applied at instant (10.35 sec) the centers parameters are tuned to adequate values as shown in Figs. 18 and 19 respectively. Outline above From Figs. 12–17 and Tables 1 and 2, it is clear that improved AFLC-PIDAM performs significantly better than a conventional AFLC .



Figure 18 Changes and updates of centers under the AFLC: (a) at Initial, (b) once the load is applied, (c) at Final.

7. Conclusions This paper presented the speed control for DC motor drive based on the FPGA technology. The speed control based on an FPGA and the two embedded controllers are implemented by using VHDL code software and Spartan-3E FPGA starter kit Board hardware. It is designed to realize the aforementioned control algorithms for ensuring high performance. Therefore, all functionalities, which are based on software/ hardware co-design, required to build a fully digital speed control for DC motor drive, have been integrated in one FPGA chip. The performance of the proposed controller is validated by the experimental results of the step and frequency com-

13

Figure 19 Changes and updates of centers under the AFLCPIDAM: (a) at Initial, (b) once the load is applied, (c) at Final.

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E.A. Ramadan received the B.Sc. and M.Sc. degrees in automatic control engineering from Faculty of Electronic Engineering, Menofia University, Menof, Egypt. He is currently working toward the Ph.D. degree in automatic control engineering. He is currently Assistant Lecture with the department of Industrial Electronics and Control Engineering, Faculty of Electronic Engineering, Menofia University, Menof, Egypt. His current research Embedded Intelligent Control System Based on FPGA.

M. El-Bardini is currently an Associate Professor with the Department of Industrial Electronic and Control Engineering, Faculty of Electronic Engineering; Menoufia University .His research interests include Robotics, Computer Controlled Systems and the Embedded System design for Control Systems. He has coauthored many journal and conference papers and has supervised many Ph.D. and M.Sc. for students working in the field of Intelligent Control Systems, Embedded Control Systems, Advanced Techniques for Systems Modeling, and Vision based Control of Robotic Systems. He is the recipient of the best students project Award in Egyptian Engineering Day.

M.A. Fkirin is currently a Professor with the Department of Industrial Electronic and Control Engineering, Faculty of Electronic Engineering; Menoufia University. He got B.Sc. (1971–1976) and MSc (1977–1980) in automatic control systems identification, in Egypt. He got Ph.D. from Birmingham University England in (1982–1986). He has authored 55 publications (53 papers and 2 books). He has significant contributions in evolving appropriate strategies of optimal exploitation for online identifying and predicting of dynamic systems. In particular for his pioneering studies on the smoothing forms to identify the SISO and MIMO systems, and for his key role in developing new effective prediction algorithms based on Kalman and lattice filters. These strategies are used for solving prediction problems in developing countries (Egypt and Saudi Arabia), such as econometric, hydrological, industrial and medical applications. Also, his research interests include the development of advanced models of educational and computer-control systems. He was awarded the prize of Young Arab scientists, in 1991. He was selected to be formal referee in Jordanian board for choosing the new winners for the Young Arab scientists prize. He was awarded the First Prize of the Third International Symposium of Date Palm, Saudi Arabia, 1993.
