Design & Implementation of Floating point ALU on a

2012 International Conference on Computing, Electronics and Electrical Technologies [ ICCEET]

Design & Implementation of Floating point ALU on a FPGA Processor Prashanth B.u.v

\ P.Anil Kumai , .G Sreenivasulu3

i

3 Maintenance Engineer, DST-PURSE, 2M. TECH Student , Associate Professor, S. V University, Tirupati-517502

an exponent of OxFF or if any input operator is infinity. The

Abstract- In this paper, the implementation of DSP modules such as a floating point ALU are presented and

Underflow exception occurs if the implicit bit of result is zero

designed. The design is based on high performance

or if the exponent out is -

FPGA "Cyclone TI" and implementation is done after

126 or OxOI the number is too small to be represented fully in

functional and timing simulation. The simulation tool and

single precision format. The Division by zero exception occurs

implementation is Quartus n. The experimental results

when the divisor is zero the result is set to infinity. The Invalid

shows the functional and timing analysis for all the DSP

operation exception occurs when the Operation cannot be

used

is

ModelSim.

The

tool

for

synthesis

modules carried out using high performance synthesis

performed on operands. Ex: Subtraction of infinity and NAN

software from Altera.

inputs.

K�ords-Floating point ALU, Adder, subs tractor,

III. BLOCK DIAGRAM OF FLOATING POINT

multiplier , divider.

I.

ADDITION AND SUBSTRACTION

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INTRODUCTION

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