Design & Implementation of MLS Data Demodulation

Design & Implementation of MLS Data Demodulation and Processing Unit (ASIC for an Integrated Navigation Receiver) Anteneh Alemu Abbo Circuits & Systems Group Department of Electrical Engineering Delft University of Technology Mekelweg 4, 2628 CD Delft The Netherlands

Delft, October 1996 Technical Report no. : TWAIO-96-03 Supervisor : Prof. Dr. Ir. R.H.J.M. Otten Advisor : Ir. L.K. Regenbogen

Design & Implementation of MLS Data Demodulation and Processing Unit (ASIC for an Integrated Navigation Receiver) Report submitted in partial ful llment of the Diploma of Chartered Designer in Microelectronics

Anteneh Alemu Abbo Circuits & Systems Group Department of Electrical Engineering Delft University of Technology Mekelweg 4, 2628 CD Delft The Netherlands

Delft, October 1996 Technical Report no. : TWAIO-96-03 Supervisor : Prof. Dr. Ir. R.H.J.M. Otten Advisor : Ir. L.K. Regenbogen

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Summary Integrating dierent navigation aids helps to improve the system integrity, reliability and availability. Such an integrated system provides guidance information at all phases of navigation,

e.g., en-route, approach and landing guidance in an aircraft. The systems to be integrated range from terrestrial navigation aids (e.g., LORAN-C and OMEGA), to satellite-based ones (GPS and GLONASS). In the case of aircrafts, guidance in the nal phase of approach and is done by systems like ILS and MLS.

This report describes the design and implementation of a data demodulation and processing unit for a Microwave landing system (MLS). This work was conducted as part of the GOLLUM integrated navigation receiver design, which consists of three more sub-systems: GPS, LORAN-C and OMEGA. The design was conducted according to ICAO speci cations concerning signal format and strength. With respect to GOLLUM, the design satis es the resource sharing requirement by relieving the MOVE application speci c processor (ASP) from computationally intensive tasks. After investigating dierent demodulator architectures, the one based on a second-order all-digital phase-locked loop (ADPLL) has been chosen. This approach has the advantage of avoiding problems related to conventional analog implementations, such as component tolerances, aging and power supply variations. It also results in a compact receiver architecture because of integration on the MOVE ASP. To reduce the computational load of the ASP, the demodulator was implemented in an application speci c hardware which executes the complex carrier acquisition and clock synchronization routines. While bene ting from the fully-digital nature, our approach allows sharing of the MOVE processor with other applications, unlike the fully-software approach. In addition to the data demodulation, part of the data validation task is also realized in hardware. The serial output bits of the demodulator are parallelized for interfacing with the MOVE data bus. These choices help to reduce the frequency of interrupts and the associated load of interrupt service overhead. This will further facilitate the sharing of the MOVE processor among low-rate routines. The associated hardware cost of this approach is only a small percentage of the overall cost. A prototype of the data-demodulator and part of the data-validation units has been implemented on a sea-of-gates sh-bone with a feature size of 1.6 m. The OCEAN/NELSIS IC design tools were used for design entry, layout and veri cation. The metalization was done by the DIMES IC-design facilities. The design costs about 20,000 transistors (12 % of the whole chip). The remaining space is left for similar application speci c hardware units of the other navigation subsystems and the generalpurpose functional units of the MOVE processor, which are shared among low-rate routines of the dierent applications.

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Acknowledgement I would like to thank all the people who directly or indirectly helped me get through the last two years and complete this designers program. Thanks to all CAS members for creating a very friendly working environment. My special thanks go to Prof. Dr. Ir. Ralph Otten for proposing this research based design task, Ir. Loek Regenbogen and Dr. Ir. Richard den Dulk for the very useful suggestions during the course of this work. My thanks go to Ir. Andre Nieuwland, Ir. Cezar Bruma (members of the GOLLUM project), and to the members of the Home Systems Project(WISSCE) for the ideas we exchanged. Special thanks to Ir. Jack Glass for the useful introductions to the MOVE processor and for sharing his experience in the OCEAN IC design system. Finally, I thank my family and friends nearby and back home in Ethiopia for giving me the moral support and peace of mind during the course of the work.

Contents 1 Introduction

1.1 The Microwave Landing System : : : : : 1.1.1 System Overview : : : : : : : : : 1.1.2 The MLS Signal Format : : : : : 1.1.3 The MLS Receiver Speci cation 1.2 Report Outline : : : : : : : : : : : : : :

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2 The MLS Receiver Architecture and its Design Overview 2.1 MLS Receiver Architecture : : : : : : : : 2.1.1 The Front-end : : : : : : : : : : : 2.1.2 The Intermediate Frequency Stage 2.1.3 MLS Post-IF Signal Processing : : 2.2 Design Overview : : : : : : : : : : : : : : 2.3 DPSK Demodulation Techniques : : : : : 2.3.1 Incoherent DPSK Demodulation : 2.3.2 Coherent Data Demodulation : : :

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3 Design and Implementation of MLS Functional Units 3.1 Implementation Considerations : : : : : : : : : : : : : 3.1.1 DPSK Demodulation in the Analog Domain : : 3.1.2 Software-based Digital DPSK Demodulation : 3.1.3 Hardware-based Digital DPSK Demodulation : 3.2 ADPLL-based Design of the MLS Data Demodulator : 3.2.1 The Remodulator Loop : : : : : : : : : : : : : 3.2.2 Mixer Design : : : : : : : : : : : : : : : : : : : 3.2.3 Data Filter Design : : : : : : : : : : : : : : : : 3.2.4 The Data Clock Generator : : : : : : : : : : : 3.2.5 The DPSK Decoder and Barker Code Detector ix

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CONTENTS

x 3.2.6 The Control Unit : : : : : : : : : : : : 3.2.7 The Frequency Divider : : : : : : : : : 3.2.8 The Data Validation Functional Unit : 3.2.9 Interfacing to the MOVE Processor : 3.3 Sea-of-Gates Layout : : : : : : : : : : : : : :

4 Simulation Results

4.1 The Sampling-type Mixer : : : : : : 4.2 ADPLL Simulation : : : : : : : : : : 4.2.1 Acquisition Performance : : : 4.2.2 Jitter in the Tracking mode : 4.3 The Data Filter and Bit Error Rate

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5 Conclusion

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A C-code Description of the MLS Data Demodulator

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List of Figures 1.1 1.2 1.3 1.4

Concept of the GOLLUM integrated navigation receiver : : : : : : : : The GOLLUM navigation receiver using the MOVE processor concept The scanning-beam concept : : : : : : : : : : : : : : : : : : : : : : : : MLS Basic data and Angle frame formats : : : : : : : : : : : : : : : :

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2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10

Functional blocks of the MLS receiver : : : : : : : : Block diagram of the MLS front-end : : : : : : : : : Block diagram of the Intermediate Frequency Stage : MLS post-IF signal processing : : : : : : : : : : : : : Design Trajectory of the MLS data demodulator : : DPSK Modulation : : : : : : : : : : : : : : : : : : : Incoherent receiver structure : : : : : : : : : : : : : Quadrature autocorrelator for DPSK demodulation : A Costas loop based demodulator : : : : : : : : : : : A Remodulation loop based demodulator : : : : : :

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3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13

Software-based MLS data demodulation : : : : : : : : : : : : : : : : The coarse acquisition algorithm : : : : : : : : : : : : : : : : : : : : Block diagram of AFC-based ne acquisition : : : : : : : : : : : : : Data demodulation in the software domain : : : : : : : : : : : : : : MOVE simulation framework : : : : : : : : : : : : : : : : : : : : : : MOVE simulation Results : : : : : : : : : : : : : : : : : : : : : : : : A second-order ADPLL formed by cascading two rst-order sections XOR phase detector characteristics : : : : : : : : : : : : : : : : : : : Frequency domain model of the cascade 2nd-order ADPLL : : : : : A second-order ADPLL based on a rate multiplier : : : : : : : : : : Model for a second-order loop based on the rate multiplier : : : : : : MLS data demodulation functional unit : : : : : : : : : : : : : : : : MLS data devalidation functional unit : : : : : : : : : : : : : : : : :

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LIST OF FIGURES

xii 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24

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Simulation of phase quantization in a sampling type mixer : : : : : : : : : : : : : : Simulation set-up for studying ADPLL acquisition and jitter : : : : : : : : : : : : Acquisition behavior of a Cascaded 2nd-order ADPLL : : : : : : : : : : : : : : : : Acquisition behavior of a rate multiplier based 2nd-order ADPLL : : : : : : : : : : Jitter characteristics in the tracking mode: cascaded ADPLL at fin = 265 kHz and rate multiplier based ADPLL at fin = 215 kHz. : : : : : : : : : : : : : : : : : : : : 4.6 Data lter (integrator) operation in dierent receiver modes : : : : : : : : : : : : :

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4.1 4.2 4.3 4.4 4.5

ADPLL-based remodulation loop : : : : : : : : : : : : : : : : : : : : : : : : : : Digital mixer using a D-type ip- op : : : : : : : : : : : : : : : : : : : : : : : : Block diagram of the data lter using an up/down counter with a control logic Interior of the lter cells : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Data clock generator using a triggerable down counter : : : : : : : : : : : : : : DPSK decoding and Barker code detection unit : : : : : : : : : : : : : : : : : : Receiver control unit and its state graph : : : : : : : : : : : : : : : : : : : : : : Frequency Divider : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Cells for the data validation unit : : : : : : : : : : : : : : : : : : : : : : : : : : Hardware for MLS data validation process : : : : : : : : : : : : : : : : : : : : : Sea-of-gates layout of the MLS data demodulator : : : : : : : : : : : : : : : : :

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Chapter 1

Introduction Today, the importance of navigation ranges from the basic personal needs of travelling through a city, to the accurate guidance of aircrafts, ships and missiles with a very high accuracy. These needs are met with the help of dierent navigation aids such as [1, 26]

 terrestrial: { LORAN-C (LF 100 kHz):which covers the northern hemisphere { OMEGA (VLF 10 kHz): with a world-wide coverage { VOR (VHF 100 MHz), DME-N(Distance Measuring equipment)(UHF 1 GHz): useful

for en-route aircraft guidance { DME-P (UHF 1 GHz), ILS (Instrument Landing System, VHF 100 MHz) and MLS (Microwave Landing System, UHF 5 GHz): for nal approach, missed-approach and landing guidance  satellite-based: { the American GPS (Global Positioning System) and its Russian equivalent GLONASS: UHF (GHz) with a total of 48 satellites providing world-wide coverage A single navigation aid is insucient for an all-phase navigation process, for instance, guiding an aircraft from start to destination or guiding ships in the sea and around the harbor. The problem is that one system, either doesn't provide enough coverage or doesn't satisfy the accuracy and availability requirements. The solution to this problem is the use of two or more navigation aids, i.e, an integrated approach. The way in which the dierent nav-aids are put together has an impact on the cost, power consumption and weight of the overall receiver. In the case of large ships and aircrafts, these considerations may not be very crucial. At the other end of the market are small aircrafts and boats for which price and probably weight are of importance. There are also areas for which size and powerconsumption of the receiver are of great importance: these include battery-powered hand-held GPS receivers and animal tracking tags [5]. A research on the design of a low-power, low-cost and low-weight integrated navigation receiver has been going on at the Delft University of Technology [2]. This navigation receiver, called GOLLUM, consists of four sub-systems: GPS, OMEGA, LORAN-C, and MLS, gure 1.1. The design approach to achieve the above goals is:

 identify the signal processing similarities between the dierent sub-systems 1

CHAPTER 1. INTRODUCTION

2

 share hardware resources among similar signal processing tasks  nd ecient receiver algorithms and architectures  implement the subsystems using an application-speci c processor (ASP) with

{ application-speci c hardware functional units to perform computationally intensive sig-

nal processing algorithms { general-purpose functional units which execute low rate data processing routines and are shared among the dierent sub-systems

(5 GHz)

(1.2 GHz)

MLS SENSOR

GPS SENSOR

MLS Sub-System

GPS Sub-System

NAVIGATION PROCESSOR LORAN-C Sub-System

RF/IF Sections (possible hardware sharing)

Application Specific Processor (ASP) = Software = Hardware

OMEGA Sub-System RF/IF Sections (possible hardware sharing)

LORAN_C SENSOR (100 kHz)

OMEGA SENSOR (10 kHz)

Figure 1.1: Concept of the GOLLUM integrated navigation receiver Major cost reduction is possible by replacing the precision distance measuring equipment (DMEP), necessary for the operation of the MLS sub-system, with the functionalities of the other sub-systems. Since a 10 ft accuracy of DGPS (dierential GPS) is better than 100 ft accuracy of DME-P, there is no performance degradation. The auxiliary data frames of the MLS sub-system can be used to transmit data necessary for the correction of GPS position estimates [30]. The GOLLUM receiver design is based on the framework of an application speci c processor (ASP) called MOVE [8]. This processor can be customized to the user needs by adding dierent functional units (FUs) and scaling the number of MOVE-buses (data, address and control). The functional units are divided into (i) application speci c FUs which execute computationally intensive tasks and (ii) general purpose FUs which execute less intensive tasks. A MOVE processor customized for GOLLUM's purpose is shown in gure 1.2. The work described in this report considers the design and implementation of MLS data demodulation and data processing functions. The design is divided into a hardware part, which is implemented as one of the GOLLUM's application speci c functional units, and a software part which can be executed on the general purpose FUs of the MOVE processor.

1.1. THE MICROWAVE LANDING SYSTEM

3

Costomized MOVE Processor

Memory (Program & Data) Navigation Software & Sub-systems Routines

General Purpose FUs

FU_1

FU_2

. . .

FU_K To Guidance Mechanisms To & From Pilot

Control Unit

Transport Network

LORAN-C FUs

OMEGA FUs

GPS FUs

MLS FUs

LORAN-C Sensor

OMEGA Sensor

GPS Sensor

MLS Sensor

[100 kHz]

[10 kHz]

[1.2-1.6 GHz]

[5 GHz]

Figure 1.2: The GOLLUM navigation receiver using the MOVE processor concept

1.1 The Microwave Landing System 1.1.1 System Overview The Microwave Landing System (MLS) provides terminal area approach, missed approach, and landing guidance in the form of azimuth angle, elevation angle and data concerning the airport[26]. It is an upgraded version of the Instrument Landing System (ILS) which is being used at many airports. Compared to ILS, MLS is less susceptible to eects of bad weather and landing terrain. These features make it applicable for all-weather, curved approach and automatic landing. MLS uses the time reference scanning beam (TRSB) technique to supply the aircraft with information from the ground antennas. In this technique, radio waves scan the air space in the azimuth and elevation directions. The on-board receiver measures the time dierence between successive interceptions of the scanning waves to determine the horizontal and vertical coordinates of the aircraft relative to the reference, i.e., the runway. Figure 1.3 shows operation of the scanning beam technique. As the beams move in the "TO"scan and "FRO"-scan directions, the aircraft encounters two pulses (bundles). By measuring the dierence between the arrival times of the two bundles, it is possible to determine the angular position of the aircraft relative to the center line. Prior to the start of either scanning beam, a synchronization packet is broadcast over the whole coverage region to tell the air-borne receivers the start of a transmission and its type. In the case of MLS, the scanning beam frequency lies in the range 5031 MHz to 5091 MHz. It is this high frequency that yields narrow scanning beams that are less sensitive to weather and terrain. The MLS standard allows up to 200 channels for simultaneous guidance. Each channel occupies 300 kHz of the frequency band and supports 15 dierent functions to accomplish the guidance process. The functions are classi ed into Data Functions (basic or auxiliary) and Angle Functions elevation or azimuth. The data functions provide information about the airport layout, the status of the ground equipment, and other parameters.

CHAPTER 1. INTRODUCTION

4 -40o

-40o

"TO"-Scan

"FRO"-Scan



signal

reference



reference

scanning beam

scanning beam

+40o

+40o

T1

T0

T2

time

Azimuth (Elevation) Angle:  = V  (T0 ? (T2 ? T1 ))=2 Scanning Speed: V = 0:02o= s

Figure 1.3: The scanning-beam concept

1.1.2 The MLS Signal Format The MLS functions (angle or data) are transmitted in separate time slots at dierent repetition rates. Each slot starts with a preamble which is composed of: (i) a carrier acquisition period, in which an unmodulated signal is transmitted (ii) a 5-bit Barker frame synchronization code, and (iii) a 7-bit function identi cation code (FID). The remainder of the packet consists of information speci c to the transmitted MLS function. While basic and auxiliary data words contain a de ned number of data bits, elevation and azimuth functions contain information in the form of pulse amplitudes at certain time instants during th "TO"-scan and "FRO"-scan intervals. As an example, the detailed packet formats of the basic data words and the angle functions are shown in gure 1.4.

1.1.3 The MLS Receiver Speci cation The task of the air-borne MLS receiver is to extract guidance information out of the incoming MLS signal. The receiver has to satisfy two requirements: (i) the ICAO (International Civil Aviation Organization) speci cations concerning the input signal dynamics and the quality of the output signals [26], and (ii) its architecture should comply with the concepts of the GOLLUM integrated navigation receiver, i.e., resource sharing for low-cost and low-power requirements. The ICAO speci cations on signal level and modulation are tabulated in table 1.1. Using the data in table 1.1, the calculated worst case signal-to-noise ration (SNR) of the received signal is about 5 dB. At all SNR levels, the receiver performance is measured by the number of undetected bit errors [13] and the ability to generate warning signals when unreliable information is received. In this regard, the receiver should guarantee:

 a preamble detection probability of 72%  undetected bit error rate (BER) less than 10?6

1.1. THE MICROWAVE LANDING SYSTEM 0

0.832 Carrier Aquisition

5 1.152

5-bits Barker Code

1.6 [ms] 5-bit Function ID

2-bits Parity

(a) Preamble Format 0

1.6

[ms]

2.88

Preamble

18-bits Data

Guard Time

+ 2-bits Parity

(b) Basic Data Frame 0

2.56

1.6 Preamble

8.76

Sector Signals

To-Scan

9.36

15.56

Pause

Fro-Scan

15.9 [ms]

Guard Time

∆t mid-scan

point

(c) Angle Function Frame 1.6

1.664

Ground Equipment ID

2.048

Antenna Selection

2.176 Rear-OCI

2.304 left-OCI

2.432 Right-OCI

2.56 [ms] To-test

(d) Sector Signals (azimuth function)

Figure 1.4: MLS Basic data and Angle frame formats

 BER after accounting for parity bits less than 10?4  proper validation of both data and angle functions and generation of warning signals Table 1.1: MLS signal speci cations

1 Carrier Frequency Range Number of Channels Transmitter Uncertainty Doppler Shift 2 Signal and Noise Levels Psignal at Coverage Limit Pnoise (in 150 kHz band) Receiver Noise Figure Cable Loss (front-end to IF stage) Margin 3 Modulation Type Bit Rate Logic "0" Logic "1"

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5.031 GHz to 5.091 GHz 200 each 300 kHz wide  10 kHz  5 kHz

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-95 dBm -122 dBm 11 dB 5 dB 6 dB

: : : :

DPSK (dierential phase shift keying) 15.625 kHz 0  10 180  10

In order to be applicable for GOLLUM, the receiver should meet additional requirements:

 performing signal processing in the digital domain as far as possible to allow integration on

the MOVE processor  implementing signal processing functions in software as timing constraints allow  resorting to an application-speci c hardware unit either when the timing requirements can't be met with shared hardware resources, or if the hardware alternative is relatively cheaper.

6

CHAPTER 1. INTRODUCTION

The rst condition is advantageous in reducing the component count and avoiding problems associated with analog designs, which improves the reliability of the design. The software approach, if applicable, is always preferred as it simpli es the design process and allows for later updates.

1.2 Report Outline The remaining part of this report is divided into 4 chapters. Chapter 2 discusses the MLS receiver architecture and gives a comparison of dierent DPSK demodulation techniques. The design and implementation of the data demodulation and processing units is given in chapter 3. In chapter 4, simulation results are given with which the functionality of the designs is veri ed. Finally, a conclusion is given in chapter 5.

Chapter 2

The MLS Receiver Architecture and its Design Overview 2.1 MLS Receiver Architecture From the MLS signal de nition in the previous chapter, it is clear that the receiver will consist of dierent signal processing stages:a front-end, an intermediate-frequency (IF) stage and a post-IF stage. Figure 2.1 shows the block diagram of the MLS receiver. Even though the emphasis of this report is on the design of the data demodulation and processing unit of the post-IF stage, a short introduction to the other other functional blocks of the receiver helps to have a global picture of in the design of navigation receivers.

5 GHz Envelope Detected

Front-end

1st-IF signal Clock1

IF-Stage Hard-Limited

Post-IF Digital Signal Processing

To/From Central Navigation Processor

2nd-IF

Clock2 Channel Select

Reference Oscilator

Figure 2.1: Functional blocks of the MLS receiver

2.1.1 The Front-end The front-end of the MLS receiver transforms the UHF (ultra-high frequency) signal into an intermediate frequency (IF) signal. The frequency translation is achieved with the help of microwave 7

8 CHAPTER 2. THE MLS RECEIVER ARCHITECTURE AND ITS DESIGN OVERVIEW mixers. The reference clock is synthesized according to the channel select command. The clock frequency keeps the mixer output at the same IF frequency. The block diagram of the front-end if shown in gure 2.2. The design of a monolithic MLS front-end IC is described in [15]. 5031 - 5091.5 MHz

- Mixer - Amplifier

1st-IF signal

( BW = 71.5 MHz)

(73 MHz)

Clock_1 Frequency Synthesizer (200 channels)

Clock_2 (68 MHz)

Channel Select Reference

Figure 2.2: Block diagram of the MLS front-end The frequency synthesizer also generates clock signals for the IF and post-IF signal processing stages. In accordance with GOLLUM's hardware sharing principle, this synthesizer can supply the clock signals of the other navigation subsystems as well.

2.1.2 The Intermediate Frequency Stage In addition to amplifying the input signal, the task of the IF stage includes

 mixing down the input rst-IF signal to a 5 MHz  limiting the signal bandwidth to 150 kHz to restrict noise and adjacent channel interference.  performing a logarithmic amplitude detection to extract the envelope information for angle

processing, and  hard-limiting the ltered 5 MHz IF signal for use in data demodulation

The logarithmic detection enables the receiver to overcome the large dynamic range variation of the input signal with the relative distance of the aircraft from the transmitting antenna. In addition to removing the dynamic range variation, the hard-limiting simpli es the design of the data demodulator. The block diagram of the IF stage is shown in gure 2.3. The design and implementation of this stage using standard IF components is discussed in [9].

2.1.3 MLS Post-IF Signal Processing The MLS post-IF signal processing is indicated in the block diagram of gure 2.4. There are two distinct signal processing tasks: (i) angle processing, which computes the time dierence between the "TO" and "FRO" pulses after linearizing the envelope detected signal and (ii) data demodulation and processing, which is responsible for synchronizing the receiver to the incoming information packets and extracting data that is required for the actual position computation.

2.2. DESIGN OVERVIEW

9 sampling clock (1 MHz)

1st-IF signal (73 MHz)

Logarithmic Detector

- Mixer - Amplifier

LPF (BW = 39 kHz)

A/D Converter

8

Hard Limiter

(BW = 150 kHz)

envelope signal 2nd-IF signal (5 MHz)

Clock_2 (68 MHz)

Figure 2.3: Block diagram of the Intermediate Frequency Stage RE-START

- Carrier Acuisition - Clock Synchronization - Data Demodulation - DPSK Decoding

2nd-IF signal (hard limited)

decoded bits

- Receive Data Bits - Check for Parity - Check for Consistency - Update Validation Flags

Data Word(s) Warning Signals

- Reset Receiver to Acquisition mode Barker Code Test

FAIL RE-START

PASS

FID Test

envelope signal (from A/D)

FAIL

- Read a DPSK bit to build Morse Code

Morse Code Antenna Select

data function

- Read and Process Envelope Samples

angle function

- Reset Receiver to Acquisition mode

OCI signal Guidance signals

8 RE-START

Figure 2.4: MLS post-IF signal processing The post-IF tasks have been assigned to the digital part. With respect to angle processing, this is the best choice as the corresponding algorithms can be easily implemented in software. Such an approach has been followed in [19, 28]. [19] also discusses a software based approach to the data demodulation and processing tasks. The approach followed in this work, on the other hand, resorts to a hardware approach for the data demodulation and part of the data processing. The choice of the hardware approach is due to the computational complexity of the software algorithms for implementation on a MOVE processor with resources shared among dierent applications. After describing the design strategy followed during the course of the work, dierent DPSK demodulation techniques and their performance are discussed in the following sections.

2.2 Design Overview Figure 2.5 shows the design process of the data demodulation and processing part of the MLS sub-system. In phase 1, the performances of dierent demodulator architectures were studied and the candidate architectures, those which satisfy the performance requirements, were checked for applicability in GOLLUM. The software alternative was analyzed using the MOVE simulation

10 CHAPTER 2. THE MLS RECEIVER ARCHITECTURE AND ITS DESIGN OVERVIEW framework, in which a typical processor architecture can be de ned for studying the complexity of the dierent algorithms. In phase 2, functional simulations were conducted using a behavioral description (a "C" program) to verify the dierent demodulator functions of the selected digital hardware architecture. In phase 3, the logic design, simulation and layout of the demodulator hardware were done using the OCEAN/NELSIS IC design tools [17]. The design was put into the data base using the SLS (Switch Level Simulator) [10] language. The nal realization of the design was conducted at the DIMES (Delft Institute of Microelectronics and Submicron Technology) IC design facilities. Problem Definition (MLS requirements)

Constraints: - GOLLUM specs.

Compare & Select a Design Method

Design Choices: - Analog vs Digital - Hardware vs Software

Facilities: - MOVE Processor simulation framework

Functional Simulation ("C"-language)

Physican Design: - design entry(SLS) - layout, extraction - simulation

Phase-1

Phase-2

Design Tools: - OCEAN/NELSIS

Realization: - sea-of-gates metalization

Phase-3

DIMES

Figure 2.5: Design Trajectory of the MLS data demodulator

2.3 DPSK Demodulation Techniques At the transmitter end, the MLS data bits are dierentially encoded prior to binary phase modulation of the carrier. This dierential encoding avoids potential phase ambiguity at the receiver end [7, 25]. Figure 2.6 shows the dierential encoding unit which applies a modulo-2 addition (XOR) on the current bit and the one before it. The DPSK modulated signal can be written as s(t) = m(t)A cos(!t + ) (2.1) where m(t) = 1 if dn = 0 and m(t) = ?1 if dn = 1. A and !o are the carrier amplitude and frequency respectively. The phase  represents the carrier phase oset from the ideal 0 or 180 values. The demodulation process in the receiver consists of the reverse process, DPSK decoding, which restores the original binary sequence. Depending on whether a local reference carrier phase is needed or not, the DPSK demodulation can be coherent or incoherent [7, 25].

2.3.1 Incoherent DPSK Demodulation As the name indicates, this technique requires no reference carrier phase for the demodulation process. The local oscillator is needed for frequency down conversion only. Figure 2.7 shows

2.3. DPSK DEMODULATION TECHNIQUES DPSK Encoder bit in

11

Modulator

s(t)

dn

XOR

"0" "1"

T

-1

c(t) = A cos(!t)

Figure 2.6: DPSK Modulation a receiver structure based on incoherent DPSK demodulation technique. It consists of an input bandpass lter which removes noise and interfering signals. The lter output is multiplied by its 1-bit delayed version and lowpass ltered to form a decision variable. cos(!i t)

Receiver r0 (t)

Mixer

Bandpass lter

Demodulator & DPSK decoder r1 (t) r2 (t) LPF Decision

bit out

Tb n(t) White Noise

sin(!r t) Local Reference

Figure 2.7: Incoherent receiver structure Including an additive white Gaussian noise (AWGN) and attenuation, the received signal is given by r0(t) = m(t)Ar cos(!i t + ) + n(t) (2.2) Under noise free conditions the multiplier output is given by r1 (t) = m(t)m(t ? T)A2r cos(!o t + ) cos(!o (t ? Tb ) + b) = 0:5m(t)m(t ? Tb )A2r cos(!o Tb +  ? b ) + 0:5m(t)m(t ? Tb )A2r cos(2!0t + !o Tb )

(2.3) (2.4)

where !o is the local reference carrier frequency and b is the carrier phase oset (from the ideal values 0 or 180) at the previous modulation instant. When the high-frequency component of r1 (t) is ltered out, the decision variable becomes r2 (t) = 0:5m(t)m(t ? Tb)A2r cos(!o Tb +  ? b )

(2.5)

12 CHAPTER 2. THE MLS RECEIVER ARCHITECTURE AND ITS DESIGN OVERVIEW In the ideal case, there is no modulation phase oset (i.e.,  = b = 0) and the carrier frequency is an integral multiple of the bit rate (i.e., !o Tb = k  2 or fo = 2k=Tb, where k is an integer). Under this condition, a threshold of zero gives a decision output "0" if r2 (t) > 0 and "1" if r2(t) < 0. This is equivalent to saying the output becomes "0" if the successive bits are the same and "1" otherwise, which implies DPSK decoding.

Performance in a Noisy Environment The received noise power is limited by the input bandpass lter. A bandpass ltered AWGN (additive white gaussian noise) noise can be represented by [7, 25] n(t) = nc (t) cos(!o t) ? ns (t) sin(!o t)

(2.6)

The variance of the total noise n(t) is the same as the variances of its components nc and ns . The inputs to the multiplier are given by r0(t) = (m(t)Ar + nc (t)) cos(!o Tb ) ? ns (t) sin(!o t) r0 (t ? T) = (m(t)Ar + nc (t ? Tb )) cos(!o (t ? Tb )) ? ns(t) sin(!o (t ? Tb ))

(2.7) (2.8)

After lowpass ltering and assuming fo = 2k=Tb, the multiplier output becomes r2 (t) = [m(t)Ar + nc (t)][m(t ? Tb )Ar + nc(t ? Tb )] + ns(t)ns (t ? Tb )

(2.9)

The noise components in the above equation introduce decision errors. The resulting bit error rate (BER) in the case of matched ltering is given by [7] A2r ) Pe = 12 exp(? 2 2 1 = 2 exp(? b ) (2.10) Where b is called system parameter and is also given by Eb=No , where Eb = A2r Tb is the bit energy and No is the one-sided noise spectral power density. The MLS speci cations require a BER  10?4 at the coverage extremes where the signal to noise ratio is 5 dB. According to the MLS speci cations, the total noise power at the receiver output equals 2 = ?122 + 11 = ?111 dBm over a bandwidth of 150 kHz and the signal power ?95 ? 5 ? 6 = ?106 dBm. The corresponding system parameter is b = 31:8 and eqn. ( 2.10) yields a BER of 7.7310?15. Thus, there is a large margin compared to the speci cation Pe < 10?4.

Practical Limitations of Incoherent Demodulation The above BER value assumes an ideal situation where the cos(!o Tb +  ? b ) factor in the decision variable is exactly equal to one. A real incoherent receiver is in uenced by the following non-idealities:

 frequency uncertainties of the transmitter and receiver oscillators  Doppler shift  error (
Tb) in the physically realizable delay time, and

2.3. DPSK DEMODULATION TECHNIQUES

13

 uncertainty ( = 10 ) in the modulation phase The receiver performance deteriorates due to phase error caused by the above non-idealities. The total phase error is expressed as [23]

The BER formula changes to

e = 2(f0 +
f)(Tb +
T) + 2

(2.11)

e )2 ) Pe = 12 exp(? (Ar cos 2 2

(2.12)

A BER lower than 10?4 requires cos(e ) > 0:52 or e < 58:8. A typical value for the delay time error is
T = 10 ns (assuming a glass delay-line type implementation operating) [29]. Thus, the allowed carrier frequency uncertainty becomes
f < 1:6 kHz, using e  2
fTb + 2. However, the MLS speci cation requires proper operation with a transmitting oscillator uncertainty of 10 kHz and a Doppler shift of 5 kHz. Adding an additional receiver oscillator uncertainty equal to that of the transmitter, the total frequency uncertainty amounts to 25 kHz. This implies that the simple incoherent receiver structure cannot be used. One method to reduce the in uence of frequency uncertainty is to use the quadrature autocorrelator shown in gure 2.8 [23]. In this approach the input signal and its 90 shifted version are multiplied with the input signal delayed by Tb and ltered to reject the double frequency component. The largest of the multiplier outputs forms the decision variable. Out 1 90o bandpass ltered signal

LPF Choose Largest

Tb

LPF

Decision Device

Data Out

Out 2

Figure 2.8: Quadrature autocorrelator for DPSK demodulation Depending on the input phase, one of the quadrature outputs will have a larger magnitude. Thus, by comparing the two amplitudes and choosing the larger one, it is possible to limit the phase error magnitude to e;max = 45 for n arbitrary frequency uncertainty. This error is below the limiting value, 58 , and, hence, the BER requirement can be met. However, if the phase error is is close to 135 or 315, i.e., for frequency uncertainties close to 5 kHz or 12.8 kHz, a small frequency drift will result in a polarity change in the demodulated bits and hence introduce errors. For instance, an oscillator frequency drift of 50 Hz/s and a Doppler drift of 16.5 Hz/s (due to acceleration or deceleration) result in a total drift of (50 + 16:5)  64Tb = 0:272 Hz during the maximum 64 bit duration time. The corresponding phase drift is 2  0:272  64Tb = 0.007 rad = 0:4o . Since aircraft landing is a safety critical application, error sources like this should be avoided.

14 CHAPTER 2. THE MLS RECEIVER ARCHITECTURE AND ITS DESIGN OVERVIEW

2.3.2 Coherent Data Demodulation Despite its simplicity, the incoherent technique fails to satisfy the MLS BER requirement. The performance degradation is caused by the large phase error that is associated with the frequency uncertainty. This can be overcome by using phase lock techniques{coherent demodulation [7, 25]. The drawback of this approach is the design and hardware complexity of the phase-locked loops. The rst task of a coherent demodulator is to form a local reference clock which is phase locked to the incoming carrier signal. The MLS signal format provides a carrier synchronization interval of 832s at the start of the preamble. In the tracking mode, data bits arrive in the form of phase modulations. To keep the PLL locked during this interval, the phase modulation must be removed from the PLL input. This can be done in three ways [16]: (i) the squaring loop (ii) the Costas loop and (iii) the remodulation loop. The last two techniques are relatively simple to implement and are discussed in the following sub sections.

The Costas Loop Figure 2.9 shows a Costas carrier recovery loop. The incoming signal is multiplied with the quadrature outputs of the VCO and the products are lowpass ltered to reject the double frequency component and noise. When the lower section of the loop acts as a PLL the upper section acts as a demodulator or vice-versa. The modulation removal is done by multiplying the branch signals. The product is input to the loop lter F(s) to form an error signal that drives the VCO (voltagecontrolled oscillator). To Decision, Decoding & Synchronization

LPF

vi(t) r0 (t)

VCO

zf (t)

F(s)

z(t)

x(t) y(t)

90

vq (t)

LPF

Figure 2.9: A Costas loop based demodulator The input signal, r0 (t), and the two outputs of the VCO can be written as r0 (t) = m(t)Ar cos(!o t + in); vi (t) = cos(!o t + out ); vq (t) = sin(!o t + out)

(2.13)

The lowpass ltered branch signals and the loop lter input are given by x(t) = 0:5m(t)Ar cos(in ? out) y(t) = 0:5m(t)Ar sin(in ? out ) z(t) = x(t)y(t) = 0:25(m(t)Ar )2 sin2(in ? out)

(2.14) (2.15) (2.16)

The last equations shows that the squaring removes the modulation m(t) = 1, from the VCO input. For a small phase error, e = in ? out, the sine term can be replaced by the argument

2.3. DPSK DEMODULATION TECHNIQUES

15

and a linear loop analysis can be done. The phase error, which includes phase noise, is twice as large as that of a simple phase-locked loop and requires modi cation in the loop stability analysis. When the loop is locked, the phase error is ideally zero and either x(t) or y(t) becomes the demodulated signal. Some kind of amplitude test is needed to determine which is which.

The Remodulation Loop Figure 8 shows one version of a remodulation loop for carrier recovery [16]. The modulation removal is done by multiplying the demodulated data with the quadrature output of the VCO. This product is then multiplied with the input signal to obtain a measure of the phase error. r0 (t)

LPF td z (t)

phase detector w (t)

F(s)

zf (t)

vi (t)

To Decision, Decoding & Synchronization

VCO 90 vq (t)

x(t)

remodulator

Figure 2.10: A Remodulation loop based demodulator When the input signal, the two VCO outputs, and the demodulated signal are expressed as before. the product between the demodulated data and one of the VCO outputs becomes w(t) = x(t)vq (t) = m(t)Ar cos(in ? out ) sin(!o t + out) (2.17) The input to the loop lter is given by z(t) = r(t)w(t) = 0:5(m(t)Ar )2 cos(in ? out)[sin(in ? out + sin 2(!o t + out + in)] (2.18) After ltering by F(s) the VCO drive signal becomes zf (t) = 0:5(m(t)Ar )2 cos(in ? out ) sin(in ? out) = 0:5(m(t)Ar )2 sin 2(in ? out ) (2.19) Like the Costas loop, the VCO drive signal is a function of twice the phase error and is free from input modulation. To compensate for the delay in the lowpass lter, the input signal is delayed by td before input to the phase detector. Without this compensation, the correlation between the input and the demodulated data decreases and the average (useful) signal that drives the VCO decreases making the loop susceptible to noise. One drawback of this demodulator structure is the performance degradation due to the delay unit. For proper operation it is required that the delay introduces no frequency dependent phase oset,

16 CHAPTER 2. THE MLS RECEIVER ARCHITECTURE AND ITS DESIGN OVERVIEW i.e., !o td = k  2 where k is an integer. Satisfying this condition becomes dicult if the carrier frequency has large uncertainty. To avoid the need for delay compensation, the lowpass lter can be moved out of the loop. This is possible as long as noise is suciently ltered by a preceding bandpass lter. In this case the component at 2!0 passes un ltered to the subsequent processing. Its eect can be seen from the following equations xhf (t) = m(t)Ar cos(2!o t + i + o ) whf (t) = xhf (t)vq (t) = 0:5m(t)Ar [sin(!o t + i) + sin(2!o t + i + o )] zhf (t) = whf (t)r(t) = 0:25(m(t)Ar )2 [sin2(!o t + i ) + sin(!o t + o ) + sin(3!o t + 2i + o )] (2.20) From the above equation we see that the un ltered component at the demodulation branch contributes to high frequency components that can be ltered by F(s).

Performance in a Noisy Environment The BER performance of coherent data communication systems is better than that of incoherent systems. This can be seen by comparing the error probability of an incoherent system to that of a coherent system [7]: p (2.21) Pe = Q( 2 b ) = p2 1 2 exp(? b2 ) b

b = Eb=No = A2r =2

where is the system parameter as before. For the MLS signal and noise speci cations, the system parameter becomes b = 31:8 and the corresponding error probability Pe = 7:74  10?16. This is an order of magnitude better than the error probability of an incoherent system. Compared to the speci cation Pe < 10?4, there is a large margin to allow for some performance degradations in the receiver. The above BER calculation assumes ideal coherent reception with matched ltering. In a practical receiver the BER performance depends on the con guration of the carrier recovery loop, i.e., by how well the noise is ltered prior to the modulation removal. The phase error, e = i ? o , is aected by the input noise and is randomly distributed with the probability density [12]: cos 2e) (2.22) p(e ) = exp(D Io (D) ; jej < =2 where D =  b =(1 + 1=(2y b )) and Io (D) is the modi ed Bessel function of 0-th order. The variables b ; ; and y are de ned as follows: datarate(fb ) ; y = 2  LoopBandwidth(BL ) (2.23)

b = Eb=No ;  = LoopBandwidth(B InputBandwidth(Wi ) L) As a consequence of the random phase error, the decision process makes occasional errors which increase the BER beyond the theoretical value. In the case of DPSK signal detection the conditional bit error probability and the average BER are given by [20] PE (e ) = 21 exp(? b cos2 e ) (2.24) Z =2 PE = p(e )PE (e )de (2.25) ?=2

2.3. DPSK DEMODULATION TECHNIQUES

17

The loop noise bandwidth, BL  Wi , is the only parameter that can be controlled to meet a certain error level. In the case of MLS, the xed parameters are: b = 31:8, fb = 15:625 kHz and Wi = 150 kHz. Choosing BL = fb yields  = 1 and y = 1=4:8. Computing the above integral numerically, we get a bit error probability of 1.3510?14. Even though this is higher than the theoretical value, there is still a large margin from the allowed error rate, 10?4. The above result is valid in the absence (rarity) of cycle slippage; otherwise, the steady state bit error probability is just 0.5. The PLL cycle slip rate decreases with increasing signal-to-noise ratio (SNR). The average time between cycle slips can be approximated by [16] (2.26) TAV  4B exp(4SNRL ) L where the loop SNR is given by Wi SNRL = SL  SNRi 2B (2.27) L The factor SL = 1=(1 + 0:5SNRi) accounts for the increase in phase noise variance due to noise products (noise  noise and signal  noise) in the carrier recovery loop [25]. The loop SNR should be chosen large enough to minimize the cycle slip rate or increase TAV . For instance, SNRi = 3:16 (5 dB) and BL = fb = 15:625 kHz give SNRL = 0:39  15:17 = 5:88 and TAV = 8:2  105 sec, which is practically large enough. As a comparison, if BL = 2fb = 31:25, we get SNRL = 2:94 and TAV = 3:2 sec, which is very small. To obtain a measure for the other PLL parameters, such as acquisition range and speed , it is important to derive the loop transfer function. A second order PLL is the obvious choice for constructing the carrier recovery loop since it requires a relatively simple design and analysis eort and gives an extra degree of freedom to satisfy contradicting requirements. The phase transfer function of a second order PLL is given by [16] n s + !n2 H(s) = o = s2 2! (2.28) + 2!ns + !n2 i where  is the damping and !n is the loop natural frequency. For an optimal settling behavior  = 0:7 is chosen, giving a noise bandwidth of BL = 0:53!n. From the discussion on cycle slipping, BL = 15:625 kHz was found to give an acceptable rate of cycle slip. Thus, the upper bound on the loop natural frequency can be given by !n < BL =0:53 = 29:5 krad=s (2.29) According to the MLS speci cations, the carrier recovery has to be completed within the rst 832 s of the preamble. When the carrier frequency is in the direct capture range of the PLL, acquisition is a fast process with settling and lock times [11]: t5%  3=(!n) (2.30) tL  1=(!n) (2.31) To satisfy the condition tL < 832 s, and assuming  = 0:7, we require !n > 1717 rad=s (2.32) Since the carrier frequency has an uncertainty of 25 kHz, the carrier recovery can take longer than 832 s due to a slow pull-in process [16]. Thus, the loop natural frequency has to be chosen larger than the above lower limit to speed up acquisition. A parameter in this regard is the lock-in

18 CHAPTER 2. THE MLS RECEIVER ARCHITECTURE AND ITS DESIGN OVERVIEW range, which is the frequency range over which phase lock can be achieved without cycle slipping. For a sinusoidal phase detector, it can be approximated by
!L  2!n

(2.33)

For an XOR PD the lock-in range is =2 times higher.To have a lock-in range that covers the MLS carrier uncertainty of 25 kHz, we have to meet the following condition !n > 2  11:4 = 71:4 krad=s

(2.34)

where  = 0:7. Comparing eqns. ( 2.29 & 2.34), we can see that satisfying the noise bandwidth and lock-in range requirements simultaneously is impossible. If we choose !n = 29:5 krad/s to satisfy the rst condition, the loop will still lock at frequencies outside its lock-in range, !n = 64:87 krad/s or 10.33 kHz, but after some cycle slipping, i.e., a slow pull-in process. Thus, it is necessary to provide some sort of acquisition aid. Finally, even though both Costas and remodulation loops are functionally equivalent, the latter is preferred since it requires one less lowpass lter and doesn't need an additional hardware to detect which one of the quadrature branches is in-phase with the input, which is the case with the Costas loop.

Chapter 3

Design and Implementation of MLS Functional Units In the previous chapter, dierent data demodulation methods have been discussed and the need for a coherent approach emphasized. Implementation determines such receiver aspects as cost, reliability and maintenance. Conventional systems employ analog techniques to implement the synchronization and demodulation functions. With the development of VLSI technology and high-speed DSPs, the above receiver functionalities plus other signal processing functions can be realized in the digital domain [19, 4, 11, 22]. In this chapter, we rst discuss dierent demodulator implementation possibilities, analog vs. digital and hardware vs. software, and then give the detailed design of the chosen digital-hardware.

3.1 Implementation Considerations It is possible to meet the demodulator performance requirements in one of the three implementations: analog, software or digital hardware. Thus, the implementation choice needs additional criteria. The requirements of GOLLUM (such as low-power and low-weight) together with reliability and maintenance features can be used as selection criteria.

3.1.1 DPSK Demodulation in the Analog Domain Both coherent and incoherent demodulation schemes can be implemented in the analog domain. Like all other analog systems, demodulators based on analog techniques suer from a number of disadvantages such as supply voltage variation, component parameter change due to tolerance, temperature variation and aging. Especially, the coherent method which is implemented using an analog or a semi-analog PLL is sensitive to these factors because the VCO's center frequency can deviate by up to 20%. A consequence of this parameter deviation is the need for adjustment of certain parameters from time to time. From integration point of view, the whole demodulator except for the lter components can be put on one IC. An example implementation of a coherent MLS receiver which uses a remodulatorloop based DPSK demodulator is reported in [3]. This implementation makes use of a limiter, the NE564 PLL IC with external resistors, capacitors, a few XOR gates (to implement multiplier functionality) and comparators. In [31] the acquisition behavior of a 2nd-order PLL based on NE564 is studied with the help of simulations and experiments for the noise free situation. The 19

20

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS

results indicate that the IC satis es the acquisition requirements over the whole carrier frequency range. Further study of the demodulator performance in the presence of noise is required. Simulations and experiments with the incoherent technique show that it requires a good carrier frequency estimation (not necessarily phase) to work properly [29]. The hardware complexity of a frequency locked loop (FLL) is equivalent to that of a PLL indicating that no signi cant improvement is achieved in receiver complexity compared to the coherent approach.

3.1.2 Software-based Digital DPSK Demodulation Both coherent and incoherent data demodulation schemes can be implemented in the digital domain either in software or hardware. A classi cation of dierent digital PLL architectures can be found in [21] some of which are suited for software implementation and the others for hardware. Due to the computational complexity, the coherent approach (carrier tracking software PLL running in parallel with data demodulation, decoding, and synchronization functions), the incoherent method was adopted in [19] to design an MLS post-IF processor using the ADSP2100A digital signal processor. In what follows we brie y describe the algorithm used in [19] and see if its complexity can be accommodated inside GOLLUM. Figure 3.1 shows the block diagram of the post-IF signal processing tasks. It accepts two digitized inputs from the IF-section: (i) a DPSK modulated signal and (ii) an envelope detected signal at a sampling rate of 625 kHz. The rst input is used in carrier synchronization (coarse and ne acquisition) and subsequently data demodulation and processing. The second input is used in the angle processing unit. Sampler 16-bit

DPSK-mod. signal

Coarse Acquisition

ADC

Envelope signal 1.125 MHz

Decimation Filter

Fine Acquisition Demodulation Decoding Syncronization

To Data Processing

To Angle Processing

Figure 3.1: Software-based MLS data demodulation

Coarse Acquisition This is the rst step in the carrier synchronization process. It starts when signal presence is detected from the envelope information and provides an estimate of the carrier frequency accurate to 10 kHz. Figure 3.2 shows the sequence of tasks in the coarse acquisition process. The rst step, a 16-point FFT, determines the carrier frequency with an accuracy of 0:5fs =16 = 19:53 kHz, for fs = 625 kHz. Following this a 32-point DFT is computed at the 3 most strong frequency bins and reduces the estimation error by half to 9:7656 kHz. A lower limit to the time needed for coarse acquisition is the sample collection period, (16 + 32)=fs = 76:8s.

3.1. IMPLEMENTATION CONSIDERATIONS

21

data samples (fs = 625 kHz) 16-point FFT

32-point DF T at 3 bins

select 3 strongest bins

select the strongest bin

Coarse Frequency Estimate

Figure 3.2: The coarse acquisition algorithm

Fine Carrier Acquisition To use the incoherent demodulation technique, the frequency uncertainty must be further reduced to less than 1:6 kHz (see section 2.3.1). Even though the DFT method could be applied for this purpose, [19] employs a computationally less complex approach based on an automatic frequencylocked loop (AFC) as shown in gure 3.3. The resources it needs, i.e., a sine-cosine table and two Hilbert transform lters, are also used in the data demodulation phase. Hilbert Transform & Decimation Filters HBP I s(nT1 ) HBP I

Complex Mixer (Phase Rotator)

x.I x.Q

z.I Initialize to Coarse Frequency

Cross Product Detector + y.I + +

DELAY T2

y.Q

DELAY T2

+

z.Q

Numerically Controlled Osc. (NCO)

c(nTs2 ) (frequency error)

Lock Detect

Figure 3.3: Block diagram of AFC-based ne acquisition The rst task is to reduce the sampling rate by factor 10 to 62.5 kHz, which is 4 times the bit rate 15.625 kHz, using the decimation lters. The lters also provide a Hilbert transform which converts the input signal into quadrature components. These components are then mixed to the quadrature outputs of an NCO (numerically controlled oscillator). The mixer is a phase rotator which produces outputs that contain the error frequency terms only, i.e., no lowpass lters are needed to remove the component at twice the input frequency. A measure of the frequency error is obtained with a cross product detector which drives the NCO. The NCO is initialized to the coarse frequency estimate found earlier.

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS

22

Data Demodulation, Decoding and Synchronization Figure 3.4 shows the software data demodulation technique adopted in [19]. The structure is very similar to the ne acquisition loop discussed earlier. Now the NCO frequency is xed at the value found by the ne acquisition process. The dot product detector transforms the mixer outputs into a DPSK decoded (by the delay and multiply unit). The two quadrature inputs make sure that the output is not aected by phase dierence between the input signals and the NCO outputs. Hilbert Transform & Decimation Filters HBP I

x.I

HBP I

x.Q

s(nT1 )

Set to Fine Frequency

Complex Mixer (Phase Rotator)

z.I z.Q Numerically Controlled Osc. (NCO)

Dot Product Detector + y.I - + +

DELAY Tb

y.Q

DELAY Tb Barker Code Synchronization Integrate & Dump Filter and Decision To Data Processing

Figure 3.4: Data demodulation in the software domain Following the DPSK decoding, synchronization is done to look for the 5-bit Barker frame synchronization code. The demodulation is completed after extra ltering by the integrate and dump unit.

Computational Complexity The software approach described so far has to be veri ed to see if it is applicable for use in the GOLLUM environment. We would like to see if the MOVE processor can execute the above signal processing algorithms and at the same time service the other sub systems. To study the complexity of the software approach, representative algorithms were written in the "C" programing language and simulated on a typical MOVE machine using the available MOVE framework [8]. Figure 3.5 shows the MOVE simulation framework. The processor architecture is de ned in the machine description le, "mach". It consists of the number of buses, the number and type of functional units (adders, multipliers, etc.) and their interface to the buses. The execution time and resource usage information are used to study the complexity of the algorithms. Figure 3.6 shows the simulation results of the coarse and ne acquisition algorithms. Since the same operations are repeated for every sample, the ne acquisition is simulated for one sample only. A 100 MHz MOVE processor with 2 buses and all the necessary functional units was used. We can make the following observations from the results:

 the processor busses operate at about full capacity for 150s during coarse acquisition and for 7:14s during ne acquisition.

3.1. IMPLEMENTATION CONSIDERATIONS Algorithm Description "C"

23

"gcc-MOVE" Compiler Scheduling

(sequential code)

Parallel Simulation

Sequential Simulation (# of "moves" & resource usage)

# of "move"s (code size & execution count)

Profiling Information

Define/Update the MOVE architecture

Designer’s Decision

Result

Figure 3.5: MOVE simulation framework Parallel Simulation

Algorithm

CoarseAcquisition (DFT-based)

x(nTs ) [Ts = 1:6s]

10 Fine Acquisition (AFC-based)

Code Size

Execution

Bus Usage

1110 moves

(2.2 kB)

27001 moves (15003 cycles)

98%, 82%

1550 moves (3.1 kB)

1331 moves (714 cycles)

91%, 75%

MOVE Machine: - 2 buses, FUs - 100 MHz clock

Figure 3.6: MOVE simulation Results

 data demodulation, by the algorithm similarity to ne acquisition, will also take about 7:14s. This leaves about 50% of the decimated sampling interval for other GOLLUM tasks.  transporting 2-MOVE instructions per cycle, the o-chip instruction access rates become: (27000=2)=150s = 90 MHz for coarse acquisition and, (1331=2)=16s = 41.6 MHz for ne acquisition or demodulation. These are beyond what present memory units can provide.  because of the memory sizes, a cache cannot be used to keep the algorithm codes on-chip, at least not on the sea-of-gates chip which is inecient for memory design

The nal conclusion is that the software approach is not suitable for use in the GOLLUM receiver design unless we provide a separate MOVE processor for the MLS sub-system.

3.1.3 Hardware-based Digital DPSK Demodulation Having seen the computational complexity of fully-software data demodulation, it is time to investigate the hardware implementation alternative. From GOLLUM's perspective this ts into one of the application-speci c functional units of the MOVE processor dedicated for unique signal

24

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS

processing tasks. When the hardware cost is not prohibitive, this is a sound alternative for the following three reasons:

 demodulation in the digital domain means no analog related problems and hence high reli-

ability and less maintenance  possibility of integration implies a compact receiver structure, a plus for the low-weight design objective  needs minimal processor involvement allowing a single MOVE processor to be shared among dierent applications. In this section dierent all-digital phase-locked loop, ADPLL structures are discussed. They form the heart of the MLS data demodulation hardware that is the focus of the remaining parts of this report. We select a couple of ADPLL architectures which are suitable for digital hardware implementation and brie y discuss their principles of operation. An extensive discussion of dierent ADPLLs can be found in [21, 18, 4, 11, 27]. The rst step in the design of PLLs is determining the loop order that can accommodate the input signal dynamics. In our case, the fact that the MLS carrier frequency exhibits some uncertainty necessitates the use of a second-order phase-locked loop. Three 2nd-order ADPLL structures are considered: (i) cascaded ADPLL [21, 27, 18] (ii) parallel ADPLL [18] and (iii) rate-multiplier based ADPLL [11, 18].

Cascaded 2nd-Order ADPLL A cascaded 2nd-order ADPLL is built from two rst-order sections by connecting them as shown in gure 3.7. Output of the upper 1st-order section is connected to the input of the lower section via a divider. The clock input of the upper section is obtained from the lower section. The signal lines connecting the dierent blocks and the input signal are all single bit allowing extensive use of standard CMOS counters to implement the division functions. The phase-detectors (PD) are either multiplying type, implemented using an XOR gate, or edgedetecting type, implemented using a JK ip- op. The multiplying type phase detector will be considered here after for its superior performance in the presence of noise [16, 22]. Figure 3.8 shows the XOR phase detector characteristics. The phase error (e) is zero when the input signals have a 90 phase dierence (d ). The phase detector gain is given by kd = e=ve = 2=, where ve is an "error voltage" equivalent to the XOR output. This phase error is averaged by the K-counter which generates carry or borrow pulses depending on the phase error polarity. The carry and borrow pulses are used by the increment/decrement (I/D) unit to advance or retard the phase of its output by  radians, which would otherwise have uniformly distributed pulses at half the clock frequency. The N-counter averages the pulse irregularities of the I/D-unit to form the PLL output which is input to the phase detector and closes the loop. Designing an ADPLL for a particular application means setting the dierent loop parameters: clock frequency (fc ), counter length (K1 ; K2 ; N1 ; N2 ; L) and the loop center frequency (fo ). The parameters are determined based on the dynamics of the input signal: its expected frequency (fo ), the frequency uncertainty (
f), input signal-to-noise ratio (SNRi ) and the available acquisition time. The theory of PLLs [16] indicates that the behavior of a 2nd-order PLL is fully described by two variables: loop bandwidth, !, and damping coecient, . Thus, we need to express the phase transfer function of the ADPLL in terms of fo ,
f, fc , N1 , N2 , K1 , K2 . This is done using the frequency domain model of the ADPLL shown in gure 3.9, in which N1 = N and N2 = 2N have

3.1. IMPLEMENTATION CONSIDERATIONS

Input

PD1

25 carry

K-Counter1

borrow

Output

Inc-Dec Unit

N-Counter1

L-Counter PD2

carry

K-Counter2

borrow

Inc-Dec Unit

Master Clock (fc)

N-Counter2

Figure 3.7: A second-order ADPLL formed by cascading two rst-order sections In 1 In 2

out

XOR

?

ve = kd =e 1

?=2

=2



phi e

In 2 out

-1

d = =2 e = 0 time

Figure 3.8: XOR phase detector characteristics been substituted. Such an analog domain representation is valid as long as the phase is sampled at a high rate, i.e., fc  fo [21]. The phase detector is modelled by a subtracter and its gain, kd . The center frequency of the lower loop is xed at fo2 = fc =(4LN) while that of the rst loop varies with the input frequency. The complete 2nd-order loop has a center frequency a fo = fc =(4N). When the loop is locked (e = 0), the center frequency of loop-1 equals the input frequency. After some manipulations, we nd the phase transfer function of the 2nd-order ADPLL to be (3.1) H(s) = o =i = s2 !+1!s +s !+1!!2!2 1 1 where !1 = 2fc =K1N rad=s & !2 = fc =LK2 N rad=s (3.2) Comparing with the standard second-order transfer function, the damping, , and the natural

26

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS Loop - 1 i

e

+

2fc =K1s

kd

-

o

1=N

1=L

1/2

Loop - 2

+ kd

2fc =K2s

1/2

-

1=2LN

Figure 3.9: Frequency domain model of the cascade 2nd-order ADPLL frequency, !n , are given by

r

p 2  = 12 !1 =!2 = LK 2K 1 r 2 p f c !n = !1!2 = N LK K 1 2

(3.3) (3.4)

The pull-in range of the ADPLL, the frequency range over which the loop can eventually acquire lock, is upper-bounded by the hold range and is determined by loop-2. To keep loop-1 locked, the phase error in loop-2 to has to increase to generate more carry or borrow pulses which in turn increase or decrease the output frequency of the corresponding I/D-unit. The following equations give the loop hold range: 1 (f  fc ) fout2;max=min = 4LN c K 2 f 1 c (3.5) fhold =  4N K 2

Parallel 2nd-order ADPLL This is another variant of a 2nd-order loop built from two 1st-order sections [18]. It is similar to the previous one, except that the input to the 1=L counter is connected to the input signal directly. Using a similar equivalent circuit as in gure 18, the phase transfer becomes 1 + !2)s + !1 !2 (3.6) H(s) = o =i = s2 (! + (!1 + !2 )s + !1!2

3.1. IMPLEMENTATION CONSIDERATIONS where

27

!1 = 2fc =K1N rad=s & !2 = fc =LK2 N rad=s

(3.7)

The corresponding natural frequency and damping factor are r

2 fc !n = p!1!2 = N LK1 Kr2

(3.8)

r

K1 2  = (!1 + !2)=2!n = 12 ( 2LK K1 + 2LK2 )

(3.9)

As long as  and !n are the same, this loop will behave in a similar way to the cascaded type. Its drawback is that a second modulation removal unit is needed to block phase modulations from going into the second loop. The eect of including this modulation removal unit on the demodulator performance needs further investigation.

Rate Multiplier Based 2nd-order ADPLL This second-order ADPLL con guration uses a rate multiplier (RM) to generate the clock input to the increment/decrement (I/D) unit of the 1st-order section [11]. Figure 3.10 shows a 2nd-order ADPLL using the accumulating type rate multiplier.

Input

Phase

Detector

Up / Down

K-Counter

Carry

Up / Down Counter

Borrow

Program(P) N-counter 1st-Order Section

Inc/Dec

Over ow

Accumulator (Q) Rate Multiplier

Master Clock (fc )

Figure 3.10: A second-order ADPLL based on a rate multiplier The rate multiplier circuit converts the input frequency (fc ) to an output frequency, fRM = Pfc =Q). For a given division factor Q, the program input P  Q controls the output frequency. The accumulating type RM has a more even pulse distribution compared to conventional RMs. The output spectral purity depends on how evenly the pulses are distributed and degrades as the output frequency decreases. Hence, the design should keep the RM output as close as possible to the input clock frequency. The up-down counter transforms the carry and borrow pulses into the programing value, P. When the loop is not locked, either more carry than borrow or vice versa is applied to the up-down counter driving the rate multiplier output to a frequency which would bring the loop to lock. Once a lock state is reached, equal number of carries and borrows are applied to the up-down counter and their eects cancel each other while averaging in the N-counter. Once again a frequency domain model is used to describe the loop behavior. Since every pulse input to the up-down counter changes the RM output by fc =Q pulses/sec, a combination of the updown counter and the rate multiplier can be considered as an integrator with gain fc =Q. Following this observation, the complete loop model is given by gure 3.11.

28

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS i

+ -

e

kd

2=Ks

1=N

1=2

fc =Qs

o

Figure 3.11: Model for a second-order loop based on the rate multiplier The loop phase transfer function is given by H(s) = o =i c =2NK)s + 4fc2 =2NKQ = s2 (4f + (4fc =2NK)s + 4fc2 =2NKQ The corresponding natural frequency and damping factor are given by p !n = fc 2=NKQ p  = 12 2Q=NK

(3.10) (3.11) (3.12)

3.2 ADPLL-based Design of the MLS Data Demodulator As can be seen in the following section, a hardware ADPLL is suitable for implementing the MLS data demodulator as one of the functional units of the MOVE processor. In this section, we discuss the design (parameterization) of the dierent parts of the demodulator which were implemented on a sea-of-gates IC. Figure 3.12 shows the demodulator functional unit. The mixer converts the 5 MHz IF signal to a level manageable by the ADPLL. The control unit determines the operational status of the ADPLL and the data lter which also contains lock and edge detection mechanisms for data clock synchronization. A serial-to-parallel converter is used to interface the demodulated data to the MOVE bus. Figure 3.13 shows the second functional unit which consists of resetable timers for MLS data (de)validation. The ag register contents are read either during interrupt or on demand.

3.2.1 The Remodulator Loop Figure 3.14 shows an all-digital remodulation loop constructed from an ADPLL by adding three additional modules: (i) an XOR gate for demodulation (ii) a duty cycle sampler which senses the demodulator output when it has stabilized (iii) a remodulator which prevents the modulation from getting into the ADPLL. Based on the discussion in the previous section, the ADPLL design involves determining dierent loop parameters according to the input signal dynamics. The second-order ADPLL has to satisfy the three demodulator requirements: (i) capture range, fhold  25 kHz (ii) loop noise bandwidth, BL  15 kHz and (ii) settling time,  = 1=!n < 832 s. Optimal settling implies  = 0:7 that gives a noise bandwidth BL = 0:53!n. Settling and noise performance require, respectively, !n > 1717 rad/s and !n < 29:5rad/s.

3.2. ADPLL-BASED DESIGN OF THE MLS DATA DEMODULATOR

29

DPSK-Decode

Data Filter ADPLL 2nd-IF Signal (5 MHz)

Mixer

- Carrier Acquis. - Demodulation

[5.23] Clock_2 (68 MHz)

[17]

Frequency Divider

mode

[4]

clk_2

[1] [0.5]

clk_1 clk_3

clk

Edge Detect

Data Clock Synchronize

Lock Detect

reset_1 Lock

Control

Barker Detect

barker reset_2

- Bit Count - Interrupt Gen.

[ ] = MHz

Shift-Register ....

Re-Start

b0

b7

d_clk INTerrupt_1 (15.625 kHz)

To MOVE Socket

Figure 3.12: MLS data demodulation functional unit The large discrepancy in the values of !n can be resolved if we perform acquisition by pull-in instead of lock-in. Pull-in undergoes cycle slipping and takes longer time before acquisition. To speed-up acquisition, the loop-bandwidth can be widened. This is applicable for high signalto-noise ratios [16]. During tracking, the loop bandwidth is reduced to that dictated by noise in uence. A lock-detector is used to determine when to change the bandwidth. The ADPLL center (free-running) frequency, fo , should be chosen as low as possible so that a small phase quantization error is achieved with a lower clock frequency, fc , which has the advantage of reduced power consumption. Other factors which determine the frequency choice include:

 the minimum value of K for proper loop operation, Kmin = 8 according to [27]  the ease with which some of the internal clocks can be generated from the reference clock; especially, the mixer input is easily generated when the reference frequency is set to 68 MHz (see section 3.2.2).

Cascaded and Parallel 2nd-Order ADPLLs Equation 3.5 can be rewritten as fhold = fo =K2 where the center frequency is given by fo = fc =4N. The requirements fhold  25 kHz and K2  8 imply fo  200 kHz. As indicated in the next section, a nominal mixer output (ADPLL input) frequency of 230kHz satis es this condition. The required master clock frequency is obtained from fc = 4Nfo . To keep the phase quantization low enough N should be chosen larger than 10 and for ease of implementation N should be a power of 2. Choosing N = 16, the clock frequency becomes fc = 4N  230 = 14:72 MHz. From equations ( 3.3 & 3.4), we get the relation !1 = 4 2!2 . For  = 0:7, !1  2!2 and p !n  2!2 . p Using eqns. p( 3.5 & 3.2) and the noise bandwidth p requirement, we get !2 = 4
fH =L < !n= 2 = 29500= 2 rad/s. Hence L > 4fhold =(29500= 2) = 4:8. Thus, L = 8 can be used. Using N1 = N = 16 and L = 8, the N-counter of loop-2 is set to N2 = 2LN1 = 256. Using L = 8, and  = 0:7 in eqn. ( 3.3) we get K1 = 64 and !n = 22 krad/s.

30

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS Set_Mode Select

5 4

reset_timer / reset_flag b0 b1

Timer_0 Timer_1

d_clock

Frequency Dividers

[ 0.954 Hz ]

De-Validation

To MOVE Socket

Timers

[ 15.26 Hz]

b14

Timer_14

INTerrupt_2

Figure 3.13: MLS data devalidation functional unit Demodulator Input

To Data Filter

0o

2nd-Order ADPLL

D

Q

90o

Duty cycle Sampler

Remodulator

Figure 3.14: ADPLL-based remodulation loop Due to its structural similarity, the Parallel 2nd-Order ADPLL can be set to the same parameter values, i.e., N1 = 64, K1 = 64, N2 = 256, K2 = 8, and L = 8. Now, the damping factor changes to  = 1:1.

Rate Multiplier-based 2nd-order ADPLL According to eqn. ( 3.12),  = 0:7 requires NK = Q. From eqn. ( 3.11) and the requirement !n < 29:5 krad/s, we get NKQ = 2fc2 =!n2 > 6  105. Thus, we can choose NK = Q = 1024. Using the same center frequency, fo = 230 kHz and N = 16, we get K = 64. Including fhold = 25 kHz, the required master clock frequency becomes fc = 2N  (fo + jfhold j) = 8:16 MHz. We can double N and fc to improve the phase quantization. This implies doubling the values of Q and P to keep  and !n the same. We can also let  = 0:5 and leave Q unchanged. To simplify generation of the master clock from the 68 MHz reference, we can set fc = 17 MHz. To approximate the phase jitter due to quantization in the ADPLL, we can consider the phase to be uniformly distributed in the range [?2=N; +2=N][21]. For N = 32, the phase jitter variance becomes (2  0:1963)2=12 = 0:0127 radians, which is negligible compared to the phase noise that already exists in the incoming signal, 1=2SNR = 0:158 radians [16] for a signal-to-noise ratio of SNR = 5 dB. Since the rate multiplier output frequency, fRMout = fc P=Q, varies from 0 Hz to fc , we need to

3.2. ADPLL-BASED DESIGN OF THE MLS DATA DEMODULATOR

31

limit its operation range according to the expected input frequency, fo  25 kHz. Otherwise, the loop could false lock at integral divisions of the input frequency. By xing the lower limit of the program to Pmin = 768 = "110000000" the rate multiplier operating rage becomes 12.75 MHz to 17 MHz and the corresponding ADPLL output range 199.22 kHz to 265.6 kHz. The two MSBs are hardwired while the lower 7 bits of P are checked for "all zero" and "all one" cases to disable down-count (borrow) and up-count (carry) pulses respectively.

The Increment-Decrement Unit Both loops in the cascaded (parallel) structures and the 1st-order section of the rate multiplier based design require an increment-decrement unit to modify the input clock frequency according to carry and borrow pulses. In this design the circuit described in [24] has been used.

Which ADPLL structure to Choose? Choosing one of the three 2nd-order structures for nal implementationdepends on the performanceto-cost relationship. The performance mainly refers to the level of output jitter due to phase quantization. This has to be made as low as possible for a better overall demodulator performance. The rate multiplier approach has been chosen for the demodulator design based on the following observations:

 for roughly the same master clock frequencies the rate multiplier based approach yields half

the phase jitter of the other two  the phase jitter characteristics of the cascaded and parallel types ADPLLs is degraded by the presence of the L-counter (see simulation results in the next chapter)  the hardware costs of the three approaches are similar as can be seen from the counter lengths.

3.2.2 Mixer Design Using the 5 MHz 2nd-IF signal as an ADPLL input would require a very high master clock frequency, at least 2  N1  fIF = 160 MHz, to provide sucient phase quantization. From the hold range requirement of the cascaded ADPLL, the IF frequency can be reduced to 200 kHz. A digital mixer using a simple D-type ip= op is shown in Figure 3.15. The sampling clock frequency is set to fs = f2ndIF  f3rdIF , where the 3rd-IF frequency is equal to the center frequency of the ADPLL, fo . The sampling clock frequency should be chosen to simplify its generation from the 68 MHz clock, i.e., if possible, by dividing with a power of 2; otherwise with an integer and no fractions. Candidate sampling frequencies are fs = 68=13 = 5:2308 MHz and fs = 68=14 = 4:8751 MHz with respective 3rd-IF frequencies of 230.8 kHz and 142.86 kHz. From hold range requirements of the cascaded and parallel type ADPLLs, the rst choice is appropriate. For the rate multiplier type ADPLL, both choices are applicable as the loop can lock over a wide range of frequencies. To allow comparison of the dierent ADPLL structures the rst frequency has been chosen. Due to discrete sampling instants, the zero-crossings of the mixer output contain extra phase jitter relative to an ideal square wave of frequency f3rdIF = fs ? f2ndIF . The worst case timing error occurs when the sample is taken just before the actual zero-crossing, in which case the "0-1" or "1-0" transition is delayed by Ts = 1=fs . For f3rdIF = 230kHz, the corresponding phase error is e;max = 2f3rdIF Ts = 0:2763 radians.

32

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS 2nd-IF signal (f2dnIF = 5 MHz)

D

Q

3rd-IF signal (f3rdIF )

D-FF Sampling Clock (fs = f2dnIF + f3rdIF ) Figure 3.15: Digital mixer using a D-type ip- op The phase jitter due to discrete sampling instants can be considered uniformly distributed in the range [0,e;max] [21], yielding a phase jitter variance of 2e;max =12 = 0:0064. This is negligible compared to the phase noise that already exists in the incoming signal, 1=2SNR = 0:158 radians. Here, the lowest signal-to-noise ratio, SNR = 5 dB is assumed.

3.2.3 Data Filter Design The output of the demodulator, i.e., the product of the 3rd-IF signal and one of the ADPLL outputs, contains phase noise due to additive atmospheric noise and ADPLL jitter. This phase noise has to be ltered before a decision is made about the received bit. Since the demodulator output contains information in the form of duty-cycle, the data lter should averages (integrates) the duty-cycle over a certain duration. Figure 3.16 shows an up/down counter used as duty cycle averager. The counter is built by cascading similar cells (bit-slices) whose number is determined by the integration interval, Tinteg , and the counting clock frequency, fcc . Since the data lter is used in three modes: (i) acquisition(AQ) (ii) data clock synchronization(SY) and (iii) Tracking(TR), its parameters have to be changed accordingly. up/down counter demodulated data

mode (U/D)

0 0

cell0 Q M M Ci Co S S C C Uo Ui Lo Li

cell1 Q M M Ci Co S S C C Uo Ui Lo Li

. . . . . .

. . . . . .

. . . . . .

AND U2

S0 = F R S1 = R S0 = F R

U1

cell4 Q M M Ci Co S S C C Uo Ui Lo Li

1 1

AND L2

L1

cell5 Q M M Ci Co S S C C Uo Ui Lo Li

... ... ... ... ... ...

cell7 Q M M Ci Co S S C C Uo Ui Lo Li

1 1

Lock = Uo(5)+Lo(5) Data = (AQ + TR) Q(7) + SY Q(4) Trigg = SY edge(Q(4))

lock_detect filtered data trigger

Fup = [(AQ+TR) U1 + SY U2] mode

F

3

OR

{AQ,SY,TR}

Fdn = [(AQ+TR) L1 + SY L2] mode (F = freez) 2 Clk = AQ

{clock_1, clock_2}

clock_1 + (SY + TR) clock_2

Figure 3.16: Block diagram of the data lter using an up/down counter with a control logic

3.2. ADPLL-BASED DESIGN OF THE MLS DATA DEMODULATOR

33

The counter cells generate upper limit (U) and lower limit (L) signals which are used to disable, respectively, up-counting and down-counting, via the freeze (F) signal. Figure 3.17 shows the interior of the counter cells [14]. Q mode

U/D

mode

carry_in

carry_out 3

{S0,S1,S2}

D = SUM S0 + S1 ?? + S2 Q Q

D

Q

Clk

{S0,S1,S2}

clock

clock U_out

L1_out = L1_in L2_out = L2_in

L_out

Q Q

U_in (upper limit) L_in (lower limit)

Filter Cell (?? = 0 for all cells but the MSB)

Figure 3.17: Interior of the lter cells

Filtering During Acquisition The demodulator output, being a product of the input IF signal and the ADPLL output, contains both sum and dierence frequency terms. Thus, a measure of the lock status can be obtained by ltering the demodulator output. The lter integration interval should be chosen in such a way that lock indication is raised when the frequency dierence is very close to or within the the tracking mode lock-in range (
!L) of the p ADPLL. For an XOR type phase detector,
!L  !n . In the tracking mode, we have !n = fc 2=(NKQ) = 16:6 krad/s (where N = 32; K = 64; Q = 1024) and  = 0:5. The corresponding lock-in range becomes
!L  26:2 krad/s or
fL  4:2 kHz. An 8-bit up/down counter with a clock of fcc1 = 1 MHz has been selected for lock detection ltering. The 1 MHz clock provides at least 3 samples per period of the input IF signal, f3rdIF 2 [230 ? 25; 230+25]kHz, which is enough for majority decision of the duty-cycle of the demodulated signal. The counter is rst reset to its middle value, 128 = "10000000". Depending on whether the ADPLL is locked in-phase or out-of-phase to the incoming carrier, the up/down counter eventually settles at a value above or below 128. Two threshold levels have been de ned at THhigh = 255 ? 31 = "11100000" and THlow = 31 = 00011111 allowing lock detection by sensing the 3 MSBs. Using the above thresholds, the lowest integration time is Tinteg = (128 ? 31)Tcc1 = 97s. This means the thresholds will be passed if the frequency dierence equals 1=(2Tinteg) = 5:2 kHz. Actually, noise results in some integration loss and leads to a longer integration interval before the thresholds are passed. This means, up on lock detection the frequency dierence between the ADPLL input and output signals is close to the lock-in limit
fL  4:2 kHz for which acquisition is very fast, tsettle  1=!n = 60s.

Filtering During Tracking For a binary data transmission with a bit rate of fb , the power spectral density has the form of [sin(x)=x]2 with 90% of the power contained in 2fb band and the -3 dB point is at 0:5fb [7]. For the present case fb = 15:625 kHz and a lowpass lter of 8 kHz gives a near optimal result. The lter integration time is now set to Tinteg = Tb = 1=fb = 64s, which is achieved by an 8-bit counter running at a fcc2 = 4 MHz clock. The up/down counter keeps on integrating without

34

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS

dumping, but with upper and lower limit detection to prevent over ow or under ow when identical bits arrive consequently. The output bit is obtained by sampling the MSB of the counter with the data clock at times when the integrator has maximum or minimum values.

Filtering During Clock Synchronization A data clock synchronized to MLS bit stream is required for optimal demodulator operation, i.e., to sample the data lter output at its peak value. The MLS data format provides a 5-bit Barker frame synchronization interval during which data clock synchronization has to be completed. Such a short time interval implies the used of open-loop clock synchronization techniques as opposed to closed-loop ones [16]. Here speed is exchanged for synchronization accuracy. In open-loop synchronization the bit transitions (0 ! 1 or 1 ! 0) are used to trigger a free-running data clock. Since the noisy demodulator output contains unwanted transitions as well, the edge detection should be done after ltering. The lter should be wide enough to reduce the edge detection delay from the actual transitions. As the lter bandwidth decreases, the integration interval increases and many unwanted transitions are accounted for in the counter value. The time at which the counter passes the middle value (the edge detection moment) becomes jittery about the ideal instant. The fewer noise-caused transitions in the counter value, the lower the timing uncertainty in the edge detection process. This implies the use of a wide band lter. By clocking the up/down counter at fcc2 = 4 MHz and limiting the counting range to [0; 31], an integration time of Tinteg = 32=fcc2 = 8s achieved. This corresponds to a bandwidth of about 1=2Tinteg = 62:5 kHz. When the counter crosses the middle value, i.e., 16, a trigger pulse is sent to the data clock generator. The fth bit of the counter is used as an output data for Barker code detection.

3.2.4 The Data Clock Generator Figure 3.18 shows the data clock generator block diagram. The input clock frequency is generated from the 68 MHz reference clock by dividing with 64, fcc1 = 68=64 = 1:0625 MHz. The division factor in the data clock generator is fcc1 =fb = 1:0625e6=15:625e3 = 68, which is obtained by using a 7-bit down counter that is reset to 67 ="1000011" every time it reaches 0. Clk D

Q

Register

Clock (1.0625 MHz) 7

D

Data Clock (15.625 kHz)

Q 7

Trigger

D = 62 = 67 = Q-1

if Tr if Tr Tc if Tr Tc

Tc = (Q == 0)

Tc

Figure 3.18: Data clock generator using a triggerable down counter The data clock is synchronized to the incoming bit stream with the help of the trigger input from the data lter discussed in the previous section. The trigger signal is generated by detecting the

3.2. ADPLL-BASED DESIGN OF THE MLS DATA DEMODULATOR

35

edge of the lter output using the same 1.0625 MHz clock. Upon triggering, the counter can be reset to 67 as usual. However, as the lter output makes "1 ! 0" or "0 ! 1" transition at least 4s later than the actual bit transition and the edge detection delays the moment by extra 2s, a correction can be made by resetting the counter to a value lower than 67. For instance, by resetting the counter to 62 = "0111110" upon triggering, the next clock tick comes 62=1:0625  58:4s latter. The delay correction amounts to 64 ? 58:4 = 5:6s.

3.2.5 The DPSK Decoder and Barker Code Detector Having determined the data clock, the DPSK decoding is done by comparing the current and previous bits from the data lter. The DPSK decoded data is rst used for Barker code ("11101") detection and then sent to the data processing software. Figure 3.19 shows the hardware for these tasks. DPSK Decoder

filtered_data

D

Q

decoded_data

XOR

Shift Register

Clk

Q

Q

Q

Q

Q

data_clock AND

barker_detect

Barker Code Detector

Figure 3.19: DPSK decoding and Barker code detection unit

3.2.6 The Control Unit Since the ADPLL and data lter parameters have to be changed according to the receiver state, i.e, Acquisition (AQ), Synchronization (SY) and demodulation (DE), a control unit is required to perform the state transition. Figure 3.20 shows the block and state diagrams of the controller. The state transitions are made according to three inputs, re-start, lock detect and barker detect. The restart command is issued by the receiver software and its 0 ! 1 transition generates the Reset signal which is also used to set the up/down counter of the data lter to its mid-value at the start of acquisition. The edge detection is done using a 0:5312 MHz clock which keeps the Reset command active for about 2s, which is wide enough for resetting the data lter running at 1:0625 MHz clock.

3.2.7 The Frequency Divider Figure 3.21 shows the frequency divider which generates the clocks that drive dierent sections of the demodulator. A synchronous divide-by-13 counter gives the 5.230 MHz clock for the samplingtype mixer. The remaining clocks are generated by cascading ripple divide-by-4 sections.

3.2.8 The Data Validation Functional Unit As shown in gure 3.13, the hardware support for MLS data (de)validation process consists of timers assigned for each of the 15 MLS functions. Each timer is reset to its maximum when a correct MLS function is received that is consistent with previous values. The correctness and

36

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS clock_2 (4.25 MHz)

Register D

clock_3 (0.5312 MHz) Re-Start

Reset

Edge Detect

Q

2

2

Next State

AQ (Acquisition) SY (Synchnchronization) TR (Tracking)

Decode

lock_detect barker_detect

Reset

[x0x] [xxx] Idle [00]

[0xx]

[0x0] [01x]

[0x1]

AQ [01]

TR [11]

SY [10] [1xx]

[1xx] Input = [Reset, lock_detect, barker_detect]

Figure 3.20: Receiver control unit and its state graph Divide-by-13 clock_in 68 MHz

Register D

4

Q

4 Tc = (Q == 0)

D = 12 if Tc = Q-1 if Tc

1/4

5.230 MHz

1/4

1/4

1/2

0.5312 MHz 1.0625 MHz 4.25 MHz 17 MHz

Figure 3.21: Frequency Divider consistency tests are done in software. If the maximum time is elapsed before another usable data is received, the associated ag is raised. Figure 3.22 shows three types of timer cells used in validation unit design. Each timer has two clock inputs: m clock to which the Preset command is synchronized, and c clock used for down counting. When the registers values are zero the Flag is set and stays so until reset by the software via the Preset command. Type-3 cell has an Azimuth command which is used for selecting the Back Azimuth mode. The validation interval is expressed as [(Qmax ? 1)=fcc; Qmax =fcc ], where Qmax is the maximum preset value and fcc is the counting clock frequency. This gives (1.89 to 2.75) sec for cell 2, (1.89 to 2.75) sec or (6.42 to 7.34) sec for cell 3, and (1.18 to 1.31) sec for cell 4. The cells satisfy the MLS speci cations of 1, 3, 3.6, and 9 sec validation times for dierent data functions. The cell assignment and the counting clock generator are shown in gure 3.23. The preset values are generated by a decoder which selects the addressed validation unit.

3.3. SEA-OF-GATES LAYOUT

37 cell_4

cell_2 1 M U 0 X

m_clk c_clk (1.0172 Hz)

Preset

Register D

2

Q

c_clk (7.629 Hz)

2 F = (Q == 0)

D=3

if P = Q-1 if P F = Q if P F

P

1 M U 0 X

m_clk

Preset

F

Flag

Register D

P

if P = Q-1 if P F = Q if P F

4

Q

D = 10

4 F = (Q == 0)

F

Flag

cell_3 m_clk

1 M U 0 X

c_clk (1.0172 Hz)

Preset Azimuth

Register D

P A

D=7

=3

3

if P A if P A

Q

3 F = (Q == 0)

F

= Q-1 if P F =Q

Flag

if P F

Figure 3.22: Cells for the data validation unit

3.2.9 Interfacing to the MOVE Processor The design is complete when the demodulation and validation functional units (FUs) are properly interfaced to the MOVE-processor. The actual interface is done via the MOVE-sockets which are not discussed here. We discuss the way how the data from the functional units is delivered to the sockets. Since data could arrive at any moment, the MOVE processor should always be ready to receive it. This could be done in two ways: (i) by polling (periodically reading the input ports) or (ii) by means of interrupts. In this design the second approach has been adopted since it saves time wasted in repeated polling, especially if the interrupt rate is low. Actually, the interrupt terminal can be considered as a data-ready status signal to be polled by the microprocessor if wasted time is not critical and interrupts are to be avoided. Once reset by the software, the demodulator FU starts to deliver data after a successful Barker code has been detected. The data bits arrive at 15.625 kHz. By converting the serial bits to 8-bits parallel the interrupt rate is reduced to less than 2 kHz. The choice of 8-bits has to do with the MLS data format in which the rst 7-bits following the Barker code identify the received function. Depending on the function type the receiver might be required to receive angle information right away. The data validation functional unit can be interfaced without an interrupt. The MLS software can be made to read the ag registers when ever it wants to determine the validity of the data.

3.3 Sea-of-Gates Layout The demodulator and devalidation functional units described in the previous section were laid out on a sea-of-gates sh-bone using the OCEAN layout tool [17]. The circuits were extracted and simulated to verify their operation. The layout image is shown in gure 3.24 also consists of extra hardware for testing purposes only, such as multiplexers to connect internal terminals to the output. The total hardware cost amounts to 12% of the sea-of-gates chip, which is 180000 transistors in total.

38

CHAPTER 3. DESIGN AND IMPLEMENTATION OF MLS FUNCTIONAL UNITS

P1

cell_2

Flag_1 (for Baic Data Word 1)

cell_4 cell_2 cell_3 D E C O D E R

S0 S1 S2 S3

cell_3 cell_3

Flag_6

(for Baic Data Word 6)

cell_2

Flag_7

(for Auxiliary Data Word 1)

cell_2 cell_3 P10

cell_3

Flag_10 (for Auxiliary Data Word 4)

Azimuth (A) m_clock data_clock (15.625 kHz)

1/2048

1/15

c_clk1 7.63 Hz

1/7

c_clk2 1.09 Hz

Figure 3.23: Hardware for MLS data validation process

Figure 3.24: Sea-of-gates layout of the MLS data demodulator

Chapter 4

Simulation Results The ideas presented in the previous chapters were veri ed with the help of functional simulations. The dierent blocks were modelled as appropriate and coded in "C". In this section, we present the simulation setup and the results.

4.1 The Sampling-type Mixer The phase quantization in the mixer manifests itself as jitter in the zero crossing of the output signal. In simulation, the zero-crossing timing error can be easily measured once the output and sampling periods are known. The simulation results are shown in gure 4.1. The phase quantization shows some periodicity that varies with the output frequency. Since the ADPLL that follows the mixer is locked at a relatively high frequency, the "dc" component has no in uence. The "ac" component, whose power is indicated by the variance, is very weak compared to the phase noise present in the actual input signal as discussed in the previous chapter.

4.2 ADPLL Simulation Acquisition and and jitter characteristics are two ADPLL features which are important in the demodulator performance. These characteristics depend on the ADPLL parameters which are summarized in table 4.1. The master clock frequency has been xed to fc = 17 MHz which results in a center frequency of fo = 230 kHz for the rate multiplier ADPLL and fo = 265 kHz for the cascaded type. Table 4.1: ADPLL parameters for simulation K1 K2 L Q fo fc  [kHz] [MHz] 256 8 8 8 265 17 1 16 0.71 32 0.5 64 0.35 8 - - 1024 230 17 1.41 16 1 32 0.71 64 0.5

Type

N1 N2

Cascaded

16

RM-based 32

39

!n [krad/s] 66.4 47 33.2 23.5 47 33.2 23.5 16.6

BL [kHz] 41.2 24.9 16.6 12.5 35.3 20.8 12.5 8.3

CHAPTER 4. SIMULATION RESULTS

40 Mixer phase quantization: fs = 68MHz/13, fo = 215 kHz

Mixer phase quantization: fs = 68MHz/13, fo = 230 kHz

0.3

0.3 mean = 0.1385 mean = 0.1306 var

0.25

0.25

0.2

0.2

0.15

0.15

0.1

0.1

0.05

0.05

0 0

0.2

0.4

0.6

= 0.0063

= 0.0055

phase quant. [rad]

phase quant. [rad]

var

0.8

time [s]

0 0

1

0.2

0.4

0.6 time [s]

−4

x 10

0.8

1 −4

x 10

Mixer phase quantization: fs = 68MHz/13, fo = 255 kHz 0

−0.05

phase quant. [rad]

−0.1

−0.15

−0.2

−0.25 mean = −0.1277 var −0.3 0

0.2

0.4

0.6 time [s]

= 0.0055 0.8

1 −4

x 10

Figure 4.1: Simulation of phase quantization in a sampling type mixer The simulation setup to study the acquisition and jitter characteristics and the bit error rate performance of the demodulator is shown in gure 4.2. The "C" code of this simulation setup is given in Appendix A. The phase measurement is done by reading the content of the N-counter at the 0 ! 1 transition of the noise free input. To account for the AWGN noise, a bandpass noise is generated by transforming two independent lowpass components.

4.2.1 Acquisition Performance Figures 4.3 and 4.4 show the acquisition process of cascaded and rate-multiplier based 2nd-order ADPLLs in the presence of noise. In the actual operation, the input signal frequency doesn't change very much between two transmissions since the major cause is Doppler shift. In the absence of MLS signal during this period, the ADPLL can drift away from its locked state because of noise. To take this into account, the (re-)acquisition simulation was conducted for the worst case situation in which the ADPLL is subjected to the maximum possible frequency step. According to table 4.1, the cascaded ADPLL can under go a 58 kHz swing from fo ?fhold = 232 kHz to fo +
fin;max = 290 kHz, where fo = 265 kHz, fhold = fo =K2 = 33:125 kHz and
fin;max = 25 kHz. Similarly the rate multiplier based ADPLL can under go a 66 kHz swing from fin = 200 kHz to fin = 266 kHz. For the cascaded ADPLL ( gure 4.3), the simulation was conducted by changing the input frequency changes from fin = 233 kHz to fin = 291 kHz at time = 2 ms. The lock detection 0

1

4.2. ADPLL SIMULATION Random Sequence Generator

41

Bit Error Count

b[nTb]

s[mTc ]

Hard Limiter Modulator

Phase Meter

n1 [mTc ]

N-count

LPF (75 kHz)

Hard Limiter

!i mTc )

cos(

n2 [mTc ]

ADPLL-based Remod. Loop Data Filter

!i mTc )

LPF (75 kHz)

sin(

Bandpass Noise Generator

data bits

Master Clock [fc ]

Figure 4.2: Simulation set-up for studying ADPLL acquisition and jitter changes K to 64 at time = 2:638 ms for the 1st plot and at time = 2:932 ms for the 2nd plot. For the rate multiplier based ADPLL ( gure 4.4), the input frequency changes from fin = 200 kHz to fin = 266 kHz at time = 2 ms. The lock detection changes K to 64 at time = 2:346 ms for the 1st plot and at time = 3:238 ms for the 2nd plot. 0

1

6

6

5

K=8

5

4 output phase[rad]

output phase[rad]

4

3

3

2

2

1

1

0 0

K = 16

0.5

1

1.5

2

2.5 time[ms]

3

3.5

4

4.5

5

0 0

0.5

1

1.5

2

2.5 time[ms]

3

3.5

4

4.5

5

Figure 4.3: Acquisition behavior of a Cascaded 2nd-order ADPLL The above simulation results indicate that the MLS requirement of 832s acquisition time is met only for K = 8. It can also be seen that the transition from wide loop bandwidth (K = 8) to narrow loop bandwidth (K = 64) is accomplished without any transients.

4.2.2 Jitter in the Tracking mode To compare the output phase jitter of the two 2nd-order ADPLL structures, the noise input was set to zero and the loop bandwidth to the tracking mode (K = 64). The simulation results are

CHAPTER 4. SIMULATION RESULTS

42 7

7

6

K=8

6

5 output phase[rad]

output phase[rad]

5

4

3

4

3

2

2

1

1

0 0

K = 16

0.5

1

1.5

2

2.5 time[ms]

3

3.5

4

4.5

0 0

5

0.5

1

1.5

2

2.5 time[ms]

3

3.5

4

4.5

5

Figure 4.4: Acquisition behavior of a rate multiplier based 2nd-order ADPLL shown in gure 4.5. It can be seen that rate multiplier based design gives a relatively lower phase jitter for the similar loop parameters and operation frequencies. 3.6

5.8 K = 64 5.6

3.5

5.4

3.4 3.3 output phase[rad]

output phase[rad]

5.2

K = 64

5 4.8 4.6

3.2 3.1 3

4.4 2.9

4.2

2.8

4

2.7

3.8 1

1.5

2 time[ms]

2.5

3

1

1.5

2

2.5

3

3.5

time[ms]

Figure 4.5: Jitter characteristics in the tracking mode: cascaded ADPLL at fin = 265 kHz and rate multiplier based ADPLL at fin = 215 kHz.

4.3 The Data Filter and Bit Error Rate As described in the previous chapter, the data lter is used in three modes: acquisition, clock synchronization and tracking. Figure 4.6 shows the lter (integrator) content for dierent operation modes. The input frequency is switched from 215 kHz to 255 kHz at t = 1:5 ms. For both input frequencies the lower threshold (31) is passed during acquisition and the ADPLL is locked in-phase to the input signal. In the synchronization mode, the lter integration ranges from 0 to 31. For the rst ten data bits (3 to 3.64 ms) trigger pulses are generated to synchronize the local data clock. In the actual operation, only 5 data bits are expected. If these 5 bits satisfy Barker code detection, synchronization is complete and the lter is switched to the tracking mode, i.e., the counter operates from 0 to 256 to provide better noise ltering. The received bits are determined by sampling the MSB of the data lter with the local data clock. Since the data clock is synchronized to the incoming bit stream, the sampling takes place when the integrator reaches its peak. Because of noise, the peak can take any value within the counter range and result in occasional bit errors. A bit error rate (BER) simulation was conducted using

4.3. THE DATA FILTER AND BIT ERROR RATE

43

integrator content

300 250 200 150 100 50 0 0

syn

acq

syn

track

1

2

3 time[ms]

4

5

6

1

2

3

4

5

6

6 trig 5 4 lock 3 bit_out

2 1

bit_gen 0 0

Figure 4.6: Data lter (integrator) operation in dierent receiver modes the same data clock as the transmitter, i.e., assuming zero local clock timing error. Out of ten simulation runs, each with 10,000 bits and dierent noise seeds, 4 errors were detected for the DPSK decoded signal; hence, BER = 4  10?5, which is less than the MLS speci cation.

Chapter 5

Conclusion The design, simulation, and implementation of an all-digital data demodulation and validation hardware has been presented. The design is used in the MLS(Microwave Landing System) section of the GOLLUM integrated navigation receiver. A prototype of the design has been made on a sea-of-gates image and is ready for testing. The rst step in the design was to identify and compare dierent implementation alternatives: analog vs. digital and hardware vs. software. The digital approach has been chosen for two reasons: (i) its suitability for integration as an application-speci c functional unit of the MOVE processor and (ii) it avoids problems such as component tolerance and sensitivity to supply voltage variation. Next, the computational complexity of the software approach was determined with the help of the MOVE simulation environment. The simulation results show that a dedicated MOVE processor is needed for implementing MLS signal processing functions alone. This is in contradiction to the objectives of GOLLUM, in which a single processor is supposed to be shared among dierent applications. The chosen digital hardware approach makes use of a second-order all-digital phase-locked loop (ADPLL). Three 2nd-order loop structures were compared: the cascaded loop, the parallel loop, and the rate multiplier based loop. The third type was chosen for its better jitter performance at small extra hardware cost. To further relax the load of the MOVE processor, data ltering, clock synchronization, DPSK decoding and frame synchronization are also implemented in hardware. A hardware approach is also adopted for the implementation of data validation timers. To reduce the frequency of interrupts, the serially received bits are parallelized before interfacing to the MOVE bus. The realized circuit costs about 12% of the sea-of-gates chip, which has 180,00 transistors in total. There is enough space left for implementing the MOVE processor together with FUs of the other sub-systems. As indicated in [6], a high speed(25 MHz), time-multiplexed GPS correlation engine takes about 16% of the chip. Thus, 72% of the chip is left for LORAN-C FUs and the MOVE general-purpose FUs, which makes the GOLLUM concept a reality.

45

Bibliography [1] Loran-C user handbook. Technical Report COMDPTPUB P16562.6, US Coast Guard, 1992. [2] E. Aardoom and A. Nieuwland. A Single Chip Integrated Navigation System. UK Journal of Navigation, 1993. [3] Bendix General Aviation Avionics Division. Maintenance Manual ML-201A MLS, 1984. [4] R.E. Best. Phase-locked loops: theory, design and applications. McGraw Hill Inc., 1993. [5] Last D. Bishop J. The Last Omega Receiver. Proc. of the 21st INA annual meeting, 1996. [6] C. Bruma. A Four channel GPS correlation Engine. Technical report, Delft University of Technology, Dept. EE/CAS, September 1994. [7] A.B. Carlson. Communication Systems. McGraw-Hill Inc., 1986. [8] H. Corporaal and J. Mulder. MOVE: A frame-work for high-performance processor design. Supercomputing-91, November 1991. [9] M. de Bruine. Het Verwerken van het Logaritmisch Gedetecteerde Scanningsignaal in een MLS Ontvanger. Master's thesis, Delft University of Technology, Circuits & Systems group, 1993. [10] A.C. de Graaf and van Genderen A.J. SLS:switch-level simulator user's mannual. Delft University of Technology, 1992. [11] R.C. den Dulk. An Approach to Systematic PLL Design. PhD thesis, Delft University of Technology, Circuits & Systems group, 1989. [12] R.L. Didday and W.C. Lindsey. Subcarrier Tracking Methods and Communication System Design. IEEE Trans. on Communications, 16(4), August 1968. [13] M.B. El-Arini and M.J. Zeltser. Analysis of the Integrity of MLS Data Functions. IEEE Trans. on Aerospace and Electronic Systems, (4), July 1987. [14] K. Eshraghian and N.H.E Weste. Principles of CMOS VLSI Design. Addiso-Wesley Pub. Company, 1993. [15] J.L. De Gouy et al. GaAs ICs for 5 GHz Microwave Landing System front-end. IEEE MMMC Symposium, 1992. [16] F.M. Gardner. Phase Lock Techniques. John Wiley and Sons, New York, 2nd edition, 1979. [17] P. Groeneveld and P. Stravers. OCEAN: The Sea-of-Gates Design System. On-line Users Manual. Delft University of Technology, Circuits & Systems group, 1993. [18] T. et al Iritani. Linear DPLLs using integrators in a pulse frequency-modulation system. IEE PROC., 129(5), October 1982. [19] S. Kockzo and A.W. Clark. A DSP-based Microwave Landing System Post-IF Processor. IEEE DASC, 1991. [20] W.C. Lindsey. Performance of Phase Coherent Receivers Preceded by Bandpass Limiters. IEEE Trans. on Communications, 16(2), April 1968. [21] W.C. Lindsey and C.M. Chie. A Survey of Digital Phase Locked Loops. Proc. of the IEEE, 69(4), April 1981. [22] H. Meyr and G. Aschied. Synchronization in Digital Communications. John Wiley and Sons, 1990. [23] E. Otto. MLS Data Demodulatie Analyse. Master's thesis, Delft University of Technology, Circuits & Systems group, 1989.

47

48

BIBLIOGRAPHY

[24] Philips Components. Philips data handbook, integrated circuits, 1986. [25] J.G. Proakis. Digital Communications. McGraw Hill Inc., 2nd edition, 1989. [26] H.W. Redlien and R.J. Kelly. MLS: The New International Standard. Advances in Electronics and Electron Physics, 57, 1981. [27] W.B. Rosinc. All-digital phase-locked loops using the 74HC/HCT297 IC, designer's guide. Philips Components, 1989. [28] D.P. Ruys. De Nauwkeurigheid van de Split Gate Processor voor het MLS. Master's thesis, Delft University of Technology, Circuits & Systems group, 1990. [29] M. van Meel. De Simulatie en Meting van een Delay-line DPSK Demodulator. Master's thesis, Delft University of Technology, Circuits & Systems group, 1992. [30] P.J. Vianen. Dierential-GPS Corrections for Multi-mode Integrated Approach Syste (MIAS). Technical Report Report A-486, Delft University of Technology, Dept. EE/TVS, August 1993. [31] W. Zwart. Een Remodulatielus voor DPSK Demodulatie. Technical report, Delft University of Technology, Circuits & Systems group, 1994.

Appendix A

C-code Description of the MLS Data Demodulator /*------------------------------------------------------*/ /*File : "mls_demodlation.c" */ /*Task : - builds a data demodulator using */ /* cascaded or rate-multiplier based */ /* 2nd-order ADPLL */ /* - simulates the demodulator at different */ /* input frequencies */ /*e.g : - "mls_demod 1 215 40 1.5 3 6 0" to see */ /* data filter and ADPLL operation */ /* - "mls_demod 1 215 40 1.5 3 7e3 1" to test */ /* about 100,000 bits for testing the BER */ /* performance */ /* (note: the file ouptut is disabled) */ /* - see below for input description */ /* */ /*Author: Anteneh Alemu Abbo */ /*UpDate : 15-10-96 */ /*------------------------------------------------------*/ #include , d_clock_old #include #include #include #define #define #define #define #define

frand() ((double) rand()/(RAND_MAX+1)) pi 3.1415926536 pi_2 6.2831853072 freq_mixer_clk 5.23e6 Nsync 10 /*number of synchronization (Barker) bits*/

#include #include #include #include #include #include #include

"signal_generator.h" "digital_mixer.h" "remodulator0.h" "remodulator1.h" "clock_generator.h" "data_filter.h" "measurement.h"

d_clock, s_clock2_old, s_clock1_old, d_clock_old; int pll_type, write_disable; float freq_signal, freq_signal2, freq_step, freq_IF_1, sum_sqr_noise, pll_phase, mixer_phase, phi_in_noise; double time, modul_start, freq_step_moment, t_max;

/*--------------------- User Inputs -----------------*/ if(argc < 9) { printf("PLEASE ENTER ARGUMENTS:\n"); printf("PLL Type(Casc. = 0, Rate Mult. based = 1)\n"); printf("Input signal frequency [kHz]\n"); printf("frequency step [kHz]\n"); printf("freq. step moment [ms]\n"); printf("start of modulation [ms]\n"); printf("simulation interval [ms]\n"); printf("noise seed\n"); printf("disable file output [Y=1]\n"); exit(0); } pll_type = atoi(argv[1]); freq_signal = atof(argv[2])* 1000; freq_step = atof(argv[3])* 1000; freq_signal2 = freq_signal + freq_step; freq_step_moment = atof(argv[4])* 1e-3; modul_start = atof(argv[5])* 1e-3; t_max = atof(argv[6])* 1e-3; seed = atoi(argv[7]); write_disable = atoi(argv[7]); /*new random number seed*/ srand(seed); /*start UNIX system timer*/ clock();

FILE *file_remod, *file_phase, *file_filter;

/*open output file_remod = file_phase = file_filter =

main(int argc, char* argv[]) { int pll_input, pll_input_1, pll_input_2, input_type, clean_input, clean_input_old, pll_out_q, bit_gen, demod_data, out_data, data_filt_state, N_count, num_bits, err_count, num_samples; int type = 0, lock = 0, reset = 0, sync = 0, trig = 0; int m_clock, s_clock0, s_clock1, s_clock2,

files*/ fopen("file_remod", "w"); fopen("file_phase", "w"); fopen("file_filter", "w");

/*------------------Main Loop-------------------------*/ while(time freq_step_moment) freq_signal = freq_signal2; if(time == 0 || (time >= freq_step_moment-1e-6 && time modul_start + Nsync*64e-6) { sync = 1; num_bits = 0; } } else { type = 2; reset = 0; DataFilter(time, type, reset, demod_data, s_clock1, s_clock2, bit_gen, d_clock, &out_data, &data_filt_state, &num_bits, &err_count); } MeasurePhaseShift(0, clean_input, pll_out_q, time, freq_signal, &pll_phase); MeasurePhaseShift(1, clean_input, pll_input_1, time, freq_signal, &mixer_phase);

} /*--------------------------------------------------*/ /*Header File: "signal_gen.h" */ /*Task : generates */ /* - a 5 MHz(+- Fsig kHz) IF siignal */ /* for mixing */ /* - a clean signal (Fsig kHz) for */ /* phase jitter */ /* measurement */ /*Date : 15-10-96 */ /*--------------------------------------------------*/ #define Asig 1 /*signal amplitude*/ #define variance_1 17.91e-0 /*for SNR=5dB at fs = 17 MHz & BW = 150 kHz*/ #define variance_2 5.5e-0 /*for SNR=5dB at fs = 5.23 MHz & BW = 150 kHz*/ void NoiseSource(int, float*, float*);

51 void LowPassFilter(int, float*, float*); void BitGenerate(double time, double modul_start, int d_clock, int *bit_gen, int *num_bits); void ModulateCarrier(int type, float freq_IF, double time, int *bit_gen, int *signal, int *num_samples, float *sum_sqr_noise, float *phi_in_noise); void CleanSignal(float freq_sig, double time, int *signal_clean); void SignalGenerator( /*inputs*/ int type, float freq_sig, float freq_IF, double time, double modul_start, int m_clock, int s_clock, int d_clock, /*outputs*/ int *signal_0, int *signal_1, int *signal_clean, int *bit_gen, int *num_bits, int *num_samples, float *sum_sqr_noise, float *phi_in_noise ) { static int m_clock_old, s_clock_old, d_clock_old; BitGenerate(time, modul_start, d_clock, bit_gen); if(type && s_clock_old && !s_clock) ModulateCarrier(type, freq_IF, time, bit_gen, signal_0, num_samples, sum_sqr_noise, phi_in_noise); if(!type && m_clock_old && m_clock) ModulateCarrier(type, freq_sig, time, bit_gen, signal_1, num_samples, sum_sqr_noise, phi_in_noise); CleanSignal(freq_sig, time, signal_clean);

NoiseSource(type, &n1, &n2); LowPassFilter(type, &n1, &n2); *sum_sqr_noise = *sum_sqr_noise + n1*n1; (*num_samples)++; s = s + n1*cos(phi) + n2*sin(phi); *signal = s > 0; /*phase jitter in the input*/ *phi_in_noise = atan2(n2,(1+n1)); } void CleanSignal( /*inputs*/ float freq_sig, double time, /*outputs*/ int *signal_clean ) { /*- clean signal at freq_IF_2 for phase jitter measurement - not slaved to the 5.23 mixer clock or the 17 MHz adpll clock */ *signal_clean = sin(pi_2*freq_sig*time) > 0; } void NoiseSource(int type, float *n1p, float *n2p) /*_ Generates Gaussian distributed noise: the noise power (sigma^2) is calculated such that, when sampled by freq_clk and bandlimited to 150 kHz, produces a S/N = (0.5A^2)/sigma^2 = 3.1627 (5 dB), for A = 1 and N = (sigma^2/freq_clk)xBW */ { float x1, x2, var;

s_clock_old = s_clock; m_clock_old = m_clock;

x1 = frand() + 1e-45; x2 = frand() + 1e-45; if(!type) var = sqrt(-2*log(x1)*variance_1); else var = sqrt(-2*log(x1)*variance_2); *n1p = var*sin(pi_2*x2); *n2p = var*cos(pi_2*x2);

} void BitGenerate( /*inputs*/ double time, double modul_start, int d_clock, /*outputs*/ int *bit_gen, int *num_bits ) { static int d_clock_old; /*generate a random train of bits*/ if ((!d_clock_old && d_clock) && (time >= modul_start)) { *bit_gen = (frand()-0.5) > 0; } d_clock_old = d_clock; } void ModulateCarrier( /*inputs*/ int type, float freq_IF, double time, int *bit_gen, /*outputs*/ int *signal, int *num_samples, float *sum_sqr_noise, float *phi_in_noise ) { float phi, s, n1, n2; phi = 2*pi*freq_IF*time; /*PSK-modulation*/ if (*bit_gen) s = -Asig*cos(phi); else s = Asig*cos(phi); /*printf("t = %e s = %e phi = %e\n", time, s, phi);*/ /*noise addition*/

} void LowPassFilter(int type, float *n1p, float *n2p) /*_ Band limits the noise processes to 75KHz. _ The filter coefficients are obtained by a bilinear transf. at a sampling freq. of freq_clk (see also ../filters/desIIR.c and dft.c)*/ { /*- sampling frequency: freq_clk = 17 MHz - use for pll_input generator without the digital mixer*/ static float a0 = 1.883942e-04, a1 = 3.767884e-04, a2 = 1.883942e-04, b1 = -1.960803e+00, b2 = 9.615566e-01; /*- sampling frequency: freq_clk = 5.23 MHz - use when the mixer is used */ static float a0_ = 1.906935e-03, a1_ = 3.813871e-03, a2_ = 1.906935e-03, b1_ = -1.872732e+00, b2_ = 8.803596e-01;

static float float out;

n1[2], n2[2], y1[2], y2[2];

/*filter first noise component*/ if(!type) out = (a0*(*n1p) + a1*n1[0] + a2*n1[1]) ( b1*y1[0] + b2*y1[1]) ; else out = (a0_*(*n1p) + a1_*n1[0] + a2_*n1[1]) -

APPENDIX A. C-CODE DESCRIPTION OF THE MLS DATA DEMODULATOR

52

( b1_*y1[0] + b2_*y1[1]) ; n1[1] n1[0] y1[1] y1[0] *n1p

= = = = =

n1[0]; *n1p; y1[0]; out; out;

/*filter second noise component*/ if(!type) out = (a0*(*n2p) + a1*n2[0] + a2*n2[1]) ( b1*y2[0] + b2*y2[1]) ; else out = (a0_*(*n2p) + a1_*n2[0] + a2_*n2[1]) ( b1_*y2[0] + b2_*y2[1]) ; n2[1] = n2[0]; n2[0] = *n2p; y2[1] = y2[0]; y2[0] = out; *n2p = out; } /*---------------------------------------------------*/ /*Header File: "digital_mixer.h" */ /*Task : convert the 5MHz IF signal to */ /* 230+-25 kHz */ /*Method : simple 1-bit sampler(flip-flop) */ /*Note : it is assumed that (image) freq. */ /* above */ /* 5.23 MHz are sufficiently suppresed */ /*Date : 15-10-96 */ /*---------------------------------------------------*/ void Mixer( /*inputs*/ int if_in, int s_clock, /*outputs*/ int *if_out ) { static int s_clock_old; if(!s_clock_old && s_clock) *if_out = if_in; s_clock_old = s_clock; } /*----------------------------------------------------*/ /*Header File: "remodulator0.h" */ /*Task : - data demodulation using a */ /* cascaded-type */ /* 2nd-order loop */ /*Note : - the loop-parameters can be changed */ /* in this file prior to compilation */ /* */ /*Date : 15-10-96 */ /*----------------------------------------------------*/ /*Loop Parameters*/ #define K1_acq 8 /*K1-counter setting for fast acquis.*/ #define K1_track 64 /*K1-counter setting in steady state*/ #define K2 8 /*K2-counter setting*/ #define N1 16 /*N1-counter setting*/ #define N2 256 /*N2-counter setting: 2N1L*/ #define L 8 /*L-counter setting*/ void PhaseDetector0(int in1, int in2, int *out); void K_Counter0(int lock, int i, int clk, int mode, int *carry, int *borrow); void ID_Circuit0(int id_clock, int i, int carry, int borrow, int *id_out); void N_Counter0(int id_out, int i, int *out_i, int *out_q, int *n_count); void L_Counter0(int out_q, int *pd_input); void Remodulator0(int in1, int in2, int *out); void Demodulator0(int in1, int in2, int *out); void DutyCycleSampler0(int data, int clk, int *out); int XOR0(int, int);

void CascadedRemodulator( /*inputs*/ int lock, int input, int m_clock, double time, /*outputs*/ int *demod_data, int *out_q_, int *N_count, FILE *file_remod, int disable ) { static int PD_input[2], PD_out[2], carry[2], borrow[2], remod_out, out_i[2], out_q[2], out_i_old[2], out_q_old[2], ID_out[2], sampled_data, PD_input_old[2], PD_out_old[2], loop, n_count[0]; /*loop-1*/ loop = 0; PD_input[0] = input; PhaseDetector0(PD_input[0], remod_out, &PD_out[0]); K_Counter0(lock, loop, m_clock, PD_out[0], &carry[0], &borrow[0]); ID_Circuit0(ID_out[1], loop, carry[0], borrow[0], &ID_out[0]); N_Counter0(ID_out[0], loop, &out_i[0], &out_q[0], N_count); Demodulator0(input, out_i[0], demod_data); DutyCycleSampler0(*demod_data, out_q[0], &sampled_data); Remodulator0(sampled_data, out_q[0], &remod_out); /*loop-2*/ loop = 1; L_Counter0(out_q[0], &PD_input[1]); PhaseDetector0(PD_input[1], out_q[1], &PD_out[1]); K_Counter0(lock, loop, m_clock, PD_out[1], &carry[1], &borrow[1]); ID_Circuit0(m_clock, loop, carry[1], borrow[1], &ID_out[1]); N_Counter0(ID_out[1], loop, &out_i[1], &out_q[1], &n_count[1]); /*output data: - to reduce the stored data, sample ouputs at data edges - note: the data file has 4 columns */ if(!disable) { loop = 1; if((!PD_input_old[loop] && PD_input[loop]) || (PD_input_old[loop] && !PD_input[loop])) fprintf(file_remod, "%e %e %e %e %e\n", time, 1.0*PD_input[loop], 1.0*out_i[loop]+1.2, 1.0*out_q[loop]+2.4, 1.0*PD_out[loop]+3.6); if((!PD_out_old[loop] && PD_out[loop]) || (PD_out_old[loop] && !PD_out[loop])) fprintf(file_remod, "%e %e %e %e %e\n", time, 1.0*PD_input[loop], 1.0*out_i[loop]+1.2, 1.0*out_q[loop]+2.4, 1.0*PD_out[loop]+3.6); if((!out_i_old[loop] && out_i[loop]) || (out_i_old[loop] && !out_i[loop])) fprintf(file_remod, "%e %e %e %e %e\n", time, 1.0*PD_input[loop], 1.0*out_i[loop]+1.2, 1.0*out_q[loop]+2.4, 1.0*PD_out[loop]+3.6); if((!out_q_old[loop] && out_q[loop]) || (out_q_old[loop] && !out_q[loop])) fprintf(file_remod, "%e %e %e %e %e\n", time, 1.0*PD_input[loop], 1.0*out_i[loop]+1.2, 1.0*out_q[loop]+2.4, 1.0*PD_out[loop]+3.6);

53 Q2[i]

} PD_input_old[0] = PD_input[0]; PD_input_old[1] = PD_input[1]; PD_out_old[0] = PD_out[0]; PD_out_old[1] = PD_out[1]; out_i_old[0] = out_i[0]; out_i_old[1] = out_i[1]; out_q_old[0] = out_q[0]; out_q_old[1] = out_q[1]; *out_q_

= (!Qb1[i] (!Qb2[i]

&& Qb2[i] && Qb3[i]

/*execute JK flip-flop: note J and K are updated after evaluating JK output*/ JK[i] = (J [i] && !K[i] ) || (J[i] && K[i] && !JK[i] ); J[i] = !Q1[i] ; K[i] = !Q2[i] ;

= out_q[0];

}

/*shift Qc3[i] Qc1[i] Qb3[i] Qb1[i]

void PhaseDetector0( /*inputs*/ int in1, int in2, /*outputs*/ int *out ) { *out = XOR(in1, in2); }

carry and borrow pulses*/ = Qc2[i] ; Qc2[i] = Qc1[i] ; = carry; = Qb2[i] ; Qb2[i] = Qb1[i] ; = borrow;

} /*evaluate output: pulse = 1 if clocK = 0 && JK = 0*/ *id_out = !(JK[i] || id_clock); id_clock_old[i]

void K_Counter0( /*inputs*/ int lock, int i, int clk, int mode, /*outputs*/ int *carry, int *borrow ) { static int K[2], up_count[2], down_count[2]; static int clk_old[2];

= id_clock;

} void N_Counter0( /*inputs*/ int id_out, int i, /*outputs*/ int *out_i, int *out_q, int *n_count ) { static int count[2], N[2]; static int id_out_old[2];

if(clk_old[i] && !clk) { /*set counter length*/ if(lock) K[0] = K1_track; else K[0] = K1_acq; K[1] = K2;

if(id_out_old[i] && !id_out ) { N[0] = N1; N[1] = N2; count[i] = (count[i] + 1) % N[i]; *out_i = (count[i] >= N[i]/2); /*lags by 90 deg*/ *out_q = (count[i] >= N[i]/4 && count[i] = K[i]/2); *borrow = (down_count[i] >= K[i]/2); } } clk_old[i] = clk; } void ID_Circuit0( /*inputs*/ int id_clock, int i, int carry, int borrow, /*outputs*/ int *id_out ) { /* model for a real increment-decrement circuit (see Philips 74HCT297 Manual): - edges of the carry or borrow pulses are detected by comparing the shift register contents*/ static int Qc1[2], Qc2[2], Qc3[2]; /*carry pulse shift reg.*/ static int Qb1[2], Qb2[2], Qb3[2]; /*borrow pulse shift reg.*/ static int Q1[2], Q2[2]; /*for synch. with the sampling clock.*/ static int JK[2], J[2], K[2]; /*to generate a frequency at half ID-clock*/ static id_clock_old[2]; if(id_clock_old[i] && !id_clock) { /*perform edge detection (down going) and save into the synch. flip-flops*/ /*carry pulse*/ Q1[i] = (!Qc1[i] && Qc2[i] && JK[i] (!Qc2[i] && Qc3[i] && JK[i] /*borrow pulse*/

&& !JK[i] ) || && !JK[i] );

) || );

void L_Counter0( /*inputs*/ int out_q, /*outputs*/ int *pd_input ) { static int count; static int out_q_old; if(L == 1) *pd_input = out_q; else { if(out_q_old && !out_q) { count = (count + 1) % L; *pd_input = count >= L/2; } out_q_old = out_q; } } void Remodulator0( /*input*/ int in1, int in2, /*outputs*/ int *out ) { *out = XOR(in1, in2); } void Demodulator0(

54

APPENDIX A. C-CODE DESCRIPTION OF THE MLS DATA DEMODULATOR sampled_data, input_old;

/*input*/ int in1, int in2, /*outputs*/ int *out

PhaseDetector(input, remod_out, K_Counter(lock, m_clock, PD_out, &borrow); RateMultiplier(m_clock, carry, borrow, ID_Circuit(RM_out, carry, borrow, N_Counter(ID_out, &out_q, n_count); Demodulator(input, out_i, DutyCycleSampler(*demod_data, out_q, Remodulator(sampled_data, out_q,

) { *out = XOR(in1, in2); } void DutyCycleSampler0( /*inputs*/ int data, int clk, /*outputs*/ int *out ) { static int clk_old;

clk_old = clk; } int XOR0(int a, int b) { return (1-(a == b)); }

void PhaseDetector(int in1, int in2, int *out); void K_Counter(int lock, int clk, int mode, int *carry, int *borrow); void ID_Circuit(int id_clock, int carry, int borrow, int *id_out); void N_Counter(int id_out, int *out_i, int *out_q, int *n_count); void N_Counter2(int id_out, int *out_i, int *out_q, int *n_count); void RateMultiplier(int m_clock, int carry, int borrow, int *RM_out); void Remodulator(int in1, int in2, int *out); void Demodulator(int in1, int in2, int *out); void DutyCycleSampler(int data, int clk, int *out); int XOR(int, int); void RM_Remodulator( /*inputs*/ int lock, int input, int m_clock, double time, /*outputs*/ int *demod_data, int *out_q_, int *n_count, FILE *file_remod, int disable ) { static int PD_out, carry, borrow, remod_out, out_i, out_q, out_i_old, out_q_old, RM_out, ID_out,

&RM_out); &ID_out); &out_i, demod_data); &sampled_data); &remod_out);

/*output data: - to reduce the stored data, sample ouputs at data edges - note: the data file has 4 columns */ if(!disable) { if((!input_old && input) || (input_old && !input)) fprintf(file_remod, "%e %d %d %d\n", time, input, out_i+2, out_q+4); if((!out_i_old && out_i) || (out_i_old && !out_i)) fprintf(file_remod, "%e %d %d %d\n", time, input, out_i+2, out_q+4); if((!out_q_old && out_q) || (out_q_old && !out_q)) fprintf(file_remod, "%e %d %d %d\n", time, input, out_i+2, out_q+4); } *out_q_ = out_q;

if(clk_old && !clk) *out = data; /*sample at down going edge & hold*/

/*-------------------------------------------------*/ /*Header File: "remodulator1.h" */ /*Task : - data demodulation using a */ /* rate-multiplier */ /* based 2nd-order loop */ /*Note : - the loop-parameters can be */ /* changed in this */ /* file prior to compilation */ /* - rate multiplier ouput */ /* freq = f_(m_clk)P/Q */ /* */ /*Date : 15-10-96 */ /*-------------------------------------------------*/ /*Loop Parameters*/ #define K_acq 8 /*for fast acquis.*/ #define K_track 64 /*for tracking*/ #define N 32 /*N-counter setting*/ #define Q 1024 /*accumulator size*/ #define P_max 1023 /*for max freq: fin ~ f_clk/2N kHz*/ #define P_min 768 /*for min freq: fin ~ 200 kHz*/ #define P_mid 886 /*for initialization*/

&PD_out); &carry,

input_old = input; out_i_old = out_i; out_q_old = out_q; } void PhaseDetector( /*inputs*/ int in1, int in2, /*outputs*/ int *out ) { *out = XOR(in1, in2); } void K_Counter( /*inputs*/ int lock, int clk, int mode, /*outputs*/ int *carry, int *borrow ) { static int K, up_count, down_count; static clk_old; if(clk_old && !clk) { /*set counter length*/ if(lock) K = K_track; else K = K_acq; /*produce carry and borrow pulses*/ if (!mode) up_count = (up_count + 1) % K; *carry = (up_count >= K/2); if (mode) down_count = (down_count + 1) % K; *borrow = (down_count >= K/2); } clk_old = clk; } void ID_Circuit( /*inputs*/ int id_clock, int carry, int borrow, /*outputs*/ int *id_out ) {

55 if(Q1_old && !Q1) if(Q2_old && !Q2)

/* model for a real increment-decrement circuit (see Philips 74HCT297Manual): - edges of the carry or borrow pulses are detected by comparing the shift register contents*/ static int Qc1, Qc2, Qc3; /*carry pulse shift register*/ static int Qb1, Qb2, Qb3; /*borrow pulse shift register*/ static int Q1, Q2; /*for synch. with the sampling clock.*/ static int JK, J, K; /*to generate a frequency at half ID-clock*/ static id_clock_old; if(id_clock_old && !id_clock) { /*perform edge detection (down going) and save into the synch. flip-flops*/ /*carry pulse*/ Q1 = (!Qc1 && Qc2 && JK ) || (!Qc2 && Qc3 && JK ); /*borrow pulse*/ Q2 = (!Qb1 && Qb2 && !JK ) || (!Qb2 && Qb3 && !JK ); /*execute JK flip-flop: note J and K are updated after evaluating JK output*/ JK = (J && !K ) || (J && K && !JK ); J = !Q1 ; K = !Q2 ; /*shift carry and borrow pulses*/ Qc3 = Qc2 ; Qc2 = Qc1 ; Qc1 = carry; Qb3 = Qb2 ; Qb2 = Qb1 ; Qb1 = borrow; } id_clock_old

Q2 = !Q2; {Q3 = !Q4; Q4 = Q3_old;}

/*compute counter value: Note: the Jonson counter gives grey-code which must be converted to binary first*/ count = Q0+2*(Q1+2*(Q2+2*(XOR(Q3,Q4)+2*Q4))); /*wave forms: - Q3 leads Q4 by 90 deg - the (out_i, out_q) selection below allows lock with a down-going edge duty-cycle sampler and a non-invereted "sampled_data" input to the remodulator */ *out_i = Q4; *out_q = Q3; *n_count = count; Q0_old = Q0; Q1_old = Q1; Q2_old = Q2; Q3_old = Q3; Q4_old = Q4; id_out_old = id_out; } void RateMultiplier( /*inputs*/ int m_clock, int carry, int borrow, /*outputs*/ int *RM_out ) { static int p_count = P_mid; /*initialized to mid value*/ static int sum, regist, overflow; static int m_clock_old, carry_old, borrow_old;

= id_clock; /*calculate frequency setting number(P)*/ if(carry_old && !carry && p_count < P_max) p_count ++; if(borrow_old && !borrow && p_count > P_min) p_count --;

/*evaluate output: pulse = 1 if clocK = 0 && JK = 0*/ *id_out = !(JK || id_clock); } void N_Counter( /*inputs*/ int id_out, /*outputs*/ int *out_i, int *out_q, int *n_count ) { static int count; static int id_out_old; if(id_out_old && !id_out ) { count = (count + 1) % N ; *out_i = (count >= N /2); /*lags by 90 deg*/ *out_q = (count >= N /4 && count = Q; if (m_clock_old && !m_clock) regist = sum; m_clock_old = m_clock; carry_old = carry; borrow_old = borrow; *RM_out = m_clock && overflow; } void Remodulator( /*input*/ int in1, int in2, /*outputs*/ int *out ) { *out = XOR(in1, in2); } void Demodulator( /*input*/ int in1, int in2, /*outputs*/ int *out ) { *out = XOR(in1, in2); } void DutyCycleSampler( /*inputs*/ int data, int clk, /*outputs*/ int *out

56

APPENDIX A. C-CODE DESCRIPTION OF THE MLS DATA DEMODULATOR return count >= (N_mclk/2);

) {

} static int clk_old; if(clk_old && !clk) *out = data; /*sample at DOWN going edge & hold*/

int D_Clock(int m_clock) { static int count, m_clock_old; if(!m_clock_old && m_clock) count = (count + 1) % N_dclk; m_clock_old = m_clock; return count >= (N_dclk/2);

clk_old = clk; } int XOR(int a, int b) { return (1-(a == b)); }

}

/*---------------------------------------------------*/ /*Header File: "clock_generator.h" */ /*Task : generates 17,5.23,4.25,1.0625 MHz */ /* clocks */ /* */ /*Date : 15-10-96 */ /*---------------------------------------------------*/ #define freq_ref 68e6 /*reference clock*/ #define freq_mclk 17e6 /*ADPLL master clock*/ #define N_mclk 4 /*freq_ref / freq_clk*/ #define N_sclk0 13 /*freq_ref/(freq_sclk1=5.23M) for mixer input*/ #define N_sclk1 4 /*freq_mclk/(freq_sclk1=4M) for synch. tracking*/ #define N_sclk2 16 /*freq_mclk/(freq_sclk2=1M) for lock detection*/ #define N_dclk 1088 /*freq_mclk/(freq_dclk=15.625kHz) transmitting data clock*/ int int int int int int

R_Clock(); M_Clock(int r_clock); S_Clock0(int r_clock); S_Clock1(int m_clock); S_Clock2(int m_clock); D_Clock(int m_clock);

void ClockGenerator( /*inputs*/ /*outputs*/ int *m_clock, int *d_clock, int *s_clock0, int *s_clock1, int *s_clock2, double *time ) { int r_clock; r_clock = R_Clock(); *m_clock = M_Clock(r_clock); *d_clock = D_Clock(*m_clock); *s_clock0 = S_Clock0(r_clock); *s_clock1 = S_Clock1(*m_clock); *s_clock2 = S_Clock2(*m_clock); *time = *time + 1/freq_ref; /*calls every ref. clock period*/ /*printf("m_clk = %d

%d\n", *m_clock, *s_clock0);*/

} int R_Clock() { /*generate reference clock*/ static int clock_old; clock_old = !clock_old; return clock_old; } int M_Clock(int r_clock) { /*generate master clock*/ static int count, r_clock_old; count = (count + 1) % N_mclk; r_clock_old = r_clock;

int S_Clock0(double time) /* - divide-by-N_sclk0(=13) - generates a ~5.23 MHz clock for clock synch. filtering and tracking */ { static int count, r_clock_old; /*return (cos(pi_2*freq_mixer_clk*time) > 0);*/ count = (count + 1) % N_sclk0; r_clock_old = r_clock; return count >= (N_sclk0/2); } int S_Clock1(int m_clock) /* - divide-by-N_sclk1(=4) - generates a ~4 MHz clock for clock synch. filtering and tracking */ { static int count, m_clock_old; if(!m_clock_old && m_clock) count = (count + 1) % N_sclk1; m_clock_old = m_clock; return count >= N_sclk1/2; } int S_Clock2(int m_clock) /* - divide by N_sclk2(=16) - generates a ~1 MHz clock for lock detection filtering and data-clock input */ { static int count, m_clock_old; if(!m_clock_old && m_clock) count = (count + 1) % N_sclk2; m_clock_old = m_clock; return count >= N_sclk2/2; } /*---------------------------------------------------*/ /*Header File: "data_filter.h" */ /*Task : generates */ /*"data_filter.h": - integrate & limit(~dump) type filter for . acquisition (lock detection) . synchronization . tracking - Note: . Acquisition: - the filter is clocked at 1 MHz and the up/down counter operates in -128 to +128 range => integration time = tau = 128 us - due to phase ambiguty, the loop can lock in-phase or out-of-phase to the input signal => two thresholds (TH_low and TH_high) - 1 MHz clock implies at least 3 samples from one input signal cycle (215 kHz to 265 kHz for rate multiplier based ADPLL) => OK for majority decision on the duty-cycle information

57 } else {

. Synchronization: - the filter is clocked at 4 MHz and the up/down counter operates in 0 to 31 count => integration time = tau = 32*0.25 = 8us - though lock detection requires N=256 and the counter is frozen to 0 or 255 value, it is still possible to use the 5-LSBs for integration - for full integration tau = 32/fclk = 8us => approx. cut-off freq. = 1/2pi*tau = 19.89 kHz enough to reject the 2*fin spikes and some noise => short enough to keep edge information since edge = dv/dt, where v = counter value . Tracking: - the is filter clocked at 4 kHz and uses counts in the range 0 to 255 => integration time = tau = 256/4 = 64 us = bit duration - if conescutive bits are the same, the counter is frozen at 0 or 255 Note:- as limit detection is already needed in the synch. mode(5 bits), the extra hardware cost is small (for 3 more MSBs) - the result could also be dumped every 64 us */ /* */ /*Date : 15-10-96 */ /*---------------------------------------------------*/ #define N_acq 256 /*counter length during acquisition*/ #define N_synch 32 /*counter length during clock synch*/ #define N_track 256 /*counter length during tracking*/ #define TH_low 31 /*lower threshold for lock detection*/ #define TH_up 225 /*upper threshold for lock detection*/

/*tracking mode: at 4 MHz clock*/ s_clock = s_clock1; N_filt = N_track; /*synchronzed received bits: - to data clock(ideal case)*/ if(!d_clock_old && d_clock) { *out_data = filter_count > N_track/2; /*count decision errors*/ ErrorCount(out_data, bit_gen, num_bits, err_count); } } /*limited integration: - in the case of "synch or type = 1", max_limit = N_synch = 31. => if lock is in phase, i.e., via TH_low, the count down eventually put filter_count to 0(+error) => if lock is out of phase, i.e., via TH_high, max_limit < filter_count(at lock) => - no up count possible - down count due to noise brings filter_count to max_limit - filter_count stays at max_limit until a 0 bit is received which causes further down count till min_limit = 0) */ if(!s_clock_old && s_clock) { if(in_data && filter_count < N_filt) filter_count ++; else if(!in_data && filter_count > 0) filter_count --; } *filt_state = filter_count;

void ErrorCount(double time, int *out_data, int bit_gen, int *num_bits, int *err_count); int XOR2(int a, int b); int DataFilter( /*inputs*/ double time, int type, int reset, int in_data, int s_clock1, int s_clock2, int bit_gen, int d_clock, /*outputs*/ int *out_data, int *filt_state, int *num_bits, int *err_count ) { static int filter_count, N_filt; static int s_clock, s_clock_old, d_clock_old; if(type == 0) { /*acquisition mode: at 1 MHz clock*/ /*set to mid-value*/ if(reset) filter_count = N_acq/2; s_clock = s_clock2; N_filt = N_acq; /*lock detect*/ *out_data = ((filter_count < TH_low) || (filter_count > TH_up)); } else if(type == 1) { /*synchronization mode: at 4 MHz clock*/ s_clock = s_clock1; N_filt = N_synch; /*trigger pulse*/ *out_data = filter_count == N_synch/2;

/*set old values*/ s_clock_old = s_clock; d_clock_old = d_clock; } void ErrorCount( /*inputs*/ double time, int *out_data, int bit_gen, /*output*/ int *num_bits, int *err_count ) { static int out_data_old, bit_gen_old[2], count; int error; /*to avoid 180 deg phase ambiguity, DPSK decode prior to comparison */ error = XOR2(*out_data, out_data_old) != XOR2(bit_gen_old[0], bit_gen_old[1]); count++; if(count > 2) { /*note: the first two bits are ignored since the error count is started in the middle of data transmission and the 1st bit of "out_data" represents an old "bit_gen" which is not used in the counting process */ (*num_bits)++; if(error) { (*err_count)++;

APPENDIX A. C-CODE DESCRIPTION OF THE MLS DATA DEMODULATOR

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printf("bit error1: time = %e err_count = %d\n", time, *err_count); } } /* printf("count = %d ", count); printf("b_gen_prev = %d b_out = %d b_gen_dec = %d b_out_dec = %d\n", bit_gen_old[0], *out_data, error); */ /*old values: 1-bit delay is added to the incoming data stream to account for delay in the decision output*/ bit_gen_old[1] = bit_gen_old[0]; bit_gen_old[0] = bit_gen; out_data_old = *out_data;

/*Task : routines for some data analysis */ /*Date : 15-10-96 */ /*--------------------------------------------------*/ void MeasurePhaseShift( /*inputs*/ int i, int u_in1, int u_in2, double time, float freq_signal, /*outputs*/ float *phase ) { static int u_in1_old[2], u_in2_old[2]; static float phi[2]; static double prev_time[2]; if(u_in1_old[i] && !u_in1) prev_time[i] = time; if(u_in2_old[i] && !u_in2) { phi[i] = 2*pi*freq_signal*(time - prev_time[i]); if(phi[i] > 4*pi) phi[i] = phi[i] - 4*pi; } *phase = phi[i];

} int XOR2(int a, int b) { return (1-(a == b)); }

u_in1_old[i] = u_in1; u_in2_old[i] = u_in2; /*--------------------------------------------------*/ /*Header File: "measurement.h" */

}