Session M2G
Design Space Exploration of Embedded Processors in Computer Architecture Education using T&D-Bench Sandro Neves Soares1, Flávio Rech Wagner 2 Abstract - We present T&D-Bench, Teaching and Design Workbench, a framework for design space exploration of embedded processors. Design space exploration has become a fundamental phase of the SOC (System on a Chip) design process in industry and in research, and so it is important also in Computer Architecture education. T&D-Bench is an innovative framework to be employed in Computer Architecture education, providing the students a contact with a contemporary hardware design activity, and offering an easy and rapid design process, together with graphical user interface resources for tracking and steering the experiments with the processor models. T&DBench has been used at Universidade de Caxias do Sul since 2003 with positive results reported by the students, both beginners and seniors. T&D-Bench is available as an open source and platform-independent framework on the Internet. Index Terms – Computer Architecture education, Design Space Exploration, Embedded Systems Design, Processor Modeling and Simulation. INTRODUCTION Design space exploration (DSE) is now an important phase of the SOC (System on a Chip) design process in industry and in research, and so it is in Computer Architecture education since, if Computer Architecture is a science at all, it is a science of trade-offs. The student is best served if he/she thoroughly understands the fundamental principles so as to be able to make the appropriate trade-offs in reaching a particular design objective [1], regarding performance and cost of each possible architectural solution, for instance. The main objective of T&D-Bench, and its relevance for engineering education, is to offer resources for design space exploration that are available only in professional and research CAD tools, based on Architecture or Hardware Description Languages, while avoiding the steep learning curves required for understanding and using such description languages. Seniors students are provided with an easy and rapid design process that can be employed to create a processor model from scratch or to explore the design space, altering models or their configurations. Beginners, in turn, are users of the processor simulators generated by T&D-Bench designers (seniors, or the instructor himself). At simulation time, the T&D-Bench processor models incorporate, automatically, graphical user 1 2
interface resources for tracking and steering the experiments. The only requirement to install and use T&D-Bench, on a specific platform, is the availability of the Java Runtime Environment. The remainder of the paper is organized as follows. We first explain why T&D-Bench has been developed. A section discussing related work then follows. The framework’s design methodology is then presented. A further section describes the T&D-Bench resources for tracking and steering the simulation experiments. Obtained results are then presented, and the paper is closed drawing final conclusions and discussing future work. MOTIVATION The most common problems in Computer Architecture education, as reported in the literature, are [2]: • The complexity of Computer Architecture concepts – minimization of logical functions, assembly programming and data dependencies, for example, are subjects that require a considerable effort to be learned and are easily forgotten by the students; • The growth of the Computer Architecture area – this means more concepts to be taught in the same courses of the curriculum; • The different expectations of Computer Science and Engineering students – most of them need just an overview of the related subjects, while only a reduced number will work with hardware design; • The less applicability of the concepts in the professional environment when compared to other Computer Science areas, such as Software Engineering; • The difficulty to experiment with hardware – the laboratories have a cost to be equipped, and important microprocessor mechanisms, such as data forwarding in a pipelined processor, are not feasible to be showed to the students inside the real hardware. In the technical literature, we can find different methodologies employed to overcome the Computer Architecture education problems [2]. These methodologies have in common the use of software and/or hardware environments of one of the following categories: • Didactic simulators – they are simple programs, specialized to be employed in education, with graphical
Sandro Neves Soares, Universidade de Caxias do Sul, Brasil,
[email protected] Flávio Rech Wagner, Universidade Federal do Rio Grande do Sul, Instituto de Informatica, Brasil,
[email protected]
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user interface resources for experimenting with some processor models (one to three models are very common); CAD tools based on Hardware Description Languages – they are complex environments, with a considerable number of resources, largely employed by the industry and also in education. CAD tools provide a contact with professional tools, but the learning of a hardware description language is not a trivial task and requires a considerable time ; and Hardware kits – they include microcontrollers and a set of peripheral devices. These kits have a more restrict use in Computer Architecture education compared to the other two categories, since the student can experiment with only a single processor model.
Table 1 shows how these three categories of environments handle the problems of Computer Architecture education. The gray cells indicate a solution to the problem, while white cells explain why the category does not treat that problem. TABLE I SOLUTIONS TO THE COMPUTER ARCHITECTURE EDUCATION PROBLEMS Didactic CAD Tools Hardware Kits Simulators Using a high The use of an The level of Complexity level of HDL is not a abstraction abstraction and trivial task employed is low didactic (very detailed resources subjects) Using a high They add new The level of Growing level of contents to be abstraction number of abstraction and learned by the employed is low subjects didactic students (the (more details to resources language itself) be learned) Environments The didactic The student have Expectations of may be too simulators are contact with a students that complex to be implemented to single processor require only a be employed in employed by the that, in most general view education. The students cases, does not high level of employ complex abstraction architectural avoids too many mechanisms details. CAD tools are They do not They do not Expectations of created to be provide provide hardware employed in modeling modeling designers hardware capabilities capabilities design The student can Tools are Microcontrollers Practice of the program in largely are largely concepts assembly, for employed in employed in (applicability) example industry industry By means of By means of the The student have Hardware language a direct contact experimentation block diagrams representing the constructs and with the hardware. They the possibility of hardware replace a direct prototyping the experimentation designs
satisfy the expectations of the potential hardware design students. This was our motivation to build the T&D-Bench framework. T&D-Bench provides modeling resources that allow the construction of new didactic simulators. The framework’s design, or modeling, process is easy and fast. This way the user can focus on the design process itself, instead of on the tool employed to execute the process. Later on, having already acquired the design process skills, the student can learn the professional tools used in industry. RELATED WORK PCSpim [3] is a simulator used to teach how to program in assembly language of the MIPS R3000 processors. It can be executed using a graphical interface or the command line. The simulators DLXview [4] and DARC2 [5] have a graphical interface to show the internal operations of the three execution modes of the DLX processor [6]: basic pipeline, Tomasulo algorithm and scoreboarding. ESCAPE [7] simulates two alternative processor organizations: micro-programmed or pipelined. SPIECS [8] is an integrated educational environment composed by three independent systems: a computer system based on a RISC (RCS) or on a CISC processor (CCS); and a Hierarchical Memory System (HMS). SATSim [9] is an interactive and animated tool employed to teach superscalar concepts. HASE [10] is a software environment for modeling and simulation of computer systems composed by hardware and software. The modeling capabilities of HASE make this environment similar to T&DBench, but HASE is not fully platform-independent and the modeling task cannot be accomplished using a GUI, as T&DBench. PUNCH [11] is a web portal on the internet that allows the access and remote execution of software tools by means of internet browsers. RaVi [12] includes multimedia components to help the visualization of the dynamic behavior of the hardware components. Some components available include a MIPS pipeline and the MESI protocol for multiprocessors. MythSim [13] is a simulator employed by the students to implement the microcode of the assembly language of an 8-bit microprocessor. WebMIPS [14] is a MIPS simulator that can be executed via a web browser. The use of CAD tools and hardware kits in Computer Architecture Education are described in multiple references [15 – 18]. MODELING IN T&D-BENCH I. Design Methodology Principles
The educational purpose of T&D-Bench motivated us to search elements that simplify the task of design space exploration in existing educational tools. It is also our objective to avoid imposing limits to the designer regarding The information in Table 1 show that didactic simulators the modeling of embedded processors. The elements found provide the most generic solution for Computer Architecture were used to define the principles of our design methodology: education since they handle a larger number of problems and • the descriptions should be produced using high-level also satisfy the expectations of the most part of Computer modeling resources. In education, higher abstraction Science and Engineering students. If, in addition, didactic levels are used to accelerate the teaching and also the simulators provide modeling capabilities, they could also understanding of complex notions; 1-4244-0257-3/06/$20.00 © 2006 IEEE October 28 – 31, 2006, San Diego, CA 36th ASEE/IEEE Frontiers in Education Conference M2G-20
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there should be modeling resources to describe the different aspects of an embedded processor, namely micro-architecture, instruction set, and timing, and the description of these different aspects should be made using an orthogonal approach. In the educational context, the early mixing of information related to different domains does not contribute to the understanding of the concepts and theories by the students; the modeling resources should be organized into layers in a way that the use of the resources in the external layer is simpler than the use of those in the internal layers. This has been achieved by associating resources to the external layer that are only related to the problem domain, i.e., the different architectural aspects of an embedded processor, while the resources in the internal layers are more dependent on a knowledge of the software infrastructure that implements the design methodology. This is similar to the approach used in education, where the introductory concepts are mandatory for the student to learn the most complex theories and practices later on.
These elements are basic to the key innovative principles of the T&D-Bench design methodology to provide an easier and more accelerated DSE process, which are threefold: the organization of the high-level modeling resources into layers with different objectives and complexity levels, leveraging the designer knowledge about embedded processors; the reduced number of elements (keywords, classes, and methods) that must be known by the designer to access the resources in the various layers; and the availability of specific and orthogonal resources for the specification of the processor microarchitecture, instruction set, and timing. II. Design Methodology Overview The component library is the basis for the construction of new processor models in T&D-Bench. Micro-architectural processor aspects are modeled by the selection, parameterization, and interconnection of components available in the library. The definition of component execution sequences (as hardware micro-operations) builds elementary execution units that can be reused to form the instructions’ behavior. Timing of the processor can be expressed separately from the previous specifications and later associated to individual component execution statements into elementary execution units. The T&D-Bench simulation procedure can use these timing specifications in different ways to model mono-cycle, multi-cycle, and pipelined microprocessor execution paths. These specifications are produced by the T&D-Bench definition language and are translated into internal data structures that can be manipulated by a set of specialized methods, called T&D-Bench macros, which are provided by the environment to model more complex processor mechanisms. The three layers of modeling resources in the T&D-Bench design methodology are shown in Figure 1. The component library and the framework’s main class, provided to the designer to use the macros, constitute the T&D-Bench’s software infrastructure.
T&D-Bench Macros
Definition Language
Component Library
Designer
FIGURE 1. T&D-BENCH DESIGN METHODOLOGY OVERVIEW
The definition language is a very simplified language to leverage the design process. It has resources for modeling the micro-architecture, instruction set, and timing aspects of the embedded processor. The use of the definition language demands only knowledge related to the architecture of embedded processors and it is mostly sufficient to model simple processors as those employed in education. Figure 2 shows some elements of the definition language using a specification of the type R arithmetic and logic instructions of the MIPS I processor: • muxpc.SEL=1 states that the control port SEL of the component Program Counter multiplexer has the value 1 assigned to it. if_id.write defines a write operation in the pipeline register between stages FETCH and DECODE; • include fetchInstruction includes an existing elementary execution unit in the description; • mop[number] is used to link a micro-operation to a specific execution stage defined in the timing specifications. The range of numbers 0 to 4 corresponds to the MIPS I pipeline stages FETCH, DECODE, EXECUTE, MEMORY, and WRITEBACK, respectively. mop[0] muxpc.SEL = 1 mop[0] include fetchInstruction mop[0] if_id.write //
mop[1] if_id.read mop[1] include readRegisterBank mop[1] id_ex.write //
mop[2] id_ex.read mop[2] muxa.SEL = 1 mop[2] muxb.SEL = 0 mop[2] include executeAluOperation mop[2] ex_mem.write //
mop[3] ex_mem.read mop[3] mem_wb.write //
mop[4] mem_wb.read mop[4] muxwb.SEL = 1 mop[4] include writeRegisterBank FIGURE 2. MIPS I ARITHMETIC INSTRUCTION SPECIFICATION
The T&D-Bench macros are used to model more specialized characteristics of the processor, such as data dependencies or branch prediction. The use of macros is carried out by programming the T&D-Bench’s software infrastructure main class, called class processor. For example, the macros Pipeline.getCurrentInst and Instruction.get may be
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Session M2G employed in a method of this class to detect data hazards. The first is used to get the current instruction in a specified execution, or pipeline, stage; and the latter is used to test an instruction field, such as the numbers of the registers to be written. The component library is implemented as a set of classes where each class describes an individual structural component that exist in embedded processor datapaths, such as multiplexers, registers, functional units, register files, memories, and others. The designer must program new classes if the structural component required by the model is not available in the library. This type of work will not be performed often, since the library already provides various components of embedded processors. The skills required to use the T&D-Bench modeling resources, in the two internal layers, are only those related to programming with the object-oriented programming language Java, since the definition language specifications, due to their simplicity, can be produced using a Graphical User Interface (GUI) available in the T&D-Bench software infrastructure. For example, the user drags and drops icons representing the structural components on a canvas to compose the processor micro-architecture. More information about the T&D-Bench design methodology can be found in [19].
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the values in the registers and in the memories. When the component keeps more than one value, tables are used to show them; the exact behavior executed by the component in that clock cycle, by means of a color scheme, where yellow and red specify a read or write in a sequential component; orange specifies the activation of a combinational component; and white indicates that the component was not used in the previous clock cycle.
FIGURE 3. MIPS I DIDACTIC SIMULATOR
SIMULATION IN T&D-BENCH The GUI used to create a processor model provides the graphical resources to be employed also during the simulation to track and steer the experiments. Since the graphical resources have a direct relationship with the T&D-Bench design methodology, the processor models share the same GUI. The processor model itself plus the GUI constitute a didactic simulator. There are various processor models already available to the instructor and students, and other ones can be constructed as well. They can be employed to present different modules of Computer Architecture subjects in distinct stages of a course or along a sequence of courses in the curriculum. Since all of them share the same GUI, the student doesn’t need to worry about learning a new GUI when he/she initiates the study of a new processor. Figure 3 shows the window of a T&D-Bench’s didactic simulator displaying the pipelined MIPS I processor microarchitecture as a block diagram. Figure 4 shows the same window displaying the micro-architecture of a didactic microprogrammed processor called Neander. The approach employed to simulate processor models in T&D-Bench includes the following steps: (1) the user loads an assembly program; (2) he/she simulates the program execution, cycle by cycle, or during a specified number of cycles; and (3) he/she tracks and steers the experiment using the resources available in the GUI. The user can visualize in the block diagram window: • the various components of the processor microarchitecture, as well as their interconnections; • the current values in the component’s ports (input, output, and control ports);
FIGURE 4. NEANDER DIDACTIC SIMULATOR
These visualization forms can be employed to study the behavior of an individual component, before analyzing its interaction with other components in the micro-architecture. They can be also employed to observe the behavior of all components while executing the micro-operations of the current instruction(s) and to visualize the processor status. Figure 5 shows the window used to display the status of a specific component selected by the user. The values of ports and the contents and attributes of the component are shown in a tabular form. This window can show the processor status as well. For example, it can show if data forwarding is enabled or not. The information in this window complements that displayed in the block diagram window. Figure 6 shows the window used to display information about the instructions in each of the pipeline stages of the MIPS I pipeline, such as the values in the bit fields and other attributes created by the designer to identify if the instruction
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Session M2G was discarded or not, for example. These visualization forms can be employed to understand the relationship between the values in the bit fields and the status of the micro-architecture components. They also help to visualize the temporal evolution of the instructions in execution, their superposition in time, and the actions to handle data and resource conflicts.
FIGURE 5. COMPONENT STATUS WINDOW
T&D-Bench has been used in Computer Architecture education at Universidade de Caxias do Sul since 2003. More than 100 students, enrolled in the last three editions of the Computer Organization and Architecture course of the Information Systems curriculum, have had a contact with the framework. The course provides an overview of introductory Computer Architecture concepts. The approach used in classroom includes the use of the framework by the instructor to illustrate the following topics: (1) the von Neumann model; (2) sequential and combinational circuits; and (3) an introduction to the micro-programmed Neander instruction set and micro-architecture. After that, programming exercises are proposed to the students using the assembly language of the Neander processor. The students have also an alternative exercise if they do not want to use the simulator. Finally, the students that worked with T&D-Bench must choose one of the exercises and present their solution to the other students in the classroom. In this last edition of the course, almost all the 24 students chose to use the simulator and some agreed to study and develop the programs for the MIPS I processor. The programs elaborated by the students are on the T&D-Bench webpage. Four questions were proposed to these 24 students to know their opinions about the use of the simulator. They required only a positive or negative answer. The results are summarized in Table 2. TABLE II STUDENTS FEEDBACK Questions
FIGURE 6. INSTRUCTIONS IN EXECUTION
In addition to these visualization forms, the GUI also provides menus and dialog boxes to be used by the user to change aspects of the processor model. While steering an experiment, the user can: • Modify values of ports, contents, or attributes of components or of the processor itself (for example to enable the data forwarding); • Delete components or interconnections; • Modify the values in the bit fields of a instruction or discard the execution of an instruction; • Freeze or release execution stages or pipeline stages, and discard the instructions executing in specific stages. RESULTS T&D-Bench is free and available as an open source and platform-independent framework at the following address: • www.ucs.br/carvi/cent/dpei/snsoares/TDBench where simulation models of some didactic processors are also ready to use. These models include: the didactic microprogrammed CISC processor Neander [20] and the monocycle, multi-cycle, and pipelined versions of the MIPS I processor.
(1). Did you use the simulator? (2). The use of this simulator helps the comprehension of Computer Architecture concepts? (3). The use of this simulator helps to learn assembly programming? (4). The use of this simulator helps to understand the relationship between architecture and organization concepts (concerning the color scheme employed)?
Percentage of Positive Answers 91.67 % 95.83 % 87.50 % 79.17 %
The information in Table 2 allows the following considerations: • The greater percentage of positive answers in question 2 compared to question 1 indicates that even students who didn’t use the tool approved the simulator; • The answers of the students that do not use the simulator were considered as negatives in question 3. If this was not the case, the percentage would be greater, about 95%; • The smaller percentage in question 4 should be due to the fact that the use of this resource was not mandatory to verify the correctness of assembly programs, i.e., the students could also see the program execution results in the processor registers, without using the color scheme. Besides the positive numbers presented in Table 2, the use of T&D-Bench constitutes a better approach to present Computer Architecture concepts than the use of slides in conventional classrooms, because the students get more motivated and involved.
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Session M2G Two senior students employed the more advanced modeling resources of the framework. One of them developed a component cache memory and the other one searched and employed benchmarks for the MIPS I model. A senior student is now beginning to extend the MIPS I model, in order to implement a reduced instruction set for energy reduction [21]. One graduate student worked in the graphical resources module of the framework. All of them reported a better understanding of Computer Architecture concepts and a greater interest in the area. CONCLUSION This work shows that didactic simulators are very important to Computer Architecture education because, when compared to other approaches, based on CAD tools or hardware kits, they handle a larger number of the problems in Computer Architecture education and also they satisfy the expectations of the most part of Computer Science and Engineering students. The work presents also T&D-Bench, a framework for the construction of didactic simulators. T&D-Bench matches the advantages of didactic simulators with an easy and rapid design process employed to create them. The didactic simulators created with T&D-Bench can be employed by freshmen or by students that need only an overview of Computer Architecture subjects. The easy and rapid design process provided by T&DBench can be employed by seniors, by the instructor, or by students that will work on hardware design, to execute processor design space exploration, a contemporary and fundamental activity in embedded systems design. The characteristics of the T&D-Bench design methodology allow users to focus on the design process itself, instead of on the tool employed to execute the process. Later on, with the acquired design process skills, the student can learn the professional tools used in industry. T&D-Bench has been used in Computer Architecture education at Universidade de Caxias do Sul since 2003 with positive results reported by the students, both freshmen and seniors. T&D-Bench is free and available as an open source and platform-independent framework on the Internet, where simulation models of some didactic processors are ready to use. Future work with T&D-Bench includes the creation of new processor models and didactic simulators, the translation of the descriptions into a Hardware Description Language, thus creating a path to the physical prototyping of processors, and the use of the framework in a research project to investigate solutions for energy reduction in embedded processors. REFERENCES [1]
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