Development of Multi-Core Virtual Platform for Multimedia Applications JuneYoung Chang, NakWoong Eum Electronics and Telecommunications Research Institute (ETRI), Korea SoC Research & Development Group 161 gajeong-dong, Yuseong-gu, Daejeon, 305-350, Korea Tel: +82-42-860-6680, Fax: +82-42-860-6860 E-mail:
[email protected] Abstract Multi-core platform, which consists of 8~32 multimedia cores, is capable of verification and performance analysis of multimedia applications (MPEG-2, MPEG-4, AVS, H.264/AVC, VC-1). Virtual platform is a CLM(Cycle Accurate Model) platform integrating TLM(Transaction Level Model) and RTL IPs and provides performance analysis environment and cycle level verification to develop a variety of multimedia application. Multimedia applications are verified through multi-core RTL/CLM platform and performance comparison of platform is made through simulation time. As experimental result, it turns out that the simulation time of CLM platform is 6.7 times faster and that of RTL platform. Also, the simulation result of CIF 30~100 frame is provided to verify MPEG-2, MPEG-4, AVS, H.264/AVC and VC-1. Keywords: Multi-core platform, H.264, MPEG-4
1. Introduction Recent advance in multimedia technology requires high performance computing power and correspondingly there are high demands for processor performance. As yet, processor clock frequency improvement technique has been used to improve performance, but there were some restraints due to high heat over power-consuming or restrictions from making semi-conductor. To solve those problems, a multi-processor came upon the stage. A multiprocessor is a chip that has integrated certain number of processors. Multi-processor allows parallel processing, so user can implement high performance system with relatively low clock frequency. On multicore platform, software of multimedia application is easy to implement, design, and modify. Performance will boost up by using software parallelism and onchip interconnection architecture. Plenty of multimedia applications such as MPEG-2, MPEG-4, AVS, H.264/AVC and VC-1 use multi-core platform [1]. Multi-core virtual platforms are introduced to the
industry, which allow multi-core software development without a hardware prototype. Nevertheless, for developers in early design stage where no virtual platform is available, the software programming support is not satisfactory. Virtual Platforms have been introduced by companies like Platform Architect initially developed by CoWare and recently acquired by Synopsys [3] to enable software development before a hardware prototype is available. Together with high-level virtual platforms and real hardware platforms, today, developers can use three kinds of platforms to do software development. RTL(Register-Transfer-Level) platforms are the most traditional platforms for software development. However, their development is typically very timeconsuming. TLM (Transaction Level Model) platforms employ instruction-set simulators and provide software developers a binary compatible environment in which executable files for the target platform can be executed without modification. They are much easier to be built than hardware prototypes; hence they are more and more used today in order to let developers start software development early. CLM (Cycle Level Model) platforms do high-level simulation without much architecture information. They are often used by developers in early design stage, when architecture details are not fully determined [2]. Applications which are developed at high-level can hardly be directly reused on hardware target platforms. To close this gap, cycle-accurate IP model synthesis tools for virtual platform are proposed. Carbon Design Systems provides solutions to build cycle-accurate IP models for virtual platforms [4]. The generation of the IP models consists of compiling the IP’s RTL implementation into a high-speed software model. Multi-core virtual platform is a CLM platform integrating TLM and RTL IPs and provides performance analysis environment and cycle level verification to develop a variety of multimedia application. MPEG-2, MPEG-4, AVS, H.264/AVC and VC-1 are verified through multi-core RTL/CLM
platform and performance comparison is made through simulation time. Multi-core virtual RTL/CLM platform is explained in Section 2. Simulation environment of multi-core virtual platform are described in Section 3 and Section 4 draws conclusion.
2. Multi-Core Virtual Platform Multi-core virtual platform which consist of the 8 EMC (ETRI Multimedia Core), shared memory, flash memory, frame memory and connected to multi-layer AHB. 2.1 Multi-Core RTL Platform Multi-core RTL platform is a hardware platform which is only composed by RTL IPs. As Figure2, it is formed by EMC core, internal memory, cache, and external memory. EMC is a VLIW architecture which has a multimedia application specific processor. The data processed from EMC uses local memory and frame memory and communicate by multi-layer AHB bus. The 8 EMC will operate in parallel from multimedia application software which is designed in C language. It is possible to function level parallelism to each clusters based on the core level pipeline which is in each clusters.
architectures and to maintain the data coherence of hierarchical from multi-core. Buffer is formed by 2Kbyte dual port SRAM to make the data between cores to be shared in fast speed. For Video decoding TCM (Tightly Coupled Memory) and DMA (Direct Memory Access) is used to read and write the data from the frame memory in each core repeatedly. External memory provides SDRAM for video frame data and flash memory for multimedia application program/data and video input stream. EMC cluster communicates with external memory through multilayer AHB bus. 2.2 Multi-Core CLM Platform Multi-core CLM platform is designed with TLM component which is SRAM for flash memory, SDRAM for decoding video data and AHB bus for communication architecture. RTL IPs component is composed with EMC core and cache memory, DMA, local buffer memory and etc. To form CLM platform the RTL IPs is synthesized with Carbon Design Systems VSP (Virtual System Prototype) [4] and makes a Platform Architecture library.
(a)
AHB initiate transactor
(b) AHB target transactor Figure 3.AHB transactor
Figure 2.Multi-core RTL Platform Each multi cluster is possible to act data level parallelism [5]. Configurable structure is possible to require all sorts of applications to memory
TLM uses transaction level signal and RTL uses pin-level signal which will need a transactor to change the signals. CLM platform uses AHB which needs AHB initiate transactor and AHB target transactor. The TopSystem which is organized with RTL IPs and external memory such as flash memory and SDRAM are connected with AHB and through AHB transactor it changes the signals. As in Figure 3, when the TopSystem actions as a master in external memory the (a) AHB initiate transactor will be used. When it actions as slave (b) AHB target transactor will be used. Multi-core CLM platform (Figure 4) consists of Platform Architecture TLM library and CLM library which is synthesized RTL IPs. Using Carbon Design
Systems VSP it makes the EMC Cluster which is TopSystem CLM model by compiling RTL IPs (EMC core, cache memory, DMA, local buffer memory). The connection for EMC cluster and external memory is multi-layer AHB which uses PrimeCell library of Platform Architect [3].
3. Experimental Results The proposed simulation environment of multi-core virtual platform (Figure 5) has been realized by the Platform Architect in system-C level using Linux PC/3GHz. The EMCs have been designed by using Synopsys Processor Designer, and all the components such as memory model, bus interfaces frame cache and so on except EMCs are from the PrimeCell library [3]. Table 1.Simulation time of H.264/AVC (min)
Figure 4.Multi-core CLM platform To bring the data and program from flash memory to EMC cluster AHB target transactor is used. To send decoded video frame data to SDRAM AHB initiate transactor is used. Send data and program from flash memory to EMC clusters cache memory, and execute MPEG-2, MPEG-4, AVS, H.264/AVC and VC-1 decoder software which are multimedia applications from EMC core. The encoded video frame which is required in EMC cores decoding step are send from SDRAM to DMA which will finally go to EMC core. EMC core will decode video frame and store it to SDRAM by DMA.
Figure 5.Simulation environment of multi-core virtual platform
The software operated on each core is written in C language, and the executable made by lcc compiler derived from the Processor Designer. We compared simulation time of RTL and CLM platform by executing CIF (352x288) foreman I.P.P frame on H.264/AVC decoder. The result of RTL platform to verify CIF I.P.P frame took 529mins, and CLM platform took 79mins in simulation time. Table 2.Simulation time of Multi-format decoder
Multi-core CLM platform took 6.7 times faster than the RTL platform in simulation time. In the Multi-core CLM platform, CIF 30 ~ 100 frames was impossible to be verified because of the simulation time. By using CLM platform to reduce the simulation time it was possible to verify CIF 30 ~ 100 frame. Table 2 is the result of simulation time of decoding CIF (352x288) test sequence 30 frame through MPEG-2, MPEG-4, AVS, H.264/AVC, VC-1 from multi-core RTL/CLM
platform. For AVS it took 42.8 hours to verify a 30 frame tempete_cif image and for CLM platform it took 6.4 hours to verify it.
4. Conclusions The multi-core virtual platform is possible to simulate a high speed in CLM platform which is combined with TLM and RTL IPs and also possible to apply in hardware platforms. The simulation timeconsuming problem which occurred while proving multimedia applications of RTL platform has been solved. The experimental result has shown a 6.7times faster simulation time from CLM platform rather than RTL platform. CLM platform has solved the time limit which was caused when verifying CIF 30 ~ 100 frame. The simulation result of CIF 30 frame is provided to verify MPEG-2, MPEG-4, AVS, H.264/AVC and VC1.
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