Robert Chivas, Scott Silverman. Varioscale Incorporated, San Marcos, CA. Michael DiBattista. Qualcomm Incorporated, CDMA Technologies, San Diego, CA.
Adaptive Grinding and Polishing of Silicon Integrated Circuits to Ultra-thin Remaining Thickness Robert Chivas, Scott Silverman Varioscale Incorporated, San Marcos, CA Michael DiBattista Qualcomm Incorporated, CDMA Technologies, San Diego, CA ABSTRACT – Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.
Introduction Preparation of packaged integrated circuits for physical and electrical failure analysis often involves precise grinding and polishing of the thick silicon substrate from the backside. The silicon may be thinned uniformly to reduce optical attenuation in the near infrared or in order to localize a defect for more precise cross sectioning. If an imaging or probing technique uses a solid immersion lens (SIL) then the requirements for thickness accuracy, thickness uniformity and surface quality become quite stringent. Recent research has shown that ultra-thin preparation of silicon devices enables extensions of important, advanced analysis methods. By thinning a packaged silicon device to less than 5 um RST, magnetic current imaging with a GMR sensor was able to achieve detection of a peak with a lateral extent of 250 nm [1]. Laser voltage probing has been demonstrated at 633 nm when a SOI device is thinned to the buried oxide layer [2]. And near-field scanning optical microscopy (NSOM) has achieved a FWHM resolution of ~100 nm with up to 130 nm RST [3].
Figure 1 Surface profile of one die as it is thinned. The sag relaxes ~45 um from 70 um at full thickness to ~ 25 um when thinned to ~ 10 um RST.
Researchers have realized that analysis methods on ultra-thin silicon may in fact be much simpler to implement than those based on SIL; the burden, however, then shifts onto the sample preparation. Silicon die singulated from a wafer are typically very uniform in thickness and very flat; however, the die becomes stressed and bends when assembled into a package due to the coefficient of thermal expansion (CTE) mismatch between the silicon and the package materials [4]. The package stress depends on temperature and the curvature of the die depends on the stress distribution in the silicon and package materials. Even at a fixed temperature, the curvature of the die can change as the silicon is thinned primarily due to a rapid change in the bending strength [5]. Most grinding and polishing methods using a lapping process are well suited for planar surfaces but cause unacceptable nonuniformity on curved surfaces. For curved surfaces, computer numeric controlled (CNC) grinding and polishing machines perform better but require precise measurement of a three dimensional surface to maintain uniformity [6]. Since the shape of the silicon can change while processing, iterative measurements are needed. Measuring the top surface, however, may not be sufficient especially if the shape changes while processing. Instead, the best feedback is a measurement of thickness uniformity. In this work we present an adaptive grinding and polishing technique for preparation of silicon devices to ultra-thin remaining thickness (< 5 um) that incorporates in-situ measurement of thickness and flatness into a five-axis CNC machine. The CNC performs discrete measurements of the backside surface of the packaged die and the thickness uniformity of the silicon using a non-contact optical technique. Analysis software fits and filters the measurement data to construct a continuous, three dimensional (3D) model of the circuit layer. The CNC then thins the silicon by grinding to a target remaining silicon thickness (RST) referenced to the circuit layer. Additionally the 3D model is used to compute the surface normal of the five axis (i.e. X, Y, Z, tip and tilt) tool path which in turn maintains a constant tool bit contact angle. This five axis grinding results in minimal surface discontinuity which substantially reduces the time required to polish.
Adaptive 5-Axis Grinding for Backside Prep Large area packaged die are particularly curved because of the lateral extent of the CTE mismatch and typically are the most difficult to thin uniformly. A flip-chip device with an area of 272 mm2, for example, is bent as much as 70 um from center (apex) to corner at a thickness of 775 um. Since bending strength goes as the thickness3, these devices continually change shape as they are thinned which necessitates the adaptive 5-axis approach. Measuring and grinding iteratively using our CNC thins the silicon uniformly to 10 um while the die flattens to 25 um of sag. Figure 1 shows the in-situ, measured flatness of the die along a diagonal for each successive grinding pass.
Figure 2 Comparison of 3-axis vs 5-axis grinding. (Top) In 3axis the contact angle is invariant and cannot follow the shape of a bent die, producing “saw teeth” that are several um in size. (Bottom) 5-axis control changes the contact angle to follow the curved shape and yields a well-blended smooth and continuous surface profile.
applicable. We look at both measurement and sub-surface damage thrusts in this paper. Measurement One notable advantage of ultra-thin silicon is the substantial reduction of the light path attenuation to the circuit node. The attenuation is exponential and still considerable at nearinfrared wavelengths (i.e. above the intrinsic bandgap of silicon) due to doping of the substrate. Light with wavelength below bandgap (e.g. < 1000 nm) is attenuated even more such that the substrate must be only a few micrometers thick to practically transmit photons. For example, devices thinned to 10 um RST may be imaged with increased resolution at wavelengths down to 810 nm and devices at 5 um RST down to 780 nm [7]. At sub-micrometer RST, the lower limit of the wavelength used for imaging through silicon is probably only limited by the onset of direct-gap coupling in the near ultraviolet. At ~400 nm, there is an abrupt change in the index of refraction of intrinsic silicon (Figure 3 [8]). Whereas reflectivity of silicon in the near infrared is 30%, at 400 nm it increases to 48%, and at 370 nm to 58%, peaking at 73% at 270 nm. Similarly the absorption coefficient increases a decade from 9.5/um at 400 nm to 100/um at 360 nm [9]. The optimal wavelength used to obtain best resolution is suggested to depend on a trade-off of absorption and optical spot size [10]. At < 5 um RST, transmission down to 400 nm should be practical for bulk silicon devices. Combining a visible range grating spectrometer with a near infrared tunable laser spectrophotometer enables large bandwidth for ultra-thin measurements as well as large coherence for thick measurements. When the sample is thick, doped and rough, the well-established and robust long coherence measurement method may be used down to 5 um RST. Repeatability of these thick measurements is better than 100 nm. Improved Measurement of Ultra-thin Silicon
Three axis grinding has the limitation that the tool contact angle cannot be varied whereas five-axis can tip and tilt the device to keep the tool bottom normal to the surface. Polishing can also be performed in five axes improving the uniformity of the pad contact area and maintaining more consistent removal at the corners and edges. 5-Axis grinding rotates the die such that the grinding bit matches the surface normal at all points on the die. Figure 2 shows the resulting surface nonuniformity of 3-axis grinding (Top) compared the wellblended surface with 5-axis grinding (Bottom).
Ultra-thin Silicon Preparation Challenges The primary challenges for routine preparation to < 5 um RST are the current limitation in the measurement and process methods below 5 um RST. Although grinding may continue to scale, subsurface damage is the ultimate limit to how far the grind can go. Once a sample has been thinned below 5 um, measurement of its thickness with IR methods is no longer
Figure 3 Change in the index of refraction of silicon in the near UV (red real, blue imaginary) We have integrated a VIS light (500 – 1100 nm) grating spectrometer into the 5-axis measurement platform to extend the limit of RST that can be measured. From full thickness
down to 5 um the IR long coherence spectrometer measures thickness using reflectance spectroscopy and PSD analysis. When the sample is thin and polished, the grating spectrometer has a large enough bandwidth to measure from 5 um down to 0.25 um using the same PSD analysis method. Repeatability on well-defined device structures should be better than 10 nm. Even thinner thickness may be measured using amplitude fitting of the visible spectrum (e.g. EMA, effective-medium approximation).
Processing Ultra-thin preparation from 5 um to < 5 um RST must consider removal of subsurface damage as well as reduce the thickness non-uniformity to below 5 um RST. The process approach proposed is to use polishing with dwell time that is modulated by a thickness error function generated from ultra-thin measurements made with the grating spectrometer. Subsurface Damage The process challenge of achieving ultrathin RST is primarily overcoming or compensating for the surface dependency of polishing. Although grinding may continue to scale, subsurface damage and final optical quality surface are less likely to achieve results comparable to polishing. In this work we investigate the limit of circuit layer proximity by grinding due to subsurface damage with TEM direct imaging on bulk silicon before processing devices. Bulk silicon was ground with an 8um and 2 um grit covered bit and compared. The subsurface damage limit of 8 and 2 um diamond grit samples are measured by TEM. An 8u grit surface showed subsurface fracture damage ~ 1 um and generated an amorphous layer ~ 110 – 170 nm. The 2 um grit sample showed ~ 0.5 um subsurface damage, Figure 5, and amorphous layer ~ 50 nm. While some variance between individual data points is expected, the takeaway is that the grind damage is less than grit size, it scales with grit size, and is much less than industry accepted norms.
Figure 4 (Top) VIS grating spectrometer measuring ~ 2 um thickness of Si on an active device showing PSD modulation down to wavelength 500 nm, (Bottom) modulation and measurement of spin resist layer for comparison. A spin resist measurement, Figure 4 (Bottom), shows the idealized response of the VIS spectrometer demonstrating full bandwidth modulation from 500 – 1100 um measuring a 3 um layer. Figure 4 (Top) shows similar modulation down to ~ 600 nm measuring 2 um of Si on an active device with an approximated index of refraction of 4.5. In this example, PSD modulation exists down to 500 nm, but is noisy and reduced by absorption and scattering loss.
Figure 5 TEM cross-section image of Silicon that has been ground with a (Left) 2 um grit fixed abrasive showing ~ 0.5um damage layer and (Right) 8 um grit fixed abrasive with ~ 1um sub-surface damage.
Historically, a rule-of-thumb in the industry is that top down grinding and polishing imparts damage on the order of 3x the grit size. We believe that our approach of side grinding greatly reduces the load placed on the device which yields significantly less subsurface damage. This reduces the amount of material removal required by polishing and the number of steps required to achieve it.
At this level we are in the range where thickness is on the order of uniformity and polishing can be used as a fine shaping tool. The process approach proposed is to use polishing with dwell time that is modulated by a thickness error function generated from ultra-thin measurements made with the grating spectrometer. Table 1 depicts the considerations and steps involved to achieve < 5 um RST.
Therefore, the approach to achieving ultra-thin RST is not limited by subsurface damage imparted with grinding even down to a conservative RST of 3 um with range +/- 1 um. At 3 um RST the approach is limited by stopping accuracy and thickness uniformity.
Using a conservative surface roughness of 500 nm, and experimentally derived removal rate of 0.3 um/polish a recipe may look like the following:
We have found that the traditional industry multi-step-down slurry polishing process becomes unnecessary when adaptive grinding is used for preparation. By using a fine grit fixed abrasive bit, the initial surface roughness is in the 100’s of nm. The process recipe concludes with a modified CMP process that inherently produces no silicon damage. The reactive slurry process is modulated to reduce thickness variation and designed to remove the last 0.5 – 1.0 um of damaged material from grinding.
Min (um)
Max (um)
2.0
4.0
Grind to target RST of 3.0 um and expect range of 2 um (+/- 1 um)
1.7
3.7
Perform a cleanup pass that removes 0.3 um globally to prep for VIS survey
1.4
2.9
Modulated polish that dilates the dwell time a factor of 0.8/0.3 to increase uniformity
1.1
2.6
A final global polish can be used to blend any surface artifacts and remove another 0.3 um
Figure 6 shows the TEM cross section of a sample that was ground with 2 um fixed grit bit, then polished with SiO2 reactive slurry directly. The global removal from polishing was 1.2 um. It is clear that this removed any subsurface damage from grinding and did not impart any of its own damage. Furthermore, the polished cross section shows an amorphous layer 45 – 50 nm, which is comparable to the 2 um grit grinding data. Modulated polishing Once confirming that the sub-surface damage propagates < 1 um due to the side grinding approach, we can transfer the burden of final thickness almost entirely to the grinding phase. Material removal from polishing only needs ~ 1 um to get well under any damage. This reduces processing time by many multiples.
Table 1 Example of a modulated polishing approach Process
Running 1x reduces uniformity to 1.5 um total range and the mean would be ~ 2 um. Iteration propagates the result to desired RST. Experimentally, we would observe data sets where the mean shifts lower and distribution narrows while the maximum was reduced, but the minimum remained the same, or close to it.
Experimental We used a Qualcomm Test Package with die size 11x11 mm starting at full thickness (775 um). 5-axis adaptive grind was performed to the target RST of 5 um. Global and modulated polish were performed to a target RST of 3 um. A commercial grade VarioMill was used for grinding and polishing. The VIS spectrometer and light source are ThorLabs (SLS201/M tungsten light source, CCS175/M grating spectrometer)
Results Test Package The process grind was stopped at ~ 5 um where polishing to 3 um commenced. The as-ground mean was 4.85 um with a range of 3.5 um (2.2 – 5.7 um), standard deviation 0.4544 (Figure 7 blue histogram and distribution). Modulated polishing resulted in a mean of 4.1 um with a range of 3.1 um (2.0 – 5.1 um), standard deviation 0.3578 (Figure 7 orange histogram and distribution).
Figure 6 SiO2 polished sample with 1.2 um removed. TEM cross section showing no subsurface fracture defects.
This was an intermediate result but it suffices to show that we are following the model of effectively removing more material where it is thicker. The removal delta is 0.2 in thin areas and 0.6 in thicker. Thus the mean has shifted by 0.75 um and narrowed as predicted.
A microscope image shows that the surface is smooth and free of tool marks and other defects. There is also a dimple pattern (Figure 9)
Figure 7 Modulated polish result showing a mean reduction of 0.75 um. The thinner areas removed 0.2 um and the thicker reduced by 0.6 um After several iterations the final result yielded: Mean 3.2 um, Range 1.6 um (+/- 0.8 um) while curvature of ~ 16 um was maintained (Figure 8).
Figure 9 Surface image of test package polished to 3 um RST with range 1.6 (+/- 0.8) showing C4 stress induced dimpling At ultra-thin RST, the Si deforms due to the stress from the C4 ball grid. Active Device The established method was also applied to an active device to be used for VIS LVP. We achieved global RST 5.1 um (+/0.7 um) (Figure 10).
Figure 10 Global RST 5.1 um (+/- 0.7 um) on active device The device was prepared for Laser Voltage Probing which is described in other work. However, the result is that the device was electrically alive and able to perform the intended testing.
Conclusion Figure 8 (Top) Final thickness mean 3.2 um, range 1.6 (+/0.8um) (Bottom) Curvature of ~ 16 um maintained throughout grind and polish
We have looked at the practical limitations of global backside preparation to ultra-thin RST. The main limiting factors are sub-surface damage imposed by grinding/polishing and the ability to measure Si < 5 um thick. By integrating a VIS light grating spectrometer into the standard VarioMill measurement systems we demonstrate the ability to measure silicon from
775 um to 0.25 um using the PSD analysis method currently employed in the tool.
on a Contour-Milled Globally Ultrathin Die. 2014 ISTFA, pp. 23-27.
In this work we have shown that our method of side grinding imparts minimal damage that scales with grind bit grit size. At 8 um grit the damage propagates ~ 1 um and using the 2 um grit bit it is ~ 0.5 um. A modulated polishing scheme has been developed where only ~ 1 – 1.5 um of material removal by polishing is required - without stepping down through multiple slurries - significantly decreasing processing time.
[2] Beutler, J., & Clement, J. J. (n.d.). Visible Light LVP on Ultra-Thinned Substrates. 2014 ISTFA, pp. 110114.
Thus, our approach to ultra-thin RST shifts the burden of final thickness to the grinding by using the finer grit bits. The process only requires one step of polishing with reactive slurry for adequate removal of damaged material in proximity to the circuit layer. Combined with a new measurement system backside silicon prep to ultra-thin levels (< 5 um - 1 um RST) is achievable and practical. On a Qualcomm test package we validated the approach which we thinned globally to 3.2 um with a range of 1.6 (+/- 0.8 um). On an active device we achieved global RST of 5.1 um (+/0.7 um) which was determined to be electrically alive and a good candidate for VIS LVP.
Acknowledgments The authors would like to thank Scott Vorreyer and Tom Harper at Varioscale for contributions to sample prep and Don Lyons at Qualcomm for TEM measurements. Additional relevant work is presented by Joshua Beutler, et al ISTFA 2015.
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