Qualcomm Incorporated, CDMA Technologies, San Diego, CA. * current affiliation, Bosch Automotive, Germany. Abstract. Anticipating the end of life for IR-based ...
Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits down to 1 um Remaining Silicon Thickness Robert Chivas, Scott Silverman Varioscale Incorporated, San Marcos, CA Michael DiBattista, Ulrike Kindereit* Qualcomm Incorporated, CDMA Technologies, San Diego, CA * current affiliation, Bosch Automotive, Germany
Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultrathin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.
advanced analysis methods. By thinning a packaged silicon device to less than 5 um RST, magnetic current imaging with a giant magnetoresistance (GMR) sensor was able to achieve detection of a peak with a lateral extent of 250 nm [3]. LVP has been demonstrated at 633 nm when a silicon on insulator (SOI) device is thinned to the buried oxide layer [4]. And near-field scanning optical microscopy (NSOM) has achieved a full with half maximum (FWHM) resolution of ~100 nm with up to 130 nm remaining silicon thickness (RST). [5] Researchers have realized that analysis methods on ultra-thin silicon may in fact be much simpler to implement; the burden, however, then shifts onto the sample preparation.
Introduction Preparation of packaged integrated circuits for physical and electrical failure analysis often involves precise grinding and polishing of the thick silicon substrate from the backside to enable advanced failure analysis techniques for fault isolation and FIB based circuit modification. The silicon is required to be thinned uniformly to reduce optical attenuation in the near infrared or in order to localize a defect for more precise cross sectioning. Challenges are mounting to continue using Laser Voltage Probing (LVP) as a primary tool in the failure analyst’s toolbox [1]. If an imaging or probing technique uses a solid immersion lens (SIL) then the requirements for thickness accuracy, thickness uniformity and surface quality become quite stringent. Recently, emphasis has been placed on using optical failure analysis techniques such as LVP and dynamic laser stimulation (DLS) at shorter wavelengths into the visible range. Due to silicon’s inherent absorption properties, this requires thinning a device < 5 um. (Figure 1, [2])
Figure 1 Absorption of light through silicon as a function of wavelength. For visible wavelength (VIS) imaging, the absorption depth is ~ 1 um at 500 nm and ~ 10 um at 700 nm. In order to use visible light laser voltage probing (VIS-LVP) successfully, silicon must be thinned to < 5 um at 700 nm or < 0.5 um at 400 nm to account for 2 passes in a round trip, while keeping the circuit under test functional.
It has long been thought that the scanning wavelength needs to stay below Si band gap energy (1.11 eV) i.e. longer than 1117 nm, to avoid electron-hole pair generation that will invariably affect the test circuit. However, as device features continue to shrink below 10 nm technology node, the limited resolution at longer wavelengths has put the idea back into consideration.
Local thinning methods have been used to demonstrate the feasibility of this approach and VIS-LVP has been successfully demonstrated on bulk silicon devices. [6] In that work, a device was globally prepped to 5 um RST using adaptive 5axis computer numerical control (CNC) grinding and polishing tool, and the region of interest for probing was etched by reactive ion plasma to 1 um locally.
Recent published research has shown that ultra-thin preparation of silicon devices enables extensions of important,
Recently, work has been done to investigate the physical invasiveness of grinding and polishing ultra-thin. By using an
adaptive 5-axis CNC grinding and polishing tool, it was shown that the side-grinding method employed minimizes subsurface damage to < 0.5 um, enabling the proliferation of this method. as a viable means for preparing devices to ultra-thin thicknesses. [7]
In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um) remaining thickness is presented.
Discussion
Experimental
The ability to achieve micron level precision and uniformity provides advancements with current technology as well as enables disruptive advanced concepts.
The Device Under Test (DUT) was provided by QTI that is an advanced 16 nm finfet test chip, flip chip land grid array (LGA) pad type with die size 9.25 x 9.25 surrounded by epoxy that is 15 x 15 mm. The sample preparation tool was a commercial grade VarioMill from Varioscale, Inc that includes visible wavelength spectroscopy for measuring the thickness of silicon when it is < 5 um.
Traditional IR prep The evolution of the solid immersion lens for optical fault isolation (FI) tools allowed the extension of IR based laser systems. As the SIL lenses push to higher NAs, to achieve higher resolutions, the depth of focus becomes very narrow. Since it is a fixed focal length lens, the thickness of the silicon defines the focus distance. Large variations in the silicon thickness result in areas of the device to be out of focus.
Device Architecture The CAD layout is used as a guide to locate the region of interest above the oscillator rings.
As a result of the high precision and thickness uniformity tolerances achievable with the VarioMill prepared samples, the optical FI tool manufacturers could now push to very very high NA lenses that were not practical before because of real limitations of manually polished samples (Figure 2).
Figure 2 Cartoon showing how the increasing NA of immersion lens technology reduces the depth of field putting higher demand on surface prep to enable these advanced techniques. Visible Light Reducing the wavelength is a key enabler to increasing the resolution of the image, and influencing/measuring the device performance. The ability to reliably and reproducibly thin down to 2-3ums of RST enables a 2X increase in resolution and the ability to use a very high NA SIL (> 3.2) with a limited depth of field. With the physical invasiveness having been established in recent work, the extent of electrical invasiveness of the ultrathinning process is investigated. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to the aforementioned electron-hole pair generation.
Figure 3 (Top) CAD layout of test device highlighting Ring Oscillators. The ring oscillators are found in a space approximately 640 x 700 um square, on the left hand side of the die. The Region of Interest (ROI) Center is (-3900, 625) and a measurement extent of 1000 um is routinely used. The CAD layout for the DUT is shown in (Figure 3, Top). A device thinned and polished to 3 um RST was imaged with typical white lamp light (Bottom) and clearly shows the reported position of the Region of Interest (ROI) in the CAD layout. AT 3 um RST the silicon is transparent to visible light and imaged directly in an optical microscope.
The second focus was to drive the global RST as low as possible while maintaining functionality to gain confidence that an approach to 1 um would be feasible.
Figure 3 (Bottom) Visible light image through silicon prepped to 2 um RST showing the rings in their place.
Prep Challenges A particular challenge to the prep is that the encapsulated epoxy is highly scattering/absorbing and rough, making an initial survey difficult. There is no a priori information about the shape of the Si underneath, so the first cut to the Si is blind. There is ~ 850 um of epoxy on top of a die that is only 87 um thick. The epoxy thickness is not critically regulated, so sometimes the margin of error for epoxy thickness is larger than the die thickness. As it turns out, the epoxy layer is concave (bowed inward) which is contrary to the expected CTE mismatch of silicon and package. Once the die is exposed, the resulting Airgap and Thickness measurement superposition shows a circuit layer that is also concave (Figure 4). Additionally, the chip is mounted on a flat top socket (FTS) test board which is non-trivial to mount rigidly without wax to ensure none of the pins underneath get crushed. Therefore, the source of the concavity could be from the stress of mounting the device into the test board where the stiffness of the board wins over the epoxy and silicon. Experimental Goals The first focus was to observe the ring oscillator performance at each step along the process path to eliminate any vulnerabilities. For this we observe the output at: initial thickness, after grinding to global ~ 5 um RST, after an initial polish < 5 um, and again after a final polish at 4 um RST.
Figure 4 (Top) Airgap only data showing epoxy encapsulant is concave (bowed inward). (Bottom) once die is exposed the AG + T representation of the circuit layer is still concave. The final thrust was to explore the option of keeping the global RST reasonably thick (~ 4 um) while achieving 1 um RST in the ROI above the oscillator rings.
Results The observable is output frequency of 4 ring oscillators. We first investigated the oscillator at each step: as-ground to target, intial polish, final polish. Next we investigated the frequency output versus global RST from 10 um down to 3 um. Finally, we performed a localized polish above the rings to 1 um RST, maintaining a global RST of 4 um. Step by Step inspection At each step of the process we stopped to ensure that the rings were working. If there were any failures, we would know where in the process to start looking. After grinding to a target of slightly thicker than 5 um, the device was removed from the tool and tested, then again after the first set polishing passes. A final assessment was performed after final polish to target of 4 um and all were compared ( Table 1)
Table 1 Ring Oscillator frequencies measured at various points along the ultra-thinning process Process Step Initial As Ground In situ Polish Final Polish
Ring 1 MHz +/0.1 5.7
Ring 2
Ring 3
Ring 4
5.7
10.0
10.7
5.7
5.7
10.0
10.7
5.6
5.6
9.8
10.4
5.6
5.6
9.9
10.5
In Situ polish result
Global RST (um) +/87 +/- 0.5 6.0 +/- 1.1 4.7 +/- 1.5 4.0 +/- 1.9
The frequency reading from the board was validated using an oscilloscope and no deviation between the two occurred to 100 kHz. The results have not been normalized to temperature or temperature controlled, therefore signal fluctuation existed in the range of 100 kHz. Rings 3 and 4 were approximately doubled in frequency from 1 and 2. This ratio persisted throughout the ultra-thinning process. At each step along the way to 4 um the rings tested the same as the initial case within the margin of error (0.1 MHz). As-Ground final thickness
Figure 6 Mid-polish thickness map showing a mean of 4.7 um with a range of 2.9 um Polishing commenced with an automated exchange to polishing bit. One set of 10 passes was completed using SiO2 50 nm reactive (pH= 9.5) slurry. Mean: 4.7, Range: 2.9 um Frequency 1, 2, 3, 4: 5.6 MHz, 5.6, 9.8, 10.4 Final Polish Result
Figure 5 As-ground thickness map showing a mean of 6.0 um with range 2.3 um Grinding proceeded from an initial thickness of ~ 86 um to a target of 5 um. The total time from alignment to completion is 2 hours. Once the ring frequencies were recorded the sample was placed back in the tool for polishing. Mean: 6.0, Range: 2.3 Frequency of rings 1, 2, 3, 4: 5.7 MHz, 5.7, 10.0, 10.7
Figure 7 Final polished thickness map and histogram showing mean of 4.0 um and range of 3.8 um ( ~ 2.5 removing outliers)
A second set of 10 polishing passes was completed and the sample was considered done at 4 um. In the center of the ROI, a single point measurement measured 3.5 um. Mean: 4.0, Range: 3.8 (2.2 – 6.0). T above ROI: 3.5 um Frequency 1, 2, 3, 4: 5.6 MHz, 5.6, 9.9, 10.5
ROI at 1 um RST
Global thickness Approaching 1 um
Figure 9 (Top) Thickness map of die showing 2 ROIs thinned down to approximately 1 um. (Bottom) histogram of ROI showing local mean 1.0 um with range 1.5 (+/- 0.75).
Figure 8 Global RST 3.2 um +/- 1.4 with measured ROI thickness = 2.7 um Next, a step-down to 1 um was considered with the goal of achieving between 2 – 3 um RST globally and in the ROI. The final result was a global RST of 3.2 +/- 1.4 um and the center of the ROI measured 2.7 um (Figure 8). Table 2 Oscillator performance unperturbed when global RST ~ 3 um, ROI = 2.7 um.
Initial Final
Ring 1 MHz +/- 0.1 31.6 31.5
Ring 2
Ring 3
Ring 4
31.9 31.9
62.0 62.0
61.6 61.6
Table 3 Chart showing that final frequency output of the ring oscillator does not shift even at 1 um RST in the ROI.
Initial Final
Ring 1 MHz +/- 0.1 5.7 5.7
Ring 2
Ring 3
Ring 4
5.7 5.8
10.0 10.1
10.7 10.8
After final polishing, the oscillators were still functional and the recorded frequency was the same as initial within the error of measurement, +/-100 kHz.
Conclusion
The ring oscillators were completely unperturbed when a global RST of 3 um was achieved ( Table 2) With confidence, then, we proceeded to attempt ROI thickness of 1 um. A global thickness of ~ 4 um was achieved and 2 ROI areas identified for polishing. The ring oscillators are located in the leftmost ROI. Local polishing achieved an average of 1 um RST above the rings (+/- 0.75 um).
Adaptive 5-axis CNC grinding and polishing of backside silicon to ultra-thin (< 5 um) remaining silicon can be achieved and the impact to electrical performance of a bank of ring oscillators observed. Grinding to ultra-thin remaining thicknesses does not appear to perturb the ring oscillation frequency beyond the error range of the initial values. Final frequencies were within the error of measurement to the initial thickness values. Therefore, the conclusion is that ultrathinning to < 5 um has negligible electrical invasiveness on this test device.
This work demonstrates that it is possible to create functional ultrathin bulk silicon devices that can be used to enable numerous advanced fault isolation and FIB debug techniques. The benefits of this work paves the way for ultra-thin grinding and polishing to be demonstrated as a method of preparation for visible light voltage probing and other techniques where ultra-thin remaining silicon is considered an advantage for advanced silicon process technology nodes.
References [1] Kindereit, U, Fundamentals and Future Applications of Laser Voltage Probing, 2014 International Reliability Physics Symposium (IRPS 2014), 1-5 June 2014, Waikoloa, HI, ISBN:978-1-4799-3317-4, 3F.1.1-11 [2] Green, M. A., & Keevers, M. J. (1995). Optical properties of intrinsic silicon at 300 K. Progress in Photovoltaics: Research and Applications, 3, 189192. [3] Vallett, D., Gaudestad, J., & al., e. (n.d.). HighResolution Backside GMR Magnetic Current Imaging
on a Contour-Milled Globally Ultra-thin Die. 2014 ISTFA, pp. 23-27. [4] Beutler, J., & Clement, J. J. (n.d.). Visible Light LVP on Ultra-Thinned Substrates. 2014 ISTFA, pp. 110114. [5] Giridharagopal, R., Eiles, T. M., & Niu, B. (n.d.). Near-Field Scanning Optical Microscopy for Through-Silicon Imaging and Fault Isolation of Integrated Circuits. 2014 ISTFA, pp. 308-312. [6] Beutler, J; Hodges, C; Clement, J; Stevens, J; Cole, E; Chivas, R; Silverman, S; Visible Light LVP on Bulk Silicon Devices, ISTFA 2015 Proceedings from the 41st International Symposium for Testing and Failure Analysis, ISBN: 978-1-62708-102-3, Portland, OR, Nov 2015 [7] Chivas, R; Silverman, S; DiBattista, M; Adaptive Grinding and Polishing of Silicon Integrated Circuits to Ultra-thin Remaining Thickness, ISTFA 2015 Proceedings from the 41st International Symposium for Testing and Failure Analysis, ISBN: 978-162708-102-3, Portland, OR, Nov 2015
