Electrical linewidth test structures patterned in - IEEE Xplore

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Electrical Linewidth Test Structures Patterned in (100) Silicon-on-Insulator for Use as CD Standards M. W. Cresswell, Fellow, IEEE, John E. Bonevich, Richard A. Allen, Member, IEEE, Nadine M. P. Guillaume, Lucille A. Giannuzzi, Sarah C. Everist, Christine E. Murabito, Patrick J. Shea, and Loren W. Linholm, Fellow, IEEE

Abstract—Electrical test structures known as cross-bridge resistors have been patterned in (100) epitaxial silicon material that was grown on Bonded and Etched-back Silicon-On-Insulator (BESOI) substrates. The critical dimensions (CDs) of a selection of their reference segments have been measured electrically, by scanning-electron microscopy (SEM), and by lattice-plane counting. The lattice-plane counting is performed on phase-contrast images of the cross sections of the reference segments that are produced by highresolution transmission-electron microscopy (HRTEM). The reference-segment features were aligned with 110 directions in the BESOI surface material. They were defined by a silicon micromachining process that resulted in their sidewalls being nearly atomically planar and smooth and inclined at 54.737 to the surface (100) plane of the substrate. SEM, HRTEM, and electrical CD (ECD) linewidth measurements have been made on features of various drawn dimensions on the same substrate to investigate the feasibility of a CD traceability path that combines the low cost, robustness, and repeatability of ECD metrology and the absolute measurement of the HRTEM lattice-plane counting technique. Other novel aspects of the (100) silicon-on-insulator (SOI) implementation that are reported here are the ECD test-structure architecture and the making of lattice-plane counts from cross-sectional HRTEM imaging of the reference features. This paper describes the design details and the fabrication of the cross-bridge resistor test structure. The long-term goal is to develop a technique for the determination of the absolute dimensions of the trapezoidal cross sections of the cross-bridge resistors’ reference segments, as a prelude to making them available for dimensional reference applications.

Fig. 1. Lattice vectors pertinent to the (110) SOI implementation.

Index Terms—BESOI, cross-bridge resistor, electrical CD, HRTEM, linewidth, SEM, silicon micromachining, silicon-on-insulator, standards, traceability. Fig. 2. SEM image of feature cross sections characteristic of the (110) implementation. The silicon–nitride hard-mask caps had not been removed from the features when this image was recorded. Manuscript received October 19, 2000; revised May 19, 2001. Wafer processing for this research was conducted partially at Sandia National Laboratories, a multiprogram laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the United States Department of Energy, under Contract DE-AC04-94AL85000. The Sandia effort is specifically being supported through the Sandia/SEMATECH Cooperative Research and Development Agreement (CRADA) 1082. This work was supported in part by the National Semiconductor Metrology Program at NIST. M. W. Cresswell, J. E. Bonevich, R. A. Allen, C. E. Murabito, and L. W. Linholm are with Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, MD 20899 USA (e-mail:[email protected]; [email protected]; [email protected]; [email protected]; [email protected]). N. M. P. Guillaume is with the National Institute of Standards and Technology, Gaithersburg, MD 20899 USA and with George Washington University, Washington, DC 20052 USA (e-mail: [email protected]). L. A. Giannuzzi is with the University of Central Florida, Orlando, FL 32816 USA (e-mail: [email protected]). S. C. Everist and P. J. Shea are with the Sandia National Laboratories, Albuquerque, NM 87185 USA (e-mail: [email protected]; [email protected]). Publisher Item Identifier S 0894-6507(01)09766-4.

I. INTRODUCTION A. Relationship to Earlier Work

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ARLIER papers have described electrical linewidth test structures replicated in (110) SOI material referred to here as the “(110) implementation” [1]–[3]. In the (110) implementation, intersecting features are oriented along lattice 112 , directions and are designed to be inclined at 70.528 to one another, as illustrated in Fig. 1 [4]. Fig. 2 shows the cross sections of features of a (110) implementation that were obtained by potassium hydroxide etching of a bulk-silicon (110) surface. The vertical sidewalls are coincident with lattice 111 planes and generate high levels of contrast which may be used for the pitch calibration of electron-beam CD systems [5]. Fig. 3 contains a perspective image that shows the characteristic acute-corner facets that

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Fig. 3. SEM image of the vertical sidewall features characteristic of the (110) implementation.

Fig. 5. SEM image of line feature with trapezoidal cross-section characteristic of the (100) implementation.

purpose is to assess the repeatability and robustness of the new (100) implementation and its suitability for applying the proposed CD reference-material traceability strategy, as reviewed below. C. CD-Traceability Strategy

Fig. 4.

Lattice vectors of the (100) SOI implementation.

are formed by micromachining at the intersection of the features of the (110) implementation. However, in the case of the (100) implementation, intersecting features, such as bridge resistors and voltage taps, are orthogonal and are oriented to lattice 110 , directions, as illustrated in Fig. 4. Their sidewalls have slopes inclined at 54.737 to the surface (100) plane of the substrate. As in the case of the (110) implementation, feature delineation by silicon micromachining provides atomically smooth sidewalls that are coincident with lattice 111 planes. Fig. 5 is a perspective image that shows the characteristic, symmetrical, trapezoidal cross section of a feature of the (100) implementation. B. Purpose of the Current Work The purpose of the current work is to supplement the usefulness of vertical sidewall reference features of the (110) implementation with those having crystallographically defined sidewall slopes other than 90 . Such attributes may be of comparable value in metrology applications, such as instrument calibration, either when used alone, or when used in conjunction with those of the (110) implementation. For example, the nonorthogonal intersection of the sidewalls and top surfaces of the reference-segment features, shown schematically in Fig. 4, may address difficulties encountered with Atomic Force Microscopy (AFM) applications where probe-tip control at the sharp 90 corners of the sidewalls with the top surfaces can be challenging. The new (100) implementation also opens the possibility of developing traceable reference materials for step-height applications. However, the specific near-term

As in the case of the (110) implementation, the intention is to develop the dimensional traceability of (100) reference features through referencing the inherent accuracy of HRTEM imaging of the silicon lattice. HRTEM microscopy has been used successfully for accurate gate-CD and oxide-thickness measurements in special applications [6]. However, its cost and destructiveness render it impractical for lattice-plane imaging of the quantities of reference features that would be needed for distribution to end users for CD reference applications. The traceability strategy that is being developed by the authors of this paper is, therefore, after fabrication of wafers on which the cross-bridge resistor test structures are replicated, and after whole-wafer ECD test, to perform HRTEM imaging of a selection of reference segments at a selection of die sites. Lattice plane counts provided by this selection of HRTEM images are then used to express the ECD measurements of all reference segments on that wafer in terms of their absolute dimensions, as provided on a sample of HRTEM measurements [7]. In this way, the ECD measurements serve as a secondary reference that is calibrated effectively by the HRTEM measurements, which are the primary reference. Traceability of the linewidths to silicon lattice spacings is thereby imparted to all reference features whose ECDs have been measured. The strategic emphasis on electrical linewidth metrology as a secondary reference results from its unique robustness and repeatability, sometimes referred to as its precision. The key characteristic that is being sought is a useful level of correlation between electrical linewidth results and absolute measurements. Without calibration by HRTEM, or by some other means, electrical CD measurements have not yet been shown to be able to provide traceability with acceptable levels of uncertainty. A central issue that is being investigated in the work reported here is whether or not the traditional robustness and repeatability

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of electrical CD metrology that has been experienced with the (110) implementation extends to the (100) implementation.

sheet resistance, , and Kelvin measurements made on the reference feature, according to the relationship (1)

II. TECHNICAL APPROACH A. BESOI Starting Material The merits of Separation-by-IMplantation-with-OXygen (SIMOX) and BESOI silicon-on-insulator options for the subject application have been compared previously [8]. Each of these material options has shown that it provides physically uniform features with planar vertical sidewalls in the (110) implementation. While SIMOX material is relatively inexpensive, BESOI has advantages that include a user’s ability to specify a relatively arbitrary thickness of the surface film in which the cross-bridge resistors are patterned, and a more sharply defined interface to the buried oxide. Additionally, databases from which sheet the Kelvin-measurement resistance and reference-segment ECDs are extracted have been found to have less statistical variability in the case of BESOI materials than in the case of SIMOX materials. In the (110) implementation, it has been observed that ECDs extracted from cross-bridge resistors replicated in BESOI material are sometimes more consistent with the drawn CDs than those extracted from SIMOX wafers [8]. Because of the resulting metrology advantages, BESOI material was selected for this preliminary study of the (100) CD reference-material application. During the performance of the research being reported here, however, a new characteristic of the epitaxial BESOI device layer was discovered. The BESOI process involves bonding a device-layer silicon wafer to a standard (100) “handle” wafer. The device-layer silicon wafer, in the case of the (110) implementation, is normally available only with doping levels of approximately 10 cm . After bonding, the device-layer silicon is ground and thinned to approximately 100 Å thickness to serve as a seed layer for the growth of low resistivity epitaxial material having doping levels to several times 10 cm , typically to a height of approximately 1 m. The purpose of this process is to provide a surface-layer resistivity that is significantly lower than that of available (110) bulk wafer material. The same epitaxial regrowth process was used for the (100) material that was used for the measurements reported here. The actual arsenic doping cm . The belief concentration was approximately was that, during epitaxial silicon regrowth, the higher resistivity seed layer would become doped to the same low resistivity level as the regrown layer. In the earlier work with the (110) vertical-sidewall implementation, the outcome is inconsequential. However, it is described later in this paper that, in the case of the (100) implementation, there might be implications for the use of electrical CD metrology in the CD traceability path for features with their trapezoidal cross sections. The matter is discussed in further detail later. B. Electrical Linewidth Measurement The electrical linewidth, or ECD, of the reference segment , is obtained from of a cross-bridge-resistor test structure,

is the shortening of the reference-length, , due where to partial shunting of reference segment current through the voltage-tap junction that has been introduced and described measurepreviously [9], [10]. Statistical analyses of ment databases that are acquired from multiple multisegment cross-bridge resistor test structures, and based on (1), have benefits over this relationship’s local application, as described elsewhere [2]. C. Sheet-Resistance Metrology Issues A number of papers have followed a pioneering paper by van der Pauw [11] on the subject of sheet-resistance extraction by patterning and electrically testing four-terminal sheet resistors. These have compared the merits and complexities of using resistors of different planar geometries, that is, for example, those patterned in a film of uniform composition and thickness with vertical sidewalls on the entire perimeter [12]–[14]. In all cases, an estimate of sheet resistance is obtained through a sequence measurements.1 of Sheet resistance is typically the largest contributor to uncer, of the reference segment tainty in the measured ECD value, of the cross-bridge resistor. For planar structures, the value of needed for the estimation of from (1) is the same as that obtained by numerical solution of of the quantity (2) and are the respective complementary where current-force/voltage-read Kelvin measurements made on a local four-terminal sheet resistor. Such complementary measurements have been described in another paper [8]. In this context, planarity is the attribute of sheet resistors that are patterned in a film of uniform composition and thickness with vertical sidewalls on their entire perimeters. In the case of the (100) implementation, nonplanarity results from the slope of the sidewalls of the intersecting features forming the resistors. , the apparent sheet resistance, In this case, the value of as given by (2), is not generally the same as the value of needed for the estimation of from (1). that The approach to obtaining an appropriate value of was adopted here was to determine a correction factor, obtained by current-flow modeling, to apply to the apparent sheet resis, determined from the application of (2) to the set of tance, measurements extracted per normal practice from planar four-terminal sheet resistors [13]. Table I shows a selection of and obtained from current-flow modcomparisons of eling performed earlier for a vertical sidewall application [15]. The important thing to note in Table I is that the modeled results in the third column exceed the corresponding “actual” sheet resistance values in the second column. The reason is that apparent 1In this paper, the notation hV =I i means an average of a set of repeated V/I measurements made both in a forward and a reverse direction.

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TABLE I THE RELATIONSHIP BETWEEN APPARENT SHEET RESISTANCE, R , AND ACTUAL SHEET RESISTANCE, R , BASED ON THE RESULTS OF CURRENT MODELING FOR DIFFERENT VALUES OF THE WIDTHS OF THE TOPS OF THE INTERSECTING FEATURES CONSTITUTING THE FOUR-TERMINAL SHEET RESISTORS. IN ALL THREE CASES THE ACTUAL FILM SHEET RESISTANCE WAS 95.2 = AND THE HEIGHT OF ALL THE FEATURES WAS 1.07 m

Fig. 7. Test-structure module of (100) implementation which is patterned with seven different drawn linewidths ranging from 0.35 to 3.0 m on each die site.

Fig. 6. Results of R measurements made on a set of Greek-cross four-terminal sheet resistors that were tested at a particular die site showing impact of correction for finite tap widths.

Fig. 8. The test structure is patterned with seven different drawn reference-segment linewidths within a single test-structure module. Seven identical modules are replicated on each die site.

sheet resistance extraction assumes that all current flow is in a horizontal plane, which is not absolutely true. On the other hand, the “actual” sheet resistance values in Table I were oband meatained by application of (2) to modeled surements representing the actual, partially three-dimensional, current paths. The physical structures were four-terminal sheet resistors as replicated by the (100) implementation. When 5- m linewidths are used, for example, (2) generates sheet-resistance values that are too high, by approximately 0.9%, for insertion in . (1) for the estimation of A selection of results obtained by the application of a compensating 0.9% correction to measurements made on four-terminal sheet resistors patterned in the (100) implementation with 5- m CDs is shown in Fig. 6. The diminution of sheet resistance extracted from structures having the higher row numbers, that is, in this case, located further from the test-chip perimeter, is due to actual spatial variations of the film’s sheet resistance with the location of the respective test structures.

terned with seven different drawn reference-segment linewidths ranging from 0.35 to 3.0 m within a single module. Seven identical modules are replicated on each die site, as shown in Fig. 8. The “ ” structures terminating the voltage tap lines are etch stops that prevent lateral propagation of material removal from outside corners. The architecture of the cross-bridge resistor allows the reby three different methods. On the quired determination of one hand, this quantity may be determined from measurements of the width of the single, tapped, voltage tap in Fig. 7 in conjunction with an expression for it in terms of bridge and tap linewidths derived from current-flow modeling, as in the case of the (110) implementation [17]. On the other hand, applimay be extracted by comparing meacable values of surements made on segments of the bridge line having and not having dummy voltage taps, that is, those defined by the shorter vertical lines in Fig. 7 [18]. Finally, there is the approach of and ECD from measurements made on mulco-extracting tiple reference segments of different lengths [4]. This third approach was the one that was used for the work reported here. that Fig. 9 shows a comparison of the measured values of were co-extracted with ECD values of reference features of the test structure shown in Fig. 7, compared with the results of current-flow modeling. The close agreement between the measured and computed values in Fig. 9 is indicative of the functionality of the algorithm that was used for the co-extraction of both pameasurements. rameters from the set of

D. Cross-Bridge Resistor Test-Structure Design Fig. 7 shows a cross-bridge resistor test structure having 22 chained reference segments ranging in length from 7.45 to 45.0 m [16]. In the figure, the longer vertical lines are voltage taps whose intersections with the horizontal bridge line define the various reference segments of the latter and whose CD measurements are reported here. On the test chip, the bridge line is pat-

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Fig. 9. A comparison of the measured values of L co-extracted with ECD values of reference features of the test structure shown in Fig. 7 compared with the results of current-flow modeling for a fixed tap width of 1.0 m.

E. Test Structure Fabrication The BESOI wafers, which generated the feature shown in Fig. 5, were fabricated according to an established SOI micromachining process flow that has been reported previously [4]. An etch of 19% by weight of KOH in water at 80 C was used to define structures in bulk silicon material having 111 planar faces. The pattern to be transferred typically is replicated first in a 500-Å silicon-nitride hard mask. The buried BESOI oxide layer serves as an etch stop in a direction normal to the wafer surface. It allows over-etching of the order of 150%–200%, which is effective in clearing all remaining device-layer silicon not having an exposed 111 surface. An alternative etch is tetramethyl ammonium hydroxide. An appropriate hard mask in this case is silicon dioxide. In either case, the 111 planes of exposed silicon etch significantly slower than any others. Material surfaces remaining at the completion of an etch are those that are protected either by the in situ hard masking or by surfaces having one of the orientations of the 111 family, as illustrated previously in Fig. 2 and in Fig. 5. III. MEASUREMENT RESULTS A. Electrical CD Measurements An example of the electrical linewidth measurements obtained from module 5 on die-site (7, 3) of a 150-mm (100) BESOI wafer is shown in Fig. 10. When the electrical conductivity of the feature is uniform over its entire trapezoidal cross , should correspond to section, its measured electrical CD, its physical width at half its physical height. The corresponding , is then given by width of the top of the feature, (3) values where is the feature’s height. In Fig. 10, the measurements according to (3) are plotted obtained from against the corresponding drawn feature widths, which ideally should match one another. However, there is an average offset whereby the ECD values are approximately 150 nm less than the corresponding drawn values. The value of the height, , that was selected for use in (3) for the calculation of the top-surface electrical CDs shown in

Fig. 10. An example of the top-surface widths, computed from their known height and measured electrical CDs, as a function of drawn linewidths for a selection of structures [module 5 on die-site (7, 3)].

Fig. 10 was 1.075 m. The selection of this number, and the fact that there is an apparently significant offset between the drawn and electrically determined top-surface CDs, will be discussed after some HRTEM results are presented in the next section. B. HRTEM Imaging of Feature Having a Trapezoidal Cross Section To resolve the atomic lattice-plane fringes in the silicon feature using HRTEM imaging [19], a cross section of the feature must be thinned to approximately 20 nm. The following procedure was used to produce HRTEM specimens. The silicon features were first encapsulated with an epoxy and a glass cover slip to act as a transparent protective layer. Then the wafer was diced with a diamond wafering blade and subsequently mechanically polished with diamond slurries to 0.05 m finish. The second side of the cross section was likewise polished, but at a 6 angle to produce a wedge-shaped specimen suitable for mounting on a 3-mm copper slotted washer. The specimen was then thinned to 20 nm in an ion mill using 4-kV argon ions at 4 . Atomic scale observations were conducted in a 300-kV microscope with a point resolution of 0.17 nm. Micrographs of the cross section of a silicon feature in module 2, having a drawn linewidth of 0.5 m, at die site (2, 10) on the same wafer from which the measurements shown in Fig. 10 were extracted, and tilted to the [110] zone, were recorded at 150 kX so that the atomic lattice fringes were visible across the entire top (001) surface. This micrograph was then scanned at 2000 dpi to obtain a digital image suitable for analysis. Fig. 11 shows a large scale TEM image of the trapezoidal cross section of the feature. The insets show atomic scale resolution of the top (100) surface in the upper left and the ( 1 ) sidewall surface in the upper right. The (1 0) lattice fringes across the top surface were then counted to determine the absolute width of the silicon feature. The silicon (1 0) nm). lattice spacing corresponds to 0.3840 nm ( The (1 0) fringe count across the top of the feature was 1345, and thus the feature width is 516.52 nm. The height of the silicon feature was similarly measured to be 1074.9 nm. This figure determined the value of that was selected to compute the electrical top-surface CDs in Fig. 10 by use of (3). Close examination of the HRTEM micrographs in Fig. 11 reveals the silicon sidewalls have a surface roughness of approximately 2 atomic layers. The lack of a distinct boundary be-

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Fig. 12. The values of the top-surface CDs of the eight reference segments of module 5 of chip (7, 3), as determined from SEM measurements, compared to their values determined electrically. Fig. 11. Large-scale TEM image of the trapezoidal cross section of a feature with a drawn CD of 0.5 m in module 2 at die site (2, 10). The insets show atomic scale resolution of the top (001) surface in the upper left and the (111) sidewall surface in the upper right.

tween the silicon lattice and the encapsulating epoxy can introduce noise and obscure the high resolution image. These factors contribute to an uncertainty in the width and height measurements estimated to be approximately 0.77 nm. Specimens prepared by focused ion beam (FIB) techniques [20] with 30-kV gallium ions were also examined by 300-kV HRTEM. Micrographs of the 0.5- m-drawn silicon features were digitized as above for analysis. Although the (1 0) fringes were not discerned in these thicker specimens, the image of the silicon feature was calibrated so that its height corresponded to 1075 nm. The width of the feature was then measured to be approximately 464 nm. The uncertainties of these measurements are larger than those of the previous specimen. A conservative upper bound [21] is 2.50 nm. The top-surface electrical CD measurement for the feature shown in Fig. 11 was 0.386 m, which differs from its HRTEM measurement of 0.517 m by 131 nm. Since the difference is quite substantial, and close to the offset between the drawn and electrically measured top-surface CDs that were shown in Fig. 10, and since the HRTEM measurements may be considered absolute, the derivation of the electrical measurements, as described in Section III-A, becomes suspect. In order to throw some light on the offsets, the same features, whose electrical measurements were reported in Fig. 10, were cross sectioned and imaged by a conventional SEM. The results are reported in the next section. C. Comparison of Electrical and SEM Measurements The cross sections of the reference features, whose electrical CDs have been reported in Fig. 10 in Section III-A, were inspected by SEM. All eight images were acquired from the same test piece at the same magnification, and the 1- m magnification markers on all the images had the same actual length. In order to avoid reliance on the use of the markers, the magnification of each image was estimated from the assumed constancy of the film thickness and the known feature sidewall slopes. Specifically, the difference between the top and bottom imaged linewidths of a given feature is expressed uniquely in terms of the feature’s height, consistent with (3), and a common scaling

factor for the eight reference-feature images. A spread-sheet “Solver” function was used to minimize the sum of the squares of the differences between the scaled SEM-measured top widths and the drawn top widths of seven features with different drawn linewidths. In the minimization, the variables were the features’ height and a constant representing the amount of hard-mask undercut sustained during the patterning process. For the latter, the minimization process generated a value of 0.031 m, which is an amount typically experienced with the micromachining fabrication process. The values of the resulting top-surface CDs of the eight reference segments of module 5 of chip (7, 3), as determined from the cross-section-SEM measurements, are compared to their electrically determined values in Fig. 12. The average offset between the SEM value and the corresponding ECD value is 127 nm. As explained previously, the HRTEM measurements reported here were made on a different test chip from the same wafer. The height value that minimized the sum of the squares of the differences between the scaled CDs of the feature-top images and their corresponding drawn CDs was 1.092 m. This was consistent with measurements made with use of the SEM-generated marker to within 0.05%. The level of agreement between the SEM-determined value of the height, and the absolute value of 1.075 m determined by HRTEM on a neighboring die site, supports the validity of the minimization approach described above, although it is not being claimed here as universally valid. The less-than-2% difference between the extracted film height and the absolute measurement does not have any material impact on the conclusions being reached with regard to the negative offsets of the electrical measurements to both the HRTEM and the SEM measurements. The origin of both of the HRTEM and SEM measurement offsets from the “top” electrical CDs, which are more or less of the same extent, is being attributed provisionally to characteristics of the BESOI-silicon films from which the (100) crossbridge-resistor test structures were fabricated. In particular, Section II-A has mentioned how a layer of the BESOI film that is adjacent to the buried silicon dioxide could have a resistivity that is significantly higher than that of the upper part of the film. This higher resistivity layer would render the electrical height of the film different from its physical height, as recorded by HRTEM and SEM images. Initial measurements have in fact shown that the high-resistivity layer does indeed exist in starting material

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that was prepared at the same time as that used for the studies reported here. Whereas the result is, in principle, inconsequential for the vertical sidewall (110) implementation, it does have an effect in the (100) implementation because, in the case of the latter, it is from the electrical height and the electrical CD measurement that the top-surface CD is calculated, according to (3). In such cases, the top-surface electrical CD is commensurately lower than its physical CD unless a correction is provided for the lower, high-resistivity, layer.

ACKNOWLEDGMENT The authors acknowledge computer-aided drawing services provided by D. Renninger and C. Ellenwood. J. Martinez and D. Josell at NIST and J. Sniegowski at Sandia are thanked for technical reviews. J. Wilkes, K. Cresswell, and E. Secula are thanked for editorial reviews and related contributions. The authors acknowledge the FEI Company, and Micro Optics, Inc., for the use of their equipment.2 Solecon Laboratories, Inc. of San Jose, California, made spreading-resistance measurements. REFERENCES

IV. SUMMARY We have reported previously ECD measurements that were made on features having sub-micrometer linewidths and rectangular cross sections which were fabricated by micromachining SOI films. The purpose was to develop a means of determining the features’ absolute linewidths, with several nanometers uncertainty, with acceptable cost. In the longer term, their use as CD reference materials is being considered. Whereas their absolute cross-section dimensions were measurable through lattice-plane counting of HRTEM images, this technique is costly and destructive. A CD traceability-path combining the low cost, robustness, and repeatability of ECD metrology with the absolute dimensional metrology of lattice-plane counting appears to be economically feasible. This implementation involves ECD testing of all reference features on a wafer and selective HRTEM imaging of a subset of them. In effect, a limited number of HRTEM lattice-plane counts is thus used to calibrate the highprecision ECD measurements of all reference features on the wafer. The work reported here is an extension of the earlier work to reference features having trapezoidal cross sections with crystallographically-defined sidewall slopes for CD-reference and related applications. It involves a preliminary comparison of cross-section measurements of the trapezoidal features as made by SEM, electrical, and HRTEM methods and an investigation of the sources of the differences between the respective measurements sets. The cross-section dimensions of trapezoidal reference features embedded into electrical test structures were measured by the three metrology techniques specified above. The ECD of one feature that was measured with HRTEM was less than the HRTEM measurement by approximately 131 nm. ECD measurements of 7 features on a second test chip were systematically smaller than their SEM cross-section measurements by an average of 127 nm. The similar offsets of the electrical measurements from the SEM and HRTEM measurements were attributed to the existence of a layer of high-resistivity material in the active-layer silicon adjoining the buried oxide. While this high-resistivity layer would not impact ECD extraction from vertical-sidewall features, it results in an apparent narrowing of the ECD measurements in the case of trapezoidal sidewall features. In any event, the proposed traceability path is shown to be a viable approach since the effect of any constant offset between the ECD and HRTEM measurement-sets is provided for in the calibration process. Any desired further reduction of the offset through adjusting the active dopant species implant and anneal conditions is not a major materials-engineering challenge.

[1] R. A. Allen, P. M. Troccolo, J. C. Owen, III, J. E. Potzick, and L. W. Linholm, “Comparisons of measured linewidths of sub-micrometer lines using optical, electrical, and SEM metrologies,” SPIE—Integrated Circuit Metrology, Inspection,and Process Control VII, vol. 1926, pp. 34–43, 1993. [2] M. W. Cresswell, R. A. Allen, W. F. Guthrie, J. J. Sniegowski, R. N. Ghoshtagore, and L. W. Linholm, “Electrical linewidth test structures fabricated in mono-crystalline films for reference material applications,” IEEE Trans. Semiconduct. Manufact., vol. 11, pp. 182–193, May 1998. [3] M. W. Cresswell, R. N. Ghoshtagore, L. W. Linholm, R. A. Allen, and J. J. Sniegowski, “Mono-crystalline test structures, and use for calibrating instruments,” U.S. Patent Number: 5 684 301. [4] M. W. Cresswell, J. J. Sniegowski, R. N. Ghoshtagore, R. A. Allen, W. F. Guthrie, A. W. Gurnell, L. W. Linholm, R. G. Dixson, and E. C. Teague, “Recent developments in electrical linewidth and overlay metrology for integrated circuit fabrication processes,” Jpn. J. Appl. Phys., vol. 35, pp. 6597–6609, 1996. [5] Y. Nakayama and K. Toyoda, “New sub-micron dimension reference for electron-beam metrology system,” SPIE—Integrated Circuit Metrology, Inspection, and Process Control, vol. 2196, pp. 74–78, 1994. [6] G. Timp, A. Agarwal, F. H. Baumann, T. Boone, M. Buonanno, R. Cirelli, V. Donnelly, M. Foad, D. Grant, M. Green, H. Gossmann, S. Hillenius, J. Jackson, D. Jacobson, R. Kleiman, A. Kornblit, F. Klemens, J. T. C. Lee, W. Mansfield, S. Moccio, A. Murrell, M. O’Malley, J. Rosamilia, J. Sapjeta, P. Silverman, T. Sorsch, W. W. Tai, D. Tennant, H. Vuong, and B. Weir, “Low leakage, ultra-thin gate oxides for extremely high performance sub-100nm MOSFETS,” in IEDM Proc., 1997, pp. 930–933. [7] R. A. Allen, T. J. Headley, S. C. Everist, R. N. Ghoshtagore, M. W. Cresswell, and L. W. Linholm, “High-resolution transmission electron microscopy calibration of critical dimension (CD) reference materials,” IEEE Trans. Semiconduct. Manufact., vol. 14, pp. 26–31, Feb. 2001. [8] R. A. Allen, R. N. Ghoshtagore, M. W. Cresswell, L. W. Linholm, and J. J. Sniegowski, “Comparison of properties of electrical test structures patterned in BESOI and SIMOX films for CD reference material applications,” SPIE, vol. 3332, pp. 124–131, 1998. [9] R. A. Allen, M. W. Cresswell, and L. M. Buck, “A new test structure for the electrical measurement of the widths of short features with arbitrarily wide voltage taps,” IEEE Electron Device Lett., vol. 13, no. 6, pp. 322–324, 1992. [10] L. W. Linholm, R. A. Allen, and M. W. Cresswell, “Microelectronic test structures for feature-placement and electrical linewidth metrology,” in Handbook of Critical Dimension Metrology and Process Control, SPIE Critical Reviews of Optical Science and Technology, vol. CR52, 1993, pp. 91–118. [11] L. J. van der Pauw, “A method of measuring specific resistivity and Hall effect of discs of arbitrary shape,” Philips Res. Rep., vol. 13, no. 1, 1958. [12] J. M. David and M. G. Buehler, “A numerical analysis of various cross sheet resistor structures,” Solid-State Electron., vol. 20, pp. 539–543, 1977. [13] M. G. Buehler and W. R. Thurber, “An experimental study of various cross sheet resistor test structures,” J. Electrochem. Soc., vol. 25, no. 4, pp. 645–650, 1978.

2Certain commercial equipment, instruments, or materials are identified in this paper in order to specify adequately the experimental procedure. Such identification does not imply recommendation or endorsement by the National Institute of Standards and Technology, nor does it imply that the materials or equipment identified are necessarily the best available for the purpose.

CRESSWELL et al.: ELECTRICAL LINEWIDTH TEST STRUCTURES PATTERNED IN (100) SILICON-ON-INSULATOR FOR USE AS CD STANDARDS

[14] M. I. Newsam, A. J. Walton, and M. Fallon, “Numerical analysis of the effect of geometry on the performance of the Greek cross structure,” in Proc. IEEE Int. Conf. Microelectronic Test Structures (ICMTS 96), Mar. 19–21, 1996, pp. 35–38. [15] M. W. Cresswell, N. M. P. Guillaume, W. E. Lee, R. A. Allen, W. F. Guthrie, R. N. Ghoshtagore, Z. Osborne, N. Sullivan, and L. W. Linholm, “Extraction of sheet resistance from four-terminal sheet resistors replicated in mono-crystalline films with nonplanar geometries,” IEEE Trans. Semiconduct. Manufact., vol. 12, pp. 154–165, May 1999. [16] M. W. Cresswell, R. A. Allen, R. N. Ghoshtagore, N. M. P. Guillaume, P. J. Shea, S. C. Everist, and L. W. Linholm, “Characterization of electrical linewidth test structures patterned in (100) silicon-on-insulator for use as CD standards,” in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 13, Monterey, CA, Mar. 21–23, 2000. [17] W. E. Lee, W. F. Guthrie, M. W. Cresswell, R. A. Allen, J. J. Sniegowski, and L. W. Linholm, “Reference-length shortening by Kelvin voltage taps in linewidth test structures replicated in mono-crystalline silicon films,” in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 10, 1997, pp. 35–38. [18] M. W. Cresswell, J. J. Sniegowski, R. N. Ghoshtagore, R. A. Allen, W. F. Guthrie, and L. W. Linholm, “Electrical linewidth test structures fabricated in mono-crystalline silicon films for reference-material applications,” IEEE Trans. Semiconduct. Manufact., vol. 11, pp. 1–12, May 1998. [19] J. C. H. Spence, Experimental High-Resolution Electron Microscopy. New York: Oxford Univ. Press, 1988. [20] L. A. Giannuzzi, J. L. Drown, S. R. Brown, R. B. Irwin, and F. A. Stevie, “Focused ion beam milling and micro-manipulation lift-out for site specific cross-section TEM specimen preparation,” in Proc. Symp. Materials Res. Soc., vol. 480, 1997, p. 19. [21] B. N. Taylor and C. E. Kuyatt, “Guidelines for evaluating and expressing the uncertainty of NIST measurement results,” NIST Tech. Note, vol. 1297, 1994.

M. W. Cresswell (M’66–SM’96–F’01) received the Ph.D. degree in physics from the Pennsylvania State University, University Park, PA, and the MBA degree from the University of Pittsburgh, Pittsburgh, PA. He is a physicist in the IC Technology Group at the National Institute of Standards and Technology (NIST). He spent 19 years working in bipolar power-devices, flat panel displays, and IC-process development. At NIST, he is developing reference materials for nanometer-level metrology for submicrometer feature placement, linewidth, and overlay. He holds twenty-five patents in the field of semiconductor-fabrication technology. He is a member of the American Physical Society and a Fellow of the Institute of Electrical and Electronics Engineers.

John E. Bonevich received the Ph.D. degree in materials science and engineering from Northwestern University, Evanston, IL, in 1991 and the B.S.E. degree in materials science and engineering from University of Michigan, Ann Arbor, in 1986. From 1995 to 1998, he was a Metallurgist at the Metallurgy Division, National Institute of Standards and Technology, USA; from 1994 to 1995, he was a Postdoctoral Fellow at the National Center for Electron Microscopy, Lawrence Berkeley Laboratory, Berkeley, CA; and from 1991 to 1994, he was a Research Scientist at the Advanced Research Laboratory, Hitachi, Japan. His research interests are investigations of interfacial structure and chemistry of microelectronic interconnects, ferroelectric and optical materials, magnetic multilayer thin films, nanostructured materials, characterization of electromagnetic fields in GMR materials, electrodeposited nanowires, and superconductors. His expertise is in high-resolution and analytical transmission electron microscopy, electron holography, and image analysis.

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Richard A. Allen (M’85) received the B.S. and M.S. degrees, both in physics, from Rensselaer Polytechnic Institute, Troy, NY, in 1982 and 1984, respectively. He has worked at the Jet Propulsion Laboratory, Pasadena, CA, where he developed test structures for monitoring space radiation effects in the VLSI Technology Group and at College Park Software, Altadena, CA, where he worked on the development of LISP-based expert systems tools. Since June 1990, he has been with Integrated Circuits Technology Group of the National Institute of Standards and Technology, Gaithersburg, MD. His present interests include developing test structures for nanometer-level linewidth and overlay metrology. Mr. Allen is a member of the American Physical Society.

Nadine M. P. Guillaume received the M.S. degree in electrical engineering from Ecole Nationale Superieure d’Electronique, Electrotechnique, Hydraulique, Informatique, Toulouse, France, in 1998. She is currently working toward the Ph.D. degree in microelectronics and VLSI systems at the George Washington University, Washington, DC. She is a Guest Researcher in the IC Technology Group, National Institute of Standards and Technology (NIST), Gaithersburg, MD. At NIST, she is performing research in developing a novel sensor designed to enable noncontact linewidth metrology on substrates used for sub-micrometer metrology.

Lucille A. Giannuzzi received the B.E. degree in engineering science in 1985 and the M.S. degree in materials science and engineering in 1987, both from the State University of New York, Stony Brook, and the Ph.D. degree from The Pennsylvania State University, University Park, PA, in metals science and engineering in 1992. She is currently an Associate Professor, Mechanical Materials and Aerospace Engineering at the University of Central Florida, Orlando, FL. She developed an ongoing research and educational partnership in 1996 with Cirent Semiconductor (Lucent Technologies, Orlando, FL). This partnership resulted in the donation of nearly $10M in analytical equipment that is now housed at the UCF/Cirent Materials Characterization Facility, which she directs. She was a founding faculty member of the State appropriated Advanced Materials Processing and Analysis Center. She is a local affiliate speaker for the Microscopy Society of America and is also active in the national and local Chapters of the American Vacuum Society. Her primary research interests include grain boundary segregation and diffusion, ion beam/material interactions and the microstructural evaluation of materials using focused ion beams and transmission electron microscopy. Dr. Giannuzzi is a recipient of the NSF CAREER Award.

Sarah C. Everist received the B.A. degree in chemistry from California State University, Chico, where she also performed graduate studies and worked as a lecturer in Chemistry. She is a member of Technical Staff at Sandia National Laboratories. Since 1983, she has worked at Sandia’s Microelectronics Development Laboratory in the areas of nonvolatile memory development, process integration, and process development. More recent work has been in the area of rapid thermal processing. Jointly with NIST, she has worked to develop single-crystal reference materials for microelectronics, using bulk micromachining techniques.

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Christine E. Murabito is currently attending Montgomery College, Rockville, MD and is working toward the B.S. degree in computer science at the University of Maryland, College Park. She is a Student Computer Specialist in the IC Technology Group, National Institute of Standards and Technology (NIST), Gaithersburg, MD. At NIST, she writes data analysis programs to extract the electrical linewidth of silicon test structures, performs processing experiments, and assists with other research.

Patrick Shea started working for Motorola’s Government Electronics Group in the late seventies offering SEM/EDS/WDS analysis for the entire division. For the past seven years, he has been The Key SEM Operator for the Microelectronics Development Laboratory at Sandia National Labs.

Loren W. Linholm (S’67–M’68–SM’92–F’98) received the B.S. degree in electrical engineering from the University of California, Berkeley, in 1968, and the M.S. degree in electrical engineering from the University of Maryland, College Park, in 1973. He has been employed by the Naval Missile Center, Point Mugu, CA, and the Department of Defense, Ft. Meade, MD. Since 1978, he has been with the Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, MD, and heads the Integrated Circuits Technology Group. His research interests include the design, evaluation, and application of test structure based measurement methods for evaluating advanced integrated circuit performance, manufacturing tool control, reliability and failure analysis, and fabrication process diagnosis and control. Mr. Linholm is a member of the IEEE Electron Devices Society and the IEEE Instrumentation and Measurement Society and was a co-founder of the IEEE International Conference on Microelectronic Test Structures.