Evolution of navigation and simulation tools in failure

Evolution of navigation and simulation tools in failure analysis Etienne Auvraya, Paul Armagnata, Morgan Casonb, Emanuele Villab, Maheshwaran Jothi c, Michael Brügel c a

STMicroelectronics, Grenoble STMicroelectronics, Agrate c Synopsys

b

Abstract The work presented here is related to the utilization of EDA (Electronic Design Automation) & CAD Navigation tools in combination with real time images from analytical equipment in order to improve the accuracy & efficiency of Failure Analysis. Automation tools have been developed to better understand the design, which provide capabilities to overlay signal traces in analog and logic domains of the chip. This includes tools to start from ATPG (Automated Test Pattern Generated) and BIST (Built-In Self-Test). Dedicated patterns are generated to improve the accuracy of diagnosis. CAD Navigation and EDA schematic view tools are integrated with graphical drag and drop capability between them. This paper demonstrates applications specialized to analyse failing scan chains in complex SOC and Analog IP. It combines diagnosis results, backside imaging and simulation results in order to provide very accurate results. Subsequently performed destructive physical analysis greatly benefits from precise and confirmed fault localization.

Corresponding author. [email protected] Tel: +33 (0) 476584536; Fax: +33 (0) 476585200

Evolution of navigation and simulation tools in failure analysis Etienne Auvray a, Paul Armagnat a, Morgan Cason b, Emanuele Villab, Maheshwaran Jothi c, Michael Brügel c a

STMicroelectronics, Grenoble STMicroelectronics, Agrate c Synopsys

b

1. Introduction IC manufacturing processes are becoming more and more complex; hence yield- and reliabilityengineering is facing new challenges. As a matter of facts, Failure Analysis of rejects such as ATPG (Automated Test Pattern Generated) and memories failures are always anticipated by a diagnosis phase. Diagnosis is the process to isolate the source of observed errors in a defective circuit, so that physical failure analysis can be performed in order to determine the technical cause of the errors. Effective and accurate diagnosis is crucial to perform successful defect identification. Diagnosis verification, obtained through simulation tools, is useful to assess the quality of the diagnosis result. Today functional, electrical and fault simulations are mainly done by design engineer of the product, because this step cannot be easily executed inside failure analysis laboratories. But it becomes more and more critical as current design flows include different IPs and different design teams. In this work, we demonstrate how fault simulation software can guide FA engineers to probe the silicon much more efficient. Furthermore, in order to facilitate the navigation starting from results of diagnosis tools we developed several automation scripts to visualize the candidates. We also demonstrate how modern GUI features like drag and drop can help to cross-probe nets and instances between schematics, layout and simulation – for both logical- and analog fails. Analog fails thru SPICE simulation, logic fails thru diagnosis. In addition, this helps to quickly correlate CAD (Computer Aided Design) data with data measured on the faulty device. 2. Description of Tools in use 2.1. CAD navigation tool for Failure analysis CAD navigation software used in failure

analysis starts with a tool to view the layout and with possibility to drive the stage of the analytical equipment. For CAD navigation we are using the Avalon software from Synopsys due to its rich capability to bring in design data from multiple flows and the possibility to use automation scripts. See Data flow in Fig. 1

Fig. 1: Data flow

2.2. FASTKIT tool in Failure analysis [1] FASTKIT, written with Tool Command Language provides both a Graphical User Interface (GUI) and all the background functions that automate the database setup and the analysis process. Its features do allow the visualization of nets & instances by alignment of the hierarchies across different tools. See Fig. 2.

Fig. 2: Drag & Drop example between tools

2.3 Loading scan chains to CAD Navigation In order to analyse scan chain fails we have to overlay scan chain instances with their sequence number on the layout. Avalon automates this step and provide a direct loading mechanism to overlay scan chain elements on the layout as seen in Fig. 3.

Fig. 3: From DFT Scan chain to Avalon

2.4. Direct loading of DFT structures through drag and drop from Verdi to Avalon. DFT structures are either loaded from the STIL pattern file or through export from the DFT tool.(Fig4.)

measurements of the signals inside these flip-flops. This is generally done through backside access to the device using three typical methods:  Photon Emission Microscopy images  Laser Scanning Microscopy techniques  Probing techniques. The latter come in two methods, based on emission behaviour (Time resolved emission microscopy) or laser stimulated (Laser voltage probing) 3.1 Case 1: Localization of a failure in scan chain based on emission microscopy images linked to simulation. The product is a mixed signal product and has only one scan chain. The scan chain is uncompressed and a simple shift scan test sequence is applied (0011). We get the images below during execution of this sequence. The images are composed of the graphical overlay of three domains (Fig. 5.) 1. CAD Layout of poly and metal 1 layer 2. Photon Emission Image 3. Scan Chain FF bounding boxes along with their sequence number

Fig. 5: Emission image during scan shift loop

Fig. 4: From DFT tool to Verdi and Avalon

3. Analysis of interrupted scan chains Diagnosing on failing scan chains could be quite an issue: in case of mixed signal products we generally have few non-compressed chains and typical results of the diagnosis lead to multiple scan flip flops (in worst case this could even be the entire scan chain). In case of complex SOC, we have a compressed scan architecture, and again may have several flipflop candidates as diagnosis result. Applying the xtolerance pattern generation method [14], we are able to reduce the localization down to one segment of the compressed chain. Even with a diagnosis resulting in a single flipflop, the probability to get the physical defect is not at 100% because the physical defect could also be in the external interconnections or internal into the flipflop itself. Intra-cell aware diagnosis can help to increase the diagnosis accuracy. The usual method to improve physical analysis results is to complement the diagnosis by

Expected is the same emission pattern inside every scan chain FF. At other locations there should be no photon emission. Unexpected emission spot detected outside a Flipflop between FF 211 and FF 212. (Fig. 6.) We can clearly identify a photon emission which does not follow the pattern of the other FF’s. Using the CAD Navigation system and by adding the interconnect signals we can show the relation of emission and interconnects between scan chain Flip Flops.

Fig. 6: Abnormal emission outside chain cells

Fig. 6a: Left side: CAD Navigation with emission spot, Right side: Schematics with simulation.

Emission spots could be easily cross-mapped to Verdi schematic and simulation: The bright spot as seen in fig. 6a (red highlighted instance) is a buffer clock toggling. The logic simulation in conjunction with the circuit schematic linked to the CAD Navigation confirms the finding of the photon emission image and is available in Verdi schematic viewer.

Fig. 8: Left side: Backside emission view during shift test repetition loop, Right side: view overlay of one chain in serial mode (about 6500 cells)

We are using probing with dichotomy approach: (Also called successive approximation method) Dichotomy approach consists of measuring the output of the first cell, the last one and then the one in the middle. After this continue with the failing portion. Number of iterations points is given in Fig. 9.

The link to chain interruption is quite clear. The impact on cell 211 and 212 can be seen in simulation (fig. 7).

Fig. 9: Number of iteration of measure versus number of cells: For 6500 cells, we can get the localization with 14 measures.

Fig. 7: Simulation on emission spot 1

3.2 Case 2 Application to probing methodology In higher integrated devices (28nm node) the analysis of interrupted scan chains is more complex compared to the previous case. One of the challenges is the length and compression mode of scan chains. In order to get images using photon emission microscopy we need the pattern sequence to be short enough to satisfy the instrument requirements. Furthermore, we require the scan chain to be exercised in a non-compressed mode. Also the spatial distribution of the scan chain FF under exercise should match the field of view of the instruments with the required resolution. In our FASTKIT automation tool [1] we provide a fully automated method to create a test sequence meeting the above requirements. 3.2.1 Non compressed chain flow. In this mode, scan chains could be very long (More than 2000 FF. Fig. 8) The first method to solve the problems with long scan chains, is the attempt to find the failing site by image path recognition (LVI or emission).

Fig. 10: Internal probing by LVS finds the last functional and first failing FF in Scan Chain.

The result of the probing can be seen in fig. 10. 3.2.2 Case of compressed scan chain. This mode is mandatory on latest technology like CMOS28nm because in complex SOC, noncompressed chain patterns are too long to be used in production test systems In this case we have to work using compressed patterns, and the understanding of what is applied to the segment chain is less obvious, but we are supported by the capability to visualize the waveforms applied to the segment and its corresponding cells positions in Avalon.

database and create the Avalon database which will be used for the device (transistor) level crossmapping along with the LVS database. (Fig. 13 and 14.)

Fig. 13: Export Schematics from OpenAccess data

Fig. 11: Import of diagnosis results: segment chain

The FASTKIT GUI allows creating the simulation file of this pattern and loading it inside Verdi schematic viewer. Probing becomes easy and fast using dichotomy. When the scan structure of the chip does not use scan compression techniques, applying a full scan pattern can take too much time and make the physical measure difficult. In order to get rid of this limitation, a feature has been provided that creates a shorter shift loop which loads the scan structure with the same values around the gates of interest (the candidate and its fan-in cone) so that enough measures are done. The short sequence pattern is also build with an added trigger pin often used on analytical tools and we generate at this step a simulation file relative to internal node of the fan-in cone containing simulation for user defined cycles before capture which can be read in Verdi schematic / waveform viewer. Fig. 11 gives an example of diagnosis results for a complex SOC for a compressed ATPG where short pattern could also be used. 4. Application of spice simulation The CAD-Navigation system (Synopsys Avalon in this case) has the capability to import schematic data modelled down to (device) transistor level. (SPICE/CDL netlists). We use two flows (See fig. 12) to import transistor level data into Avalon. 1. Use SPICE/CDL netlist used as source netlist in LVS. 2. Read data from OpenAccess database. In both cases the results of “sign off” LVS run are used to correlate devices, nets and instances from physical domain (layout) to the logical domain (netlists).

Fig. 14: Cross-mapping of 3 transistors across Layout & Schematics

4.1 Application of spice schematic to intra-cell diagnosis. Intra-cell diagnosis is now an available option for fault simulation and logic diagnosis: The main works in this domain is based on fault dictionaries or critical path tracing which includes circuit models down to transistor level [6], [11], [12], [13]. CAD Navigation for product which we have the navigation database build from LVS (Layout Versus Schematic), we can open results of intra-cell candidates so that physical cross mapping at transistor level (intra-cell) is possible using the schematic viewers of Avalon. In a mixed analog product we get a failure on a scan pattern in transition mode. The results of diagnosis tool gave one cell with a possible intra cell defect. Avalon allows to load direct results of design based diagnosis and to open also the whole schematic of the device obtained from OpenAccess database. Below fig. 15 shows the visualization of such results.

Fig. 15: Avalon MaskView and Schematic view with diagnosis results loaded.

Fig. 12: Flow for device level cross-mapping in Avalon.

User can export the Schematics from OpenAccess

Intra cell diagnosis can be run directly from diagnosis results using spice description of the cell Detailed intra cell flow given in [1]. Example is given in fig. 16.

The SEM image in the fig. 19 illustrates the physical cross-section performed by FIB and image on the right shows the simulated cross-section performed by Avalon. The red circled area in fig. 19 points to the defect location in silicide at the polysilicon gate. We successfully found the defect location which introduced a resistive path to the gate of PMOS MP25. Fig. 16: Zoom on diagnosis and schematic view

Results of intra cell diagnosis pointed out the 3 following elements: NET76 slow to fall, MP23/S slow to fall and MP25/G slow to rise This cross mapping of Layout & Schematics could be visualized inside Avalon as shown in fig. 17.

4.2 Application of spice simulation on interpretation of emission microscopy The flow to create a modified transistor level netlist to reproduce an emission or functional behaviour of a failing block is the following: 1. Get the netlist of the failing block. 2. Combine it with MOS model from design library 3. Start from netlist to build simulation file 4. Launch simulation [eg. ELDO] 5. View results on Verdi tool 6. Modify netlist to make short, add resistor etc Example: During an emission microscopy of failing scan chain we get different emission site depending upon the sequence of data loading inside the chain (See fig. 20 and fig. 21.

Fig. 17: Cross mapped view of Intra-cells

Results of intra-cell diagnosis leads the suspect to a resistance path near the two PMOS MP25 and MP23.

Fig. 20: Result of spice simulation (Open of one suspected contact)

Fig. 18: Location of cross section

Physical analysis is performed by a FIB crosssection.

Fig. 21: Data failure error propagation is reproduced

Fig. 19: Cross-section following plane of fig. 18

4.3 Full FA flow applied to an FDSOI28nm product In this section we describe the application of the complete flow to a yield reject on a 28FDSOI product. Failure mode was high frequency scan pattern failure (transition fault model) at minimum spec voltage at cold and room temperature. The part was good at hot temperature, indeed the pass/fail threshold of the test was sensitive to voltage and temperature. The interaction between Electrical Fault Localization techniques and EDA tools was crucial for the success of the applied Failure Analysis flow. The applied flow for the case is comprehensive of diagnosis from ATE data logs, Dynamic Analysis by Laser Stimulation (DALS), Laser Voltage Probing (LVP), physical analysis through die deprocessing and Focused Ion Beam x-section for the defect identification and SPICE simulation of the relationship between the found defect with the observed failure mode. The diagnosis was pointing with high match to a single net: data input of a scan flip-flop, output of an AND port. The CAD-Navigation system allowed the quick search of the failing net within the product netlist hierarchy tree and the identification of both the net and its driver/receiver cells on the device layout. (See fig. 22)

image and CAD layout confirmed the correspondence between diagnosis results and the anomalous spot observed. Laser Voltage Probing (LVP) technique was applied to the DUT in order to identify the critical flip-flop nodes by characterizing their waveforms as seen in fig. 24, by application of a square wave to the device.

Fig. 24: LVP waveform characterization

In this case, CAD to back-side silicon image alignment was crucial in the association of the flipflop internal nodes on the layout to the measured signals through the technique. Physical analysis was performed through die delayering and FIB cross-section at the location suggested by previous steps of Fault Localization. We identified a bridge at Metal1, inside a flipflop connecting two internal nets as shown in fig. 25.

Fig. 25: Physical analysis by FIB x-section Fig. 22: Diagnosis results vs CAD-Navigation

Second step of the FA flow was the application of DALS analysis. The laser stimulation induced a local variation of the die temperature, which resulted in a modification of the pass/fail threshold at the exact location of the defect. The synchronization between the laboratory tester (providing the testing sequence) pass/fail signal and the laser position on the die, allowed the DALS equipment to highlight a spot on the die surface, corresponding to the suspected position of the defect.

Verification is the final step of the FA flow, and it was achieved through software simulation of the bridge, by the addition of a resistive path between the two affected nets. By simulation it was possible to explain the failure mode. The simulation also showed the behavioral dependency on voltage and temperature as seen in fig. 26.

Fig. 26: SPICE simulation verification

Fig. 23: DALS anomalous spot overlay to layout

As shown in fig. 23 the overlay between DALS

5. Conclusion and perspectives We presented a new set of EDA supported tools for fast and easy use by Failure Analysis teams. The new tools greatly extend our capability of fast correlation between actual measurements and simulated results. The new tools will free the failure analysis engineer from cumbersome data crunching efforts in different domains (physical layout, simulation, crossprobing) for activation of the functional failure mode. He can now focus on interesting nodes through the real-time overlay to schematic and simulation. Consequent physical analysis will benefit from accurate fault localization and electrical characterization at point of failure. Complementary work is ongoing to experiment with spice simulation on more complex analog IP.

Acknowledgments Acknowledgments to Synopsys Verdi team and Synopsys diagnosis team.

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