Int J Syst Assur Eng Manag (July-Sept 2013) 4(3):303–311 DOI 10.1007/s13198-013-0170-9
ORIGINAL ARTICLE
Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage Ashok Kumar Suhag • Vivek Shrivastava Nidhi Singh
•
Received: 18 November 2012 / Revised: 1 June 2013 / Published online: 23 June 2013 Ó The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013
Abstract In nanometric technologies, testing of delay faults in the integrated circuits is becoming mandatory during manufacturing test. Delay fault testing involves two test vectors. Scan based designs is used for delay fault testing with architectural limitations of traditional scan limits the two pattern delay tests that can be applied to a design which results in degraded delay test coverage. Transition delay fault (TDF) coverage improves appreciably by the use of enhanced scan design as it solves the problem by supporting arbitrary delay test vector pairs at the cost of high area overhead. It also needs fast hold signal which is analogous to scan enable signal as in case of LOS testing. Delay testable enhanced scan flip–flop (DTESFF) has been proposed as a low cost DFT technique to achieve high TDF coverage using enhanced scan design without the need of fast hold signal. In this work, a partial DTESFF scheme augments few scan flip–flops with the DTESFF design by choosing scan flip–flops carefully. It attains most of the TDF coverage advantages of a full DTESFF design with reduced area overhead. Significant improvement in TDF coverage for partial enhance scan using DTESFF has been seen on ISCAS’ 89 benchmark circuits. Keywords DTESFF Fault coverage Partial enhanced scan Delay test A. K. Suhag N. Singh Gautam Buddha University, Greater Noida, India e-mail:
[email protected] N. Singh e-mail:
[email protected] V. Shrivastava (&) National Institute of Technology Delhi, Delhi, India e-mail:
[email protected]
1 Introduction Delay fault comes in picture when delay of critical path in a circuit exceeds the rated clock time period as a result it fails to meet the timing requirement. Increase in gate count and operating frequency of integrated circuits (ICs) in the deep sub micron technologies results in manufacturing defects that leads to timing errors which has become a serious concern during manufacturing test. That’s why it is compulsory to embed delay testing with the stuck-at tests for manufacturing test (EEDesign Article 2002; EETimes Article 2003). The major source of timing related failures are gate oxide failures, resistive opens and shorts, via and voids. These physical defects lead to delay faults through the violation of circuit timing requirement in nanometer technologies (Hawkins et al. 2003; Mak et al. 2004; Lin and Reddy 1987; Nassif 2000). These defects are highlighted regularly in aggressively scaled technologies. In addition, several defects that are not identified through conventional test methods that can grow with the time under the stressful operation results in premature life failure. While burn-in stress testing method to filter out these defects is exorbitantly expensive. High fault coverage delay test but low cost methods to identify such faulty parts are immediately required by the industry. Functionality of manufactured chips is not completely verified by the traditional stuck-at tests due to failure of stuck-at fault model in evaluation of circuit timing. Conventional functional at speed testing has high cost of test development especially when scale of circuit under test is in million of gates. However, in System-on-Chip (SOC) designs inadequate access to the internal cores makes application of at-speed functional tests unfeasible. Controllability and observability of internal signals in SOCs are
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appreciably improved through scan-based delay testing and are emerging as the most promising technique for the delay testing of large SOCs.
2 Scan based delay test Structural scan based delay testing is carried out as a low cost option for the functional timing tests. It needs the application of two pattern tests \V1, V2[ from scan chains. Vector V1 is known as the initialization pattern while vector V2 is called the Launch pattern. Firstly the initialization pattern V1 of the test vector pair is scanned inside the scan chain with the use of slow scan clock for the initialization of the internal logic values of the CUT (circuit under test). When the CUT becomes stable from the switching activity due to application of initialization pattern after that in the next clock cycle launch pattern is initiated and the response of the applied pattern pair is captured in the consecutive cycle. To test the delay faults, time period required in between the launch and the capture clock should be at-speed cycle so that it is equal to an appropriate launch to capture window that reflects the required frequency of operation. The time period required in between the initialization and launch clock cycle need not be at-speed and it is achieved by using slow scan clock. Finally captured response in scan chain is taken out from the CUT and then matched with the golden test response. Due to the structural restriction of scan, all the possible combinations of vector \V1, V2[ cannot be permitted through the scan based delay test. By mechanism through which vector V2 is generated, the scan based delay test are classified as skewed load test [launch-on-shift (LOS)] (Patil and Savir 1992; Savir 1992), or Broadside test [launch-on-capture (LOC)] (Savir and Patil 1994; Saxena et al. 2002). In the LOS based scan test, the vector V2 is generated from vector V1 as Vector V2 is one-bit shift from vector V1 while in LOC scan based test vector V2 is the CUT output response of vector V1, so V2 vector is constrained on vector V1. In general, LOS test is not facilitated by most of design because it needs fast scan enable signal (Fig. 1) for the switching between scan shift mode which is needed to launch test and functional mode to capture the output response of transition delay test within a specified clock period. Implementation cost of such fast signal is quite expensive. Due to this reason, LOC test is preferred over LOS test. But in general LOS test shows somewhat better fault coverage (Savir and Patil 1994; Zhang et al. 2006; Wang et al. 2004) and usually this coverage is reached with fewer test patterns (Abraham et al. 2006; Xu and Singh 2006). Unfortunately, the constraints imposed on the generation of vector V2 bounds the transition delay fault (TDF) (Waicukauski et al.
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IP
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(b) Fig. 1 Timing waveforms for delay tests a skewed-load b broadside (Devtaprasanna et al. 2005)
1987) coverage which is obtained using LOC and LOS scan delay tests. To achieve high TDF coverage, greater flexibility is needed in the selection of vector V2. The rest of paper is organized as follows. In Sect. 3 we reviewed the enhanced scan based transition delay testing which facilitates arbitrary vector V2. In Sect. 4 we reviewed partial enhance scan approach. In Sect. 5 we reviewed delay testable enhanced scan flip–flop (DTESFF) which supports test with slow hold signal. In Sect. 4 we discussed flip–flop selection criteria for partial enhanced scan and signal probability analysis. We discussed the experimental results for ISCAS 89 benchmark circuits using for partial enhance scan based on DTESFF approach in Sects. 7 and 8 concludes the paper.
3 Enhanced scan chain Enhanced scan method was introduced to attend the issue of low delay test coverage. Constrained imposed on the generation of vector V2 in scan based delay testing is eliminated by enhance scan and allows the arbitrary combinations of \V1, V2[ to obtain high fault coverage for TDF testing. This can be achieved by the addition of redundant flip–flop with every functional flip–flop in the design which ultimately doubles the length of scan chain as illustrated in Fig. 2. Now the test vectors V1 and V2 are scanned inside simultaneously and loaded inside scan in an arbitrary manner. For the initialization of test, vector V1 is placed in functional flip–flops while Vector V2 bits are placed in corresponding redundant flip–flop following
Int J Syst Assur Eng Manag (July-Sept 2013) 4(3):303–311 Fig. 2 Classical enhanced scan with alternating regular and scan FFs
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every functional flip–flop. After that delay test is executed in skewed load test or LOS test mode while the bits in redundant flip–flop may be chosen arbitrarily without any restriction on the formation of vector V2. Enhanced scan flip–flop design based on the pulsed flip–flop circuitry (Kumar et al. 2009) shows considerable improvements in power and timing compared to alternative designs. Single event upset tolerant flip–flop (Namba et al. 2010) also allows the enhanced scan based delay fault testing. Since the duplication of every flip–flop in the design is very expensive so another enhanced scan method uses extra latch instead of flip–flop with additional control signal (hold signal) on the output of every scan flip–flop as illustrated in Fig. 3. The concept behind this approach is to grasp the initialization test pattern V1 in these hold latches while the test vector V2 is shifted arbitrarily inside scan chain (Bushnell and Agrawal 2000). After scanning of test vector V2 inside scan chain delay test is launched simply by making latches transparent through deactivation of hold control signal which allows switching of combinational logic inputs from vector V1 to vector V2. One of the shortcomings of this approach is the additional delay introduced on the signal paths. Figure 4 illustrates the timing diagram to hold the vector V2. Hold signal is kept high while shifting of vector V1 from scan flip–flop to hold latch and kept low during the shifting of vector V2 in scan flip–flops to hold the vector V1. After loading of test vectors, hold control logic makes the latches transparent to accomplish the test. Due to this reason, it needs fast hold signal to hold the data in latch and then transfer it to the circuit (Hurst and Kanopoulos 1995)
which is similar to the problem that exists in Skew-load testing. It requires that the routing of hold signal should be timing critical similar to clock signal which is prohibitively expensive. It does not facilitated by most of enhance scan designs. Therefore, delay testing generally prefers to use LOC testing which has low delay test coverage. However recent trend for obtaining high delay test coverage from scan based tests has revived the interest in such methods (Wang et al. 2004; Xu and Singh 2006, 2007; Seongmoon et al. 2004; Wang and Wei 2008). Several researchers have investigated alternative delay fault testing methods for high delay test coverage with reduced DFT overhead (Cheng et al. 1991; TekuMalla et al. 1997; Chao et al. 2011; Deepak et al. 2009; Pei et al. 2011). Enhanced scan method has been found most effective method which offers high TDF fault coverage at the cost of the high area overhead. In this paper, it has been proposed to use partial enhance approach using DTESFF that supports LOC test without the requirement of fast hold signal. It provides the test coverage benefits of enhance scan design at the cost of 10–35 % scan flip–flops upgraded to DTESFF. DTESFF gives penalty of AOI gate as compared to the conventional enhanced scan flip–flop.
4 Partial enhance scan Enhanced scan based delay test methodology is most efficient method for high delay test fault coverage but rarely been used in practice so far because of the exorbitantly high area overhead.
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Fig. 3 Enhanced scan with hold latches (Bushnell and Agrawal 2000)
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Fig. 4 Waveform for hold signal during delay test (Suhag and Shrivastava 2011)
On the other hand recent trend to attain high delay test coverage which is not possible from conventional LOC tests has received attention in such methods (Cheng et al. 1991; Chao et al. 2011; Deepak et al. 2009; Pei et al. 2011; Devtaprasanna et al. 2005). Partial enhance scan (Fig. 5) is most promising approach in which a small number of carefully selected scan flip–flops is upgraded to enhanced flip–flops and provides the advantages of a full enhanced scan design.
5 Review of DTESFF delay test technique The functional structure of DTESFF presented in (Suhag and Shrivastava 2011, 2012) is shown in Fig. 6a. By observing that DTESFF has equivalent pin outs when compared to the conventional enhanced scan flip–flop (Bushnell and Agrawal 2000) thus it is fully compatible from the design point of view.
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Hold latch
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In Fig. 6a extra AOI gate is inserted in the circuitry of DTESFF as compared to enhance scan flip–flop. Hold alignment logic controls the incoming slow hold signal into a well timed signal that gives the hold latch transition in a proper timed mode during the holding and propagation of the test vectors to be support the enhanced scan approach. As illustrated in Fig. 6b that the high logic hold signal tends the (timed) control input of the hold latch to be logic high through OR gate which is equivalent with the scan shift mode. Initially during scan-in cycle hold signal is kept high and the output of AOI gate is high. When hold signal goes to low logic ‘0’ then the controlled hold latch signal through AOI does not switches directly although it stays high ‘1’ when clock signal is low because of feedback signal from this initial high value ‘1’. Output of the inverted clock is high and signal from feedback path makes high logic at the output of AND gate which is propagated through OR gate and as a result of which output of OR gate is high. High timed hold latch control signal changed to logic ‘0’ only when the clock signal goes high, which forces the output of AND gate changed to logic ‘0’. So, the hold control signal switches asynchronously from high to low at the end of the scan shift cycle which transfers vector V1 into the hold latch from the scan flip–flop. The actual timed control signal sent to the hold latch through the hold alignment logic is being switched synchronously after the next active clock edge. It results in an extra shift operation in the hold latch, which launches the test vector V2 and after that response is evaluated as required by the Enhanced scan test. With the help of DTESFF we can launch delay test in LOC mode without the requirement of fast hold signal.
Int J Syst Assur Eng Manag (July-Sept 2013) 4(3):303–311 Fig. 5 Partial enhance scan (enhance scan flip–flop is denoted as ESFF)
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Fig. 6 a Delay testable enhanced scan flip–flop (DTESFF). b Timing diagram of delay testable enhanced scan flip–flop (DTESFF) using slow hold signal (Suhag and Shrivastava 2012)
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6 Flip–flop selection procedure for partial enhanced scan Scan based delay test requires two test vector where first test vector V1 is selected randomly as vector V1 is scanned inside the scan chain while test vector V2 is dependent on test vector V1 in both of LOS and LOC based delay testing due to the structural restriction of scan design that’s why test vector V2 cannot be selected arbitrarily and the probability of vector V2 to be either 0 or 1 in LOC based delay testing is not 50 % as vector V2 is the output response of V1 applied to the combinational logic. Few of the bits in the test vector V2 are more regularly appear as 0 or 1. These bits in the vector V2 are called biased bits. Every bit of input vector V1 has an unbiased (0.25, 0.25, 0.25 and 0.25) probability to be logic ‘0–0’, ‘0–1’, ‘1–0’ and ‘1–1’. Test vector V2 is the output response of test vector V1 in the LOC based delay testing. As shown in Fig. 6 estimated probability for vector V2 (0.1094, 0.2812, 0.2812, 0.3281) and probability to be zero is 0.3907 and probability to be one is 0.6093. Suppose in a scan chain there are 10 scan flip–flops having probability of Vector V2 is (0.1, 0.21, 0.38, 0.42, 0.52, 0.58, 0.62, 0.78, 0.81 and 0.94). To define an unbiased bit we randomly defined 0.7 as upper bound value and 0.3 lower bound value. Signal probabilities 0.94 and 0.1 in above example point that they are biased towards ‘1’ and ‘0’, respectively; while bits having probability 0.42, 0.52, 0.58 and 0.62 shows that they are unbiased. During LOC delay test few flip–flops frequently attain a biased value (‘0’ or ‘1’) in the test vector V2 vector during the test which leads to degraded fault coverage in LOC testing. By any means these biased is converted into unbiased values so that the fault coverage achieved through LOC test is enhanced. Hence to substitute the biased values of flip– flops from the combinational circuits with DTESFF in LOC test mode is proposed. It provides the flexibility of choosing vector V2 randomly and scanned in Scan chain. This methodology provides low area overhead as compared to the full enhanced scan designs. Using 0.3 and 0.7 signal probabilities as the threshold levels for biased values and the bottom ‘‘unbiased’’ flip–flops (0.38, 0.42, 0.52, 0.58, 0.62) is realized with the scan flip–flops and the biased flip–flops (0.1, 0.21, 0.78, 0.81, 0.94) are realized using DTESFF. Output signal probabilities of a combinational logic are evaluated for unbiased arbitrary inputs using probabilistic analysis.
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equivalently same and independent. On the basis of this assumption we estimated the signal probability to be zero or one. Signal probabilities are defined as follows: P00: Probability so that signal remains stable 0; P01: Probability of rising edge transition; P10: Probability of falling edge transition; P11: Probability so that signal remains stable 1; Probability of the signal to remain zero is (P00 ? P10); and Probability of the signal to remain one is (P01 ? P11).
6.2 Calculation of probability AND gate, NAND gate, OR gate and inverter with two inputs (A and B) and C as an output considered for probability computation. It is assumed that all events are equivalently same at the input, i.e., stable 0, stable 1, rising (0–1) and falling (1–0) transition. So the probability for every gate is as follows: AðP00; P01; P10; P11Þ ¼ Að0:25; 0:25; 0:25; 0:25Þ BðP00; P01; P10; P11Þ ¼ Bð0:25; 0:25; 0:25; 0:25Þ Probabilities at the output of circuit is CðP00; P11; P01; P10Þ ¼ Cð0:1094; 0:2812; 0:2812; 0:3281Þ P0 ¼ 0:3907 and P1 ¼ 0:6093
Probability of AND Gate is calculated as follows: P00c ¼ P00A P00B þ P00A P01B þ P00A P10B þ P00A P11B þ P01A P00B þ P01A P10B þ P10A P00B þ P10A P01B þ P11A P00B : Rising transition probability P01 at C i.e. P01C. P01C ¼ P01A P11B þ P11A P01B þ P01A P01B : Falling transition probability i.e. P10C. P10C ¼ P10A estimated probability for P11B þ P11A P11B þ P10A P10B : Probability of stable 1 P11C ¼ P11A P11B : Probabilities for OR Gate P00c ¼ P00A P00B : P01C ¼ P00A P01B þ P01A P01B þ P01A P00B
6.1 Signal probability analysis Signal probability analysis is defined as the probability of output signal either to be 0 or 1. Let’s suppose that the probability at the input and output of every flip–flop are
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P10C ¼ P10A P10B þ P10A P00B þ P00A P10B P11C ¼ P00A P11B þ P01A P11B þ P01A P10B þ P10A P11B þ P10A P01B þ P11A P00B þ P11A P01B þ P11A P10B þ P11A P11B
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Probability for inverter C
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7 Experimental results
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To measure the effectiveness of DTESFF based partial enhanced scan methodology the experiments are carried out with large ISCAS 89 benchmark circuits. These benchmark circuits comprise of 74–638 flip–flops in the design while smaller benchmark circuits have a small number of flip–flops to offer significant results. Some of large benchmark circuits for e.g. S38584 shows good LOC (TDF) test coverage in higher nineties (97.4 %) without the use of DTESFF methodology gives a narrow margin for TDF coverage enhancement in these circuits so that’s why they are not considered. The experimental results are reported in Table 1. ATPG tool (TetraMax) is used for the generation of test vectors for TDFs. We have selected flip–flops to upgrade to DTESFFs based on the signal probability analysis of input lines. Poor controllable flip–flops are upgraded to DTESFFs. Ordering of flip–flops for every design is acquired on the basis of signal probability as explained earlier and after that TDF coverage is evaluated by increasing the number of DTESFF (5 % at a time) based on the sequencing in the priority list on the basis of signal probability analysis. The plots in above Fig. 8 demonstrate the results. TDF coverage for full enhanced scan design attains 100 % coverage. Fault coverage versus percentage of DTESFF is demonstrated in above plot which shows that by carefully choosing few scan flip–flops (10–30 %) offers most of the benefit of fully enhanced scan design.
P10C ¼ P01A P01B þ P11A P01B þ P01A P11B P11C ¼ P00A P00B þ P00A P01B þ P00A P10B þ P00A P11B þ P01A P00B þ P01A P10B þ P10A P00B þ P10A P01B þ P11A P00B As explained above, we calculate the probability for the circuit as shown in the following example: we assume A, B, C and D are the Primary inputs and o/p is the primary output. Probability calculation to be zero or one at the primary output is shown in Fig. 7 given below. 6.3 Probability computation As explained above methodology is used for the computation of static signal probability. It is assumed that all the events at primary inputs and output of flip–flops are uniformly distributed. A reasonably good estimate of signal transition probability by above explained method. On the other hand second vector at the output of a flip–flop will be dependent on the first vector. So the probability calculation should be done iteratively for the precise solution. In the circuits all the signal probabilities is computed iteratively. On the basis signal probability scan flip–flops are sorted for the up gradation to DTESFF. Signal probabilities at the input of flip–flops helps in classifying the flip–flops for the up gradation to DTESFF and allow us incrementally to discover the subsequently
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0, 0.5, 0.5, 0 Fig. 7 Probability computation
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90.4 92.54 S15850 S13207
Abraham J, Goel U, Kumar A (2006) Multi-cycle sensitizable transition delay faults. In: Proceedings of VLSI test symposium, pp 306–311
S1423
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Two pattern delay test is not allowed by traditional scan based designs due to the architectural limitation and results in the degradation of TDF coverage. This limitation is removed by enhanced scan based designs by allowing arbitrary delay test vector pairs at the expense of high area overhead. Enhanced scan design works in LOS mode which demands a control signal able to switch at operational clock speeds to ensure test timing. Such high speed signals implementation is expensive as analogous to cost of extra clock signal. DTESFF based design uses AOI gate with every hold latch in enhanced scan design for configuration of clock edge which is our low cost solution. In this work we present partial enhance scan design which uses DTESFF design and the selection of scan flip–flops needed to be replaced by DTESFF is based on probability analysis. Most of the benefits of Full enhance scan design is achieved by DTESFF based partial enhance scan design. Our result displays that by choosing 10–30 % flip–flop carefully facilitates good TDF coverage. DTESFF based partial enhance scan design make it feasible to use hold latch based enhanced scan with slow hold signal is discussed in this work and used generally where high delay test coverage is required. In this work a simple heuristic is used to find the scan flip–flops need to be replaced by DTESFF for better TDF coverage in the benchmark circuits. A better heuristic for flip–flop selection can further results in improved TDF coverage. Optimized selection of enhanced scan flip–flops is always open issues for the better TDF coverage with minimum number of enhance scan flip–flop.
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8 Conclusion
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Fig. 8 Fault coverage versus percentage of DTESFF in ISCAS 89 Benchmark Circuits
References
Circuits
Percentage of DTESFF versus TDF coverage
Table 1 Percentage of DTESFF versus TDF coverage
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