FPGA- Based Current Controllers for AC Machi

This document is the pre-print version of the final paper:

Naouar, M.-W.; Monmasson, E.; Naassani, A.A.; Slama-Belkhodja, I.; Patin, N., "FPGABased Current Controllers for AC Machine Drives—A Review," Industrial Electronics, IEEE Transactions on , vol.54, no.4, pp.1907,1925, Aug. 2007

doi: 10.1109/TIE.2007.898302

keywords: {AC motor drives;PI control;digital control;electric current control;field programmable gate arrays;on-off control;AC machine drive;FPGA-based current controller;digital controller;field-programmable gate array;hardware architecture;on-off current controller;predictive current controller;proportional-integral current controller;AC machines;Control systems;Costs;Digital control;Digital signal processing;Field programmable gate arrays;Hardware;Proportional control;Signal processing algorithms;Torque;Alternating current (ac) machine drives;current control;fieldprogrammable gate array (FPGA);hardware architecture design}, URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4271569&isnumber=42 65775

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FPGA-Based Current Controllers for AC Machine Drives – A Review

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M-W. Naouar , Student Member, IEEE, E. Monmasson , Senior Member, IEEE, A. A. Naassani , 4 5 I. Slama-Belkhodja , and N. Patin , Student Member, IEEE 1,4

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L.S.E-ENIT BP 37-1002 Tunis le Belvédère, Tunisia, email: [email protected] , [email protected] 2

SATIE-IUP GEII, rue d’Eragny, 95031 Cergy-Pontoise, France, email: [email protected] 3

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SATIE, Université d’Alep-Syrie, email : [email protected]

SATIE-ENS Cachan/CNRS, 61 avenue du Président Wilson, 94235 Cachan, France, email: [email protected]

Abstract─The aim of this paper is to present the interest of implementing digital controllers using FPGA components. To this purpose, a variety of current control techniques, applied to AC machine drives, is designed and implemented. They consist of ON-OFF current controllers, PI current controller and predictive current controller. The quality of the regulated current is significantly improved. It is mainly due to a very important reduction of the execution time delay. Indeed, in all described techniques, the execution time of the designed hardware architectures is only of a few microseconds. This time reduction derives directly from the possibility offered by FPGAs to design very powerful dedicated architectures. Numerous experimental results are given in order to illustrate the efficiency of FPGA-based solutions to achieve high performance control of electrical systems.

I. INTRODUCTION During these last twenty years, the control of industrial electrical systems has been the focus of important research and many significant improvements have been achieved [1], [2]. These progresses are mainly due to the technology revolution leading to very powerful components which allow implementing more and more complex control algorithms. With successively improving reliability and performance of digital technologies, digital control techniques have predominated over their analog counterparts. Indeed, compared with traditional analog control, digital control offers many advantages such as flexibility to modify the control schemes, adaptability to different systems and operating conditions, immunity to noise and insensitivity to component variations. Nowadays, digital control techniques are mostly carried out with microcontrollers or Digital Signal Processors (DSP) due to their software flexibility and low cost. Thus, DSP-controllers are considered by many engineers as an appropriate solution [3]. These components have an ALU (Arithmetic Logic Unit) especially dedicated to the real-time computation. They also integrate peripheral units like Analogto-Digital Converter (ADC) and Timers which are adapted to the needs of electrical system drives. Nevertheless, some advantages of the analog control are still very difficult to be replaced such as accuracy and most of all, no feedback loop delays. In fact, although multiprocessor schemes or high performance DSP processors can deal with this problem, they are still limited for complex algorithm structures and their costs can exceed the benefit they bring [4]. Field Programmable Gate Array (FPGA) can also be considered as an appropriate solution [5] in order to boost performances of controllers and consequently to reduce the gap between the analog and digital world. When associated to fast ADC, the extremely fast computation capability of FPGAs allows a few microseconds real-time computation of control algorithms in spite of their complexities. On the other hand, FPGAs allow the development of well adapted control architecture with freely positioned sampling instants [8], [9]. In the same time they allow the implementation of different control functions for a full System on Chip (SoC) integration [5]-[7]. As a result, FPGAs are quite mature for the electrical

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drive applications. They have already been applied with success to the control of PWM converters [10], machine drives [11], [12] and even to multi-machine control system [13]. Furthermore, as DSP-controllers, FPGAs are very low cost components. Even recently, a company has also introduced an FPGA family that includes several analog functions, such as an ADC [14]. Hence, having in mind to make a synthesis of these reported advantages and also to include new ones, the authors present in this paper a systematic description of a relevant set of FPGA-based current controllers applied to AC machine drives. These types of applications are good examples of high level real-time performances industrial control systems. An FPGA implementation of ON-OFF current controllers is firstly exposed. Two groups of controllers are analyzed and synthesized. The first group is characterized by a variable switching frequency, while the second one is based on a limited switching frequency. Using FPGA-based controllers permits to improve significantly the quality of the current waveforms due to their very small execution time. In these conditions, the obtained digital current controllers can be approximated quite closely to their analog counterparts. A PI current controller is then synthesized. It also consists in putting in evidence the contribution of the freely positioned sampling instants to enhance the control performances. Once again, the very small execution time permits the development of a non synchronous PWM strategy which means that the voltage references are refreshed at very high sampling rate (up to 200kHz). This high rate voltage reference refreshment has a great interest for high power applications where low switching frequency is required. After that, the development and FPGA implementation of a synchronous machine predictive current controller is presented. As known, predictive current controllers require complex on-line computation schemes [15]-[18]. Therefore, the digital implementation of a predictive current controller is characterized by an inevitable delay between the current sensing instant and the moment where the adapted Voltage Source Inverter (VSI) voltage vector is ready to be applied. The control performance in this case depends strongly on the computation time, which must be shorter enough with respect to the sampling period [19]. Otherwise, if the computation time is not short enough, complex algorithmic modifications are needed to ensure basic level performances for the system to be controlled [20], [21]. The proposed FPGA-based predictive current controller ensures a real-time voltage vector computation without adding any algorithmic modifications. In this case, the whole execution time (including AD conversion) is only equal to 4.52µs.

However, reaching a high level of control performances can only be obtained with the help of important design efforts. That is the reason why, authors present in a dedicated section an appropriate FPGA-based design methodology. It results from a necessary compromise solution between two opposite needs: a friendly design environment that does not afraid the non-expert micro-electronics designer and the full respect of control performance requirements.

All the studied current controllers were tested with the experimental set-up presented in Fig. 1. The generic architecture of all these controllers includes the current controller itself, the AD (Analog-to-Digital) and DA (Digital to Analog) converter interfaces and the RS232 serial Universal Asynchronous Receiver Transmitter (UART) interface, leading to a full SoC integration. Numerous experimental results are presented, which clearly illustrates the benefits and the effectiveness of the proposed FPGA-based current controllers.

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Rectifier

3-phases VSI

AC machine

400V/50Hz

E isa isb A/D

Sa Sb Sc RS232

RS232

UART

Host PC

Scope

D/A

Current controller

DA Interface

AD Interface

θdq

Encoder

FPGA

Fig. 1. Synoptic of the experimental set-up

II.

FPGA DESIGN METHODOLOGY

FPGA technology allows developing specific hardware architecture within a flexible programmable environment. Comparing to standard architecture of microprocessors and DSPs, this specificity of FPGAs gives to the designer a new degree of freedom since he can build dedicated hardware architectures that match all the requirements in terms of control performances and implementation constraints. Thus, these dedicated architectures are designed on the basis of a perfect adequation between the control algorithm to be implemented and its final hardware realization, allowing for example to preserve all the potential parallelism of the chosen algorithm. However, in many cases, the design of FPGA-based controller architectures is rather intuitive and require from the designer to master several different knowledges (micro-electronics, control and electrical machines theories). It is particularly true for complex algorithm structures such as the ones found in drive control applications. This naturally leads many control engineers to prefer standard implementations like DSP solution. Thus, in order to make the design of control algorithms more manageable and less intuitive, the designer has to strictly follow a set of steps and rules, which consist in an efficient design methodology. The main characteristics of this kind of methodologies are the reusability of the already made designs, the optimization of the consumed resources of the targeted component, the respect of the control performances and finally the reduction of the development time. Several authors have already presented interesting design methodologies [22]-[26]. All of them are based on a friendly development procedure where reusability is always of prime importance. As it will be shown in the next paragraphs, the specificity of the proposed methodology depends on the fact that it has been designed having always in mind that the control engineer is not a micro-electronics expert. That is the reason why, an important part of the design steps is achieved within the Simulink-Matlab friendly environment. However, another key-point is that priority is given to the respect of control performances and as a consequence the final hardware architecture needs to be optimized. Therefore, using Matlab does not means here, that the VHDL (Very high speed integrated circuit Hardware Description Language) [27] code is automatically generated with toolboxes proposed by the main FPGA manufacturers, since it necessarily leads to an unoptimized solution in terms of consumed resources. Hence, in the proposed approach, the designer has to code 3 his own architecture in VHDL but he is strongly helped by the Algorithm Architecture Adequation (A ) [28] technique as explained later. As a conclusion, this design methodology is a balanced solution between two opposite needs: a friendly method that does not afraid the non-expert designer and the respect of control performance requirements that necessarily leads to substantial efforts during the design procedure. The main steps of the design methodology are now presented.

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A. Modular Partitioning of the Control Algorithm

This step is crucial when working on complex algorithms. It is aimed to reduce the design cycle also called “time to market”. It consists in partitioning the whole control algorithm into sub-parts called modules, which are easier to develop and, which make sense from a functional point of view. This can be done by identification and extraction of several reusable and independent modules such as regulators, modulation functions, estimators and vector operators according to the hierarchy and regularity concepts [5]. Hierarchy is used to divide a large or complex design into sub-parts that are more manageable. Regularity is aimed to maximize the reuse of already designed modules.

Current control, Torque control, Speed control… Full control algorithms PI, PID, Hysteresis controller… Regulation

PWM, SVM…

PLL, Torque estimator, Flux estimator…

abc-to-αβ, αβ-to-abc, abc-to-dq, dq-to-abc … Vector operators

Estimation Registers, multiplexers, demultiplexers… Basic operators

LEVEL 3

Modulation

Adder, multipiler, sine-cosine, cordic… Arithmetic operators

LEVEL 2

LEVEL 1

Fig. 2. Specific library of reusable modules

However, in the same time, the designer has to also verify that the chosen algorithm modular partitioning satisfies the integration criterion. This criterion consists in the fact that the implementation process is constrained by the hardware resources of the targeted component. As it will be shown later, an optimization procedure is driven to this purpose [28]. It leads to consume less hardware resources. However, as it is applied separately to each extracted module, greater is the number of extracted modules, lower is the level of performances in terms of hardware resources consumption. Therefore, if the hardware constraints are not satisfied, designer has to reduce the number of extracted modules, even if a certain degree of reusability is lost. As a result, different reusable modules, with different levels of abstraction, can be extracted and added to a specific library of control of electrical systems. This library, available in [29] but still under construction, is constituted of three main hierarchical levels as shown in Fig. 2. From the experience of the authors, these three hierarchical levels are sufficient to fully characterize the different functions used in the control of electrical systems. The first or lowest hierarchical level includes fine grain operators such as registers, and arithmetic operators (adders, multipliers,…). The second or middle level comprises the modules of the most common used functions in the control of electrical systems such as anti-windup Proportional Integral (PI) controller, Pulse Width Modulations (PWM), (abc-to-dq) transformation,… These modules are built using the first level operators. Finally, the whole control algorithms constitute the third or highest hierarchical level of the library. These blocks are developed using both first and second level modules.

B.

Simulation and Algorithm Refinement Procedures

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As mentioned earlier, the simulation procedure is performed under Matlab-Simulink software environment. It is aimed to: - Verify the functionality of the complete control application, - Find the suitable sampling period and fixed-point format refinement for each control variables according to the needed control performance constraints. The functionality verification can be achieved by the development of a functional model using Simulink time-continuous blocks. Then, the parametrization of the per unit digital algorithm is performed by studying the influence of the sampling period and the effects of the chosen fixed-point format. Note that, the choice of the fixed-point format can be derived from adapted methods [30], [31]. At this level, the simulation is realized by the development of a digital fixed-point specification model using System Generator toolbox [32]. A Data Flow Graph (DFG) is then defined for each extracted second level module. DFG is a graphical representation of the algorithm, which includes no timing specifications regarding its expected implementation. It is composed of nodes and edges. Each node represents a simple arithmetic operation or a simple mathematical or logical function and each edge corresponds to a data transfer. For example Fig. 4(a) shows the DFG of a simple 2nd level algorithm characterized by the following simple function

y(t)=A1x1(t)+A2x2(t)

(1)

As it can be seen in the associated DFG, the two multiplications can be performed in parallel mode, but the addition depends on the results of the two multiplications and consequently must be done only when the multiplications are achieved. Therefore, DFG clearly shows the data dependencies and the potential parallelism of the considered algorithm. Fig. 3 represents the different mentioned steps. It can be noted that, up to now, no choice has been made regarding the targeted component since modular partitioning and fixed-point refinement is also applicable to DSP-controllers [33].

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Control Algorithm  Reusability  Regularity  Integration criterion

Modular Partitioning

Module 1

Module 2

Module (k-1)

Module k

Simulink Blocks

Simulation Simulink

Functional model

 Verification of the complete application functionality

System Generator

Specification model

 Choice of the fixed point formats and sampling period

Matlab Simulink FPGA Blocks

nd

st

1 Level Library

DFG 1

DFG 2

DFG(k-1)

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DFG k

Data Flow Graphs

Fig. 3. Development of DFGs

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Optimization Procedure

The optimization procedure is based on the A3 methodology [28]. The aim of this methodology, when applied to FPGAbased designs, is to find out an optimized hardware architecture for a given application algorithm, while satisfying size and timing constraints. In each DFG, some operations are used several times. If an operator is repeated n times, the A3 factorization process applied to this operator consists in keeping only m realizations of this operator with m < n. Most of the time m is equal to one. Operator has to be understood here as the hardware support of a given operation. The A3 methodology is generally applied to the greediest operators in terms of hardware consumed resources like multipliers. The result of the DFG factorization is the Factorized Data Flow Graph (FDFG). x1(t)

A1

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x2(t) s[n/Q(n-1)]

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Defactorization

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s[n/Q(n-1)] A1 s[n/Q(n-1)] s[n/Q(n-1)] x F s[n/Q(n-1)] s[n/Q(n-1)] F A2 x2(t) s[n/Q(n-1)] x1(t)

J s[n/Q(n-1)]

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s[n/Q(n-1)] +

s[n/Q(n-1)] F : Fork J : Join

y(t)

(a)

(b)

Fig. 4. Example y(t)=A1x1(t)+A2x2(t) (a) DFG (b) FDFG For example, Fig. 4(b) presents a FDFG example where the factorization process is applied to the multiplier operator. Note that, the factorization process reduces the hardware consumed resources, but increases the computation time. The final graph, which will be used for the design of the hardware architecture, is thus the result of a compromise between computation time and hardware consumed resources amount. For many electrical system controllers the used sampling period is much greater than the computation time delay. In these cases, objective number one is the reduction of the hardware consumed resources.

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D. Modular Hardware Architecture Design

A data-path and a control unit are defined for each module of the library. The data-path of the architecture is always obtained by replacing each node of the final graph with its corresponding operator and every edge with a data bus between operators. Data bus transfers are managed by a control unit, which is a simple Finite State Machine (FSM). Fig. 5(a) and Fig. 5(b) present the architecture corresponding respectively to the DFG and FDFG of Fig. 4. It can be noted that the obtained data-paths are the quasi-copies of their corresponding graphs and that the latency of the factorized architecture is greater than the defactorized one. x1[k] x2[k]

en0

en0

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Fig. 5. Derived architectures from (a) DFG (b) FDFG

Each developed module of the library is characterized by its inputs and outputs formats, degree of reusability, latency and communication protocol. All these specifications must be clearly indicated in data-sheets for easy reuse of the developed modules architectures. Fig. 6 presents the general structure of reusable module architecture corresponding to a second hierarchical level. The data-path is made of elementary operators such as adder, multiplier, multiplexer, register,… The data transfers between these elementary operators are managed by a control unit, which is synchronized with the clock signal (Clk). The control unit of a module is always activated via a Start pulse signal. When the computation time process is over, an End pulse element signal indicates to the global control unit that the data outputs of the module are ready to be used.

S1

Start

S4

Latency*TClk S2

S3

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Clk Start Input Data

Input Data Reset Clk

Output Data Data-path

TClk

Inputs(k)

Inputs (k+1)

Inputs (k+2)

End Output Data

Outputs (k)

Outputs (k+1)

Module name (b)

(a)

Fig. 6. (a) Generic module architecture (b) Timing diagram of the module

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Outputs (k+2)

As for the development of the hardware architecture of a third hierarchical level module, it is performed using the blocks of the first and second hierarchical levels of the library. The data-path is therefore a combination of the instantiations of second and first level modules, which are linked with data-buses. At this level, the architectures of the second hierarchical level modules can be considered as thick grain operators. An A3 factorization process can be once again applied to these thick operators. For example, if the control algorithm includes two PI controllers, the designer can freely choose to use only one factorized PI controller. The second level modules are easy to handle thanks to their Start and End flags. The coordination between these modules is done by a global control unit that activates their local control units at well defined moments as shown in Fig. 7. The global control unit is also activated by a Start pulse signal and generates an End pulse signal when the computation of the data outputs is finished. With such structure, the third level module can be also managed in the same way inside an upper hierarchical level architecture. The architecture of each hierarchical level module is then coded via a structural approach with an hardware description language such as VHDL.

Start

Global Control Unit Start1

End1

Start2

End2

Sel

Start3

End3

End en

Startn

Endn

Sub-Module 1 Input

M

Sub-Module n

Output

Sub-Module 3 Sub-Module 2

U

Global Data-path

Reset

Module Name

Clk

Fig. 7. Architecture of a 3rd hierarchical level module of the library

E.

Validation of the Designed Architecture

The first validation step is a co-simulation procedure performed using Modelsim and Matlab software tools. This step allows verifying the good functionality of the designed architecture written in VHDL by testing it with a relevant set of testbench input waveforms. The second validation step, at system level, is done via an hardware in the loop procedure. This procedure is aimed to ensure a first experimental attempt guarantee. It is carried out through the hardware implementation of a test architecture, which is composed of three main modules (See Fig. 8). The first one generates the stimuli patterns, which are stored in FPGA memory blocks. These stimuli patterns are directly derived from the simulation phase, enabling further comparisons with the simulated system. The second module is the architecture to be tested and the third module is a communication interface module that manages a communication link between the FPGA and a host PC. The computed outputs of the architecture to be tested are gathered and sent to the host PC by the communication interface module in order to be compared, in the graphical environment of Matlab, to the simulation results. Once this test procedure is validated, the designed architecture is ready for its actual environment. Stimuli Patterns (Simulation)

Architecture to be tested FPGA Target

Configuration link

Fig. 8. Hardware in the loop procedure

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Communication Interface

In the next sections, the design of a set of FPGA-based current controllers for AC machine drives applications is going to be presented. These current controllers are ON-OFF current regulators, PI current controller and predictive current controller. All these controllers are realized with the help of the proposed design methodology and in each case benefits and performances of FPGA implementations are presented and discussed.

III. CURRENT CONTROL OF AC MACHINE DRIVES BASED ON ON-OFF REGULATORS The ON-OFF current control strategies are the simplest current regulation schemes used for the current control of AC machines. They can be classified into two main groups. The first one is based on hysteresis comparators and is characterized by a variable switching frequency [34]. The second one is a special class of the ON-OFF current regulators, which is based on the delta modulation principle [34], [35] and characterized by a limited switching frequency. In the following, the FPGA implementation of AC machine drives current controllers based on these two classes of ON-OFF regulators is analyzed. Specificities of an FPGA implementation solution are also discussed. A. Current Control of AC Machine Drives Based on Variable Switching Frequency ON-OFF Regulators The aim of current controllers based on variable switching frequency ON-OFF regulators is to keep the instantaneous current inside a tolerance band with regard to the reference current. In this paragraph, the FPGA implementation of a space vector based ON-OFF regulator is presented and discussed. The corresponding block scheme is shown in Fig.9. It consists into a space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame. *

isb * isc isa

isb isc

isα

* *

*

*

abc αβ

Δisα

+

Δisβ

Sβ

(X, X) : Sα Sβ levels X : -1, 0, 1

E

Table

-Δhα/2 +Δhα/2

β

Sa

Sα

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* isβ +

isb isc

|Δisb|< |Δisc|

(-1,1)

Sb

(0,1)

Sc

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Δis

Δisβ

isα isβ

αβ abc

(1,1)

(0,0) (1,0)

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isa isb isc

(-1,-1)

is

(0,-1)

(1,-1)

*

is

AC Machine

Δisα α

(a)

(b)

Fig. 9. Current control of AC machine drives based on variable switching frequency ON-OFF regulators (a) Block scheme of a space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame (b) Corresponding current error locus

The implementation of such current control techniques is generally made using analog technology. In fact, the instantaneous response of analog controllers allows the vector of the current error to stay within the expected limits. The sensed currents are firstly converted by AD converters and then the switching states resulting from hysteresis comparison are computed digitally. So, if the whole execution time, including analog-to-digital time conversion, is consequent, the current error will exceed the hysteresis band limits. Nevertheless, these current control techniques can also be performed using digital technology such as FPGAs. Indeed, when associated to fast analog-to-digital converters, the high computation capabilities of FPGAs allow avoiding any additional delays within the feedback loops as it will be shown in the next paragraph. 1) FPGA Implementation of Current Control Techniques Based on Variable Switching Frequency ON-OFF Regulators: Fig. 10 presents the developed hardware architecture corresponding to the current control algorithm presented in Fig. 9. The architecture presented in Fig. 10 is the result of a modular partitioning, which includes four second level modules. Among them, two reusable modules can be extracted: the (abc-to-αβ) transformation and the three level hysteresis comparator. It can be noted that, in this architecture, the (abc-to-αβ) transformation module is used two times. A

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factorization process could therefore be applied to this module if the hardware constraints of the FPGA target were not satisfied. Start

Global control unit

End

Clk

End_OO

Start_OO ON-OFF Current controller

Start_AD

End_AD *

isaAD

AD Interface

isbAD AD Control Clk

isc isb isa

End=’1’

Algorithm control unit Clk

isa * isb isc

Global control unit FSM Reset

isα abc-to-αβ

*

*

Clk

Clk

Sα

3 level hysteresis comparators

* isβ

isα

abc-to-αβ

End_AD=’1’

wait

Sβ

Start=’1’

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Table

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Start_AD=’1’ Start_OO=’1’

S

|Δisb|