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FPGA Physical-Design Automation using Model-Driven Engineering Ciprian Teodorov

Damien Picard

Lo¨ıc Lagadec

Lab-STICC MOCS, CNRS UMR 3192 Universit´e de Bretagne Occidentale Brest, France Email: [email protected]

LISyC, UBO Universit´e Europ´eenne de Bretagne Brest, France Email: [email protected]

Lab-STICC MOCS, CNRS UMR 3192 Universit´e de Bretagne Occidentale Brest, France Email: [email protected]

Abstract—The physical design automation is a difficult problem due to the huge number of devices, and physical constraints to be met. The Model-Driven Engineering (MDE) approach aims to tackle the complexity of software development using a high level method based on models and transformations. While this approach is used for High-Level circuit synthesis there is no work reported on the lower part of the circuit design automation flow, namely the physical-design automation. In this work, we use the MDE approach to model the physical synthesis process with a focus mainly on reconfigurable architectures. We present a model for island style FPGAs along with the transformations needed in the case of the physical synthesis. The main result of this work is to show the feasibility of the MDE approach for the physical design automation problem, and we argue that this methodology enables orthogonal composition of the architecture / algorithms / application design space, that enables incremental exploration based on quantitative evaluations.

I. I NTRODUCTION Physical synthesis is a difficult problem since there is a huge number of devices and many physical constraints to be met[1], like timing, electrical routability, signal integrity, etc. Nowadays with the apparition of nanoscale devices, the problem becomes even more complicated, due to the huge integration densities of such devices, and to the high percentage of defects consequence of the bottom-up assembly process[2]. For reconfigurable architectures today, frameworks like VPR[3] and Madeo[4] enable fast prototyping and design space exploration by offering a generic infrastructure for FPGA physical design. Proprietary domain-specific languages (DSL) are used for architecture specification. The application netlists are mapped automatically using proved algorithms and heuristics. Moreover they provide viable alternative to vendor specific tools, and drive innovation by opening the toolbox and providing an infrastructure for architecture-specific tuning. Their use in the context of novel architectures based on emerging nanoscale devices, like NanoPLA[5], and NASIC[6] demonstrate the generality and extensibility they are supporting. But, from a software engineering perspective, none of these tools have a simple way of plugging-in new algorithms. Limitation which comes principally from the lack of isolation between the different concerns modeled, most notably there is

a circular dependence between the architectural models and the physical design algorithms. The architecture models include details specific to the physical design algorithms implemented, and the physical design algorithms strongly depend on the architectural model. This limitation directly impacts the software development costs, and limits the extent of algorithmic exploration. While, during the last years, the model-driven engineering (MDE)[7] methodology has been adopted as a generic and scalable solution for application high-level synthesis (HLS), in the context of SoC[8], hardware accelerator design[9] and embedded systems in general. At the physical design level, to the best of our knowledge, there are no tools using this methodology. One reason is that while the HLS flow is seen mainly as a compilation flow, that can be easily interpreted using models and simple model transformations. The physical synthesis is a complex resource allocation problem, which supposes more complex model transformations, that cannot be implemented using today transformation engines like ATL1 [10], QVT2 [11], due to lack of expressiveness or efficiency. But we argue that if not anything else at least as a metaphor the MDE approach is very useful at the physical design level to provide better abstraction, decomposition and separation of concerns. In this study, we propose a model based approach relying on specific components in the physical design automation field and external libraries coming from various providers. The idea is to use the MDE methodology to create a physical design automation CAD flow, which decouples the application and architecture design from the software tool design and implementation. By allowing a clear specification of concepts and relations between them, MDE helps to reduce complexity of developing and maintaining physical design tools. This study starts by introducing MDE and presenting the state of the art application design automation using MDE approach, in Section II. In Section III-A we provide a generic meta-model for describing hierarchical interconnected systems. In the context of this paper, we are extending this model for specifying a simplified view of the island-style 1 ATLAS

Transformation Language

2 Query/View/Transformation

FPGAs (ArchM) (Section III-B), and a combinatorial application model (AppM) (Section III-C). Then, in Section IV, the physical synthesis is defined using a MDE approach as a mapping transformation of a AppM instance on an ArchM instance. The approach is presented in details via a case study of the routing step in Section V. Section VI concludes this study presenting the advantages of the approach and future research directions. II. R ELATED W ORKS Model-driven paradigm provides a methodology to tackle the complexity of software development using abstraction, problem decomposition, and separation of concerns. This methodology places models and transformations at the center of the software system development. A model can be seen as an abstract and simplified way to describe and understand complex systems. According to [12] a transformation is the automatic generation of one(or more) target model(s) from one(or more) source model(s), according to a transformation definition. A transformation definition is a set of rules that together describe how a model in the source language can be transformed into a model in the target language. The massive adoption of the model-driven paradigm was favored principally by the standardization of Unified Modeling Language (UML) and Model-Driven Architecture(MDA) by the Object Management Group (OMG)[13]. The circuit design automation problem is typically decomposed in two parts: high-level synthesis, and physical synthesis. The high-level synthesis(HLS) tools automatically convert behavioral descriptions of the system into optimized registertransfer level (RTL) designs, described using languages like VHDL or Verilog, which are compiled to technology-specific logic netlists. The physical-synthesis tools are used to map the technology mapped netlists to physical circuits. In the context of this article we are looking at FPGA physical synthesis flow, which is composed of the following principal steps: partitioning, floorplanning, placement, and routing. UML extensions (profiles) such as SysML[14], Embedded UML[15], and MARTE[16] have been proposed for the embedded system design. These profiles allow the specification of systems using high-level models, and low level (i.e. VHDL) code is generated by mapping UML concepts with the target language syntax. In [8], [9], for example, the authors propose a HLS and design space exploration flow based on the MDE methodology, which based on successive refinement of the high-level model generates VHDL hardware accelerators. For FPGA physical-synthesis, a number of tools like VPR[3] and Madeo[4] aim at providing generic frameworks targeting reconfigurable architecture. They are based on highlevel models, which ease the architecture and application description (based on specific DSLs[17]), and using generic heuristics (simulated annealing[18] - placement) and algorithms (Pathfinder[19] - routing) they automate the application mapping on the FPGA architectures. The principal limitation of these tools is that they do not provide a simple way

for plugging in different algorithms from the ones already implemented. III. P ROPOSED M ETAMODEL In this section we describe the generic meta-model used for modeling different concepts characteristic to physical design automation. Only a high-level view focusing on the main concepts are presented. This model then is extended with concepts capturing FPGA architectures characteristics, and combinatorial applications. A. Generic Metamodel At the high abstraction level we structurally describe our domain as a hierarchical composition of primitive elements interconnected together. In the circuit design automation field this kind of hierarchical representation is very common and is used at different abstraction levels. Some examples are: application netlist description, device level architecture description, switch level architecture description, logic level description etc.

Fig. 1.

A view of the core structure of the proposed meta-model

In the proposed meta-model, see Fig. 1, the domain structure is captured as a MHComposite that contains one or more MHEntity instances (called ”entities” from now on). MHEntity is an abstract construct specialized as MHLeaf and MHComposite. The MHLeaf instances are domain primitives which are viewed as the indivisible building blocks of more sophisticated structures. The entities have hooks (MHHook) which provide an external interface through which they can be interconnected together. The abstract MHHook concept is specialized as MHPin and MHPort. The MHPin element allows connection between entities. It can be a physical contact, or a logical interface depending on the specification level or on the refinement degree. The role of MHPort instances is to group together and structure the MHPin instances, they can be seen as namespaces structuring the access to particular pins. The MHConnection purpose is to glue together the entities of a particular system by linking pins together. These connections can be interpreted as wires, communication channels, or simply as relations between entities.

All these concepts are refinements of the MHClass element which owns MHProperty instances. The MHProperty represent different attributes particular to the modeled domain. Some examples of properties are: the position of an entity on a layout, the capacity or resistance of a wire modeled as a MHConnection instance, the logical value of a circuit pin represented as a MHPin instance. The meta-model, presented in Fig. 1, represents a common abstraction which can be used to specify any kind of interconnected system having any number of hierarchical components that present the system at different abstraction levels. At this abstraction level we present just a generic view of the meta-model (the core structure) without getting into domain specific details. This core structure is refined in section III-B to describe an island-style FPGA architecture and in section III-C to capture the characteristics of a combinatorial circuit.

bricks which are replicated regularly to form a Cluster. The primitive’s pins are aliased at the tile level and cluster level, using InterfacePin instances, to expose the possible connection points.

B. Island style FPGA model

Fig. 3 presents a view of the principal types of internal connections. HardConnect can be seen as a direct connection between components without any physical properties (it is used for example to represent long wires which logically are composed of different wire segments, the connection between these wire segments is a HardConnect instance). Wire represents a physical wire. ProgrammableConnect is an abstract representation of electrically configurable components. The configuration state for these components is controlled by an instance of AbstractController, which implements a configuration state machine. The FPGA meta-model (ArchM) presented in this section is not intended to exhaustively cover the programmable architecture design concepts, nor to be used as a real-life FPGA meta-model but rather is a simplified version that capture the basic properties of interest for the purpose of this study.

The Field Programmable Gate Array (FPGA) is a flexible computing architecture that bridges the gap between Application Specific Integrated Circuits (ASIC) and General Purpose Processors(GPP). FPGA designs trade the performance of ASICs for flexibility and fabrication costs[20]. The basic structure of a FPGA is a regular mesh of logic blocks interconnected by a reconfigurable routing architecture. In the case of Island-style FPGAs the routing resources are evenly distributed throughout the mesh, the logic block usually having routing channels all around. 3

Fig. 3.

Connection hierarchy

C. Combinatorial Logic Meta-Model In this section we present another refinement of the metamodel presented in section III-A, this time with the purpose to hierarchically describe combinatorial logic. This meta-model (AppM), presented in Fig. 4, uses two-level single-output logic functions (LogicGate) to model the application netlist. Fig. 2. A simplified view of the Island-style FPGA extension of the core meta-model

To capture the particularities of FPGA architecture, the meta-model presented in the last section was refined, as it can be seen in Fig. 2. Using this meta-model the FPGAs are modeled based on 3 primitives (specializations of MHLeaf): Logic Block, Switch, and Connection Block. LogicBlock instances represent the programmable logic blocks which provide the basic computation and storage elements. The routing architecture is modeled using Switch and ConnectionBlock instances. These primitives contain a number of internalConnections that specify the way their pins are connected internally (see Fig. 3). Tile instances aggregate these primitives into logical 3 In

the scope of this paper when we say FPGA we are actually meaning Island-style FPGA

Fig. 4.

Combinatorial Logic extension of the core meta-model

As for the FPGA model, presented in the last section, only a simplified view of Combinatorial Logic meta-model is presented.

IV. T RANSFORMATIONS - BASED P HYSICAL SYNTHESIS This section presents an automated physical synthesis design flow targeting FPGA architectures. The inputs are the description of a particular FPGA architecture as an ArchM instance, and combinational circuit as an AppM instance. These models are domain specific models completely independent from any algorithms that are used for physical synthesis. The output is a refined ArchM instance, configured to implement the AppM instance. The flow is an endogenous transformation realized via four composite transformations (see Fig. 5): partitioning, floorplanning, placement, and routing. Each of these four transformations is a composition of more-elementary transformations. Thus, the physical synthesis tool flow is a hierarchical directed acyclic graph (DAG) of transformations, where the nodes represent the transformations to be done and the edges represent the dependencies between the tools. The execution of the transformations happens in topological order from the DAG inputs (ArchM and AppM instances) to the outputs (AppM instance mapped on the ArchM instance). The transformations used to implement the flow are classified in two categories: concern extraction, and complex transformations. The concern extraction represents the mapping between architectural (application) model to simpler structures required by the different concerns of the physical synthesis flow (placement, routing, etc). The purpose of the concern extraction is to decouple the domain specific details of the model from the required aspects of the algorithms used. For example in the ArchM we have capacitance, resistance informations related to the physical devices used to build up the architectural instance. But for computing the Delay of a path, during the routing step, the router framework needs just the delay of the elements in the routing graph. This delay can be computed once during the Routing Ressource Graph generation using the physical parameters[3], and then used by the routing transformation. The complex transformations are either the composite transformations, or the sophisticated transformations needed for implementing the algorithms and/or heuristics of the physical synthesis flow (placement, routing algorithms). While the concern extraction can be implemented using transformation engines like ATL[10] or QVT[11], some of the complex transformations are implemented using external tools - which are highly optimized for the problem at hand. The principal advantage of this flow is the capacity to easily replace any of the physical synthesis algorithms with different implementations, with no constraints on the implementation language or formalism. For example, Madeo framework[4] is used for floorplanning and routing, while the VPR tool[3] is used for placement. But this also has a drawback, the high number of simple transformations (concern extraction) needed to implement the flow. However, such a view of the physical design automation, that isolates and encapsulates the different steps of the flow, poses the bases for future standardizations which can limit the number of intermediate transformations

needed. In the next section we will present the details of the routing transformation. V. C ASE STUDY - ROUTING The FPGA routing architecture can be modeled with a routing graph Gr (Vr , Er )[19], [3], which is a directed graph. The vertex set Vr represents the input and output pins of logic modules, and the wire segments. The edge set Er represents the possible connections between the nodes. The nets to be routed are directed hyper-edges on Gr , (si , tji )1≤j≤n , where si and tji represents the source, and respectively the sinks of the net i. A net routed corresponds to a subtree of Gr , called the routing tree for the net. The root of the routing tree corresponds to an output pin (in the FPGA architecture) and is the source of the net. The leafs of the tree are input pins of logic blocks, and correspond to the sinks of the net. Since an electrical path cannot be shared by different signals the routing trees for the nets should be vertex disjoint, this is called the exclusivity constraint[21]. The routing problem can be stated as finding vertex disjoint routing trees in Gr for all nets while satisfying performance constraints. In the context of this section we consider a timing-driven router based on the Pathfinder algorithm[19]. For timing calculations we use Elmore delay model[22], that uses the RC values specified by the architecture to compute the sourceto-sink delay. In timing-driven routing, the timing constraints are specified as arrival time (At ) and required time (Rt ) at primary inputs or outputs of storage elements. A timing graph, Gt (Vt , Et ), is created from the placed application netlist to represent these informations. The goal of the timing-driven routing problem is to route all nets such that the delay on the critical path is minimized while satisfying the delay and exclusivity constraints. From the MDE perspective, the routing problem is a refinement of the partial ArchM instance. This refinement consists in the identification of the routing paths in the ArchM instance for the nets from the AppM instance. The transformations required to solve the routing problem are classified in 3 categories: pre-routing transformations, core routing, and postrouting transformations. The pre-routing transformations, are a preprocessing step that identifies and extracts the elements directly needed by the core routing transformation, Gr , Gt , and the nets in our case. The pre-routing transformations are simple transformations, concern extraction (as we called them in the last section), that can be implemented using transformation engines. The RRGraph extraction transformation creates the routing graph Gr from the ArchM instance. It also computes the delay for the possible connections by applying the delay model on the RC parameters of the ArchM instance. The nets are extracted from the AppM instance using the placement results to identify the architectural elements corresponding to source and sinks. A partial instance of the timing graph is created

Application Model Physical Synthesis Flow Partitioning Net2PGraph

Floorplan

Partitioning Algo

Partitions

Net2FPModel

Placement Floorplanning Algo

FP Result

Net2PlaceModel

Routing Placement Algo

Placed

Net2RouteModel Routing Algo

Arch2PGraph

Arch2FPModel

Arch2PlaceModel

Architecture Model

Fig. 5.

Arch2RouteModel

Placed And Routed Architecture

The proposed physical synthesis flow. The rectangles represent models, the ellipses and the composite boxes represent transformations.

Gt from the placement results and the AppM instance. We call Gt a partial instance because the delays of the routing paths between the logic blocks are not known, being computed during the core routing transformation.

FPGA Model

Placed App Model

RRGraph Extraction

Nets Extraction

RRGraph

Nets

Application Model

TGraph Extraction

TGraph

update costs Pathfinder

routing, in the case of Pathfinder, is to produce the routed nets according to the timing and exclusivity constraints, to refine the timing graph model, by adding the cost of the routing paths, and to update the costs of the routing resources in Gr , since the exclusivity constraint is solved by resource negotiation. Once the core-routing transformation done, the post-routing transformation refines the ArchM instance injecting the routed nets in the model. The ArchM instance obtained represents the solution of the physical synthesis flow, the mapping of the AppM instance on the architecture. Using this methodology we were able to experiment three different routing algorithms: •

Signal Routing

• add AT

Temporary Routes

add RT

• •

Arrival Time TGraph Refinement

Required Time TGraph Refinement

Final Routes

Post-routing FPGA Model Refinement

Routed FPGA Model

the timing-driven pathfinder, described in this paper; a routability-driven router realized by removing, from the flow in Fig. 6, the T GraphExtraction, AT Ref inement and RT Ref inement transformations; a lagrangian-relaxation based timing-driven router[23]; the pathfinder-based router implemented in the VPR tool[3].

In the case of the VPR tool, the pre-routing transformations create an instance of the VPR architectural model using the XML-based description language, and a netlist using the .net file format needed by the VPR tool. The post-routing transformation reads the routing results file and injects the routes in the initial ArchM model instance. This shows that core-routing transformation, the Pathfinder router in the example, can be easily replaced by any other domain independent tool having the required functionality. Moreover this result is valid for all the other core algorithms needed in the physical synthesis flow, presented in the last section. VI. C ONCLUSION AND F UTURE W ORK

Fig. 6. DAG representation of the composite routing transformation. The ellipses represent primitive transformations. The core-routing transformation is shown as the shaded area. Dotted lines represent model refinement (cost update, property injection), they do not alter the DAG structure, but represent updates of shared models

The core routing transformation, is a composite transformation (see Fig. 6) of the main algorithmic aspects of the routing problem. For the timing-driven pathfinder algorithm these aspects are: signal routing, and timing graph refinement. If these aspects are treated as transformations, they can be implemented apart from the core algorithm, thus decomposing the routing problem event further. The principal roles of the

To tame the complexity of current VLSI designs, MDE slowly became the enabling software design methodology for covering the large design space and ensuring the convergence of the design flow. But even though model-based approaches are used for many aspects of embedded system design, HLS and SoC, to date there are no reported works on MDE-based physical design tools. In this study we have presented a generic meta-model for describing hierarchical interconnected systems with arbitrary abstraction levels. This model was extended to model islandstyle FPGAs and combinatorial logic applications. Based on

these two meta-models we present a Model-Driven Engineering approach for the FPGA physical synthesis tool-flow. We showed, that the application of the MDE methodology to physical synthesis decouples the algorithm implementation aspects from the architecture, and application modeling. This improves the design-space exploration by offering an orthogonal view of the architecture/application/algorithms concerns and directly enables algorithm reutilization as plugins. Based on the experience with the Madeo[4] project, currently we are working on reengineering its physical synthesis back-end based on these concepts, to free the architecture designers from the high-cost software tool implementation, to ease the understanding and the implementation of physical design algorithms by isolating them from the architectural details, and to offer an one stop-shopping point for unbiased design space exploration.

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