FPGA Realizations of High Speed Switching-Type ...

FPGA Realizations of High Speed Switching-Type Chaotic Oscillators Using Compact VHDL Codes Talal Bonny1 and Ahmed S. Elwakil2 Department of Electrical and Computer Engineering College of Engineering, University of Sharjah PO Box 27272, Sharjah, United Arab Emirates e-mail: {tbonny, elwakil}sharjah.ac.ae

Abstract This paper introduces high speed FPGA implementations of two different chaotic systems that rely on a switching-type nonlinearity. In particular, the single-switch Jerk system and the two-wing butterfly system (previously implemented only in analog form) are realized on a modular FPGA platform. For each system, two different hardware architectures are described; a parameters-independent non-optimized architecture and a customized one with fixed parameters that utilizes less FPGA resources and thus has high throughput with the minimum number of clock cycles. Experimental results show that the parameters-independent architecture utilizes 70% more of the FPGA resources while the customized one achieves a maximum clock frequency 172.5 MHz for the Jerk and 142.6 MHz for the two-wing system. Keywords: Switching-type chaotic oscillators, Digital chaos generation, FPGA 1. Introduction Over the years, numerous chaotic oscillator systems have been introduced in the literature [1]-[3]. The complexity of these systems varies from those using passive nonlinear devices (such as diodes or transistors) [1]-[3] to real1

Corresponding author Nanoelectronics Integrated Systems Center (NISC), Nile University, Cairo, Egypt ([email protected]) 2

Corresponding
Author The
corresponding
author
is
Talal
Bonny. Funding This
research
did
not
receive
any
specific
grant
from
funding
agencies
in
the
public,
commercial,
or
not-for-profit
sectors. Conflict
of
Interest The
authors
declare
that
they
have
no
conflict
of
interest. References [1]
A.
S.
Elwakil
and
M.
P.
Kennedy,
Chua’s
circuit
decomposition:
A
systematic
design
approach
for
autonomous
chaotic
oscillators,
J.
Franklin
Institute,
vol.
337,
pp.
251-265,
2000. [2]
A.
S.
Elwakil
and
M.
P.
Kennedy,
Construction
of
classes
of
circuitindependent
chaotic
oscillators
using
passive-only
nonlinear
devices,
IEEE
Trans.
Circuits
and
Syst.-I,
vol.
48,
pp.
289-307,
2001. [3]
A.
S.
Elwakil,
Integrator-based
circuit-independent
chaotic
oscillator
structure,
Chaos,
vol.
14,
pp.
364-369,
2004. [4]
E.
Tlelo-Cuautle,
A.
Gaona-Hernndez
and
J.
Garca-Delgado,
Implementation
of
a
chaotic
oscillator
by
designing
Chuas
diode
with
CMOS
CFOAs,
Analog
Integrated
Circuits
and
Signal
Processing,
vol.
48,
no.
8,
pp.
159-162,
2006. [5]
A.
S.
Elwakil,
K.
N.
Salama
and
M.
P.
Kennedy,
An
equation
for
generating
chaos
and
its
monolithic
implementation,
Int.
J.
Bifurcation
and
Chaos,
vol.
12,
pp.
2885-2895,
2002. [6]
S.
Ozoguz
and
A.
S.
Elwakil,
On
the
realization
of
circuit-independent
nonautonomous
pulse-excited
chaotic
oscillator
circuits,
IEEE
Trans.
Circuits
and
Syst.-II,
vol.
51,
pp.
552-556,
2004. 26

[7] A. S. Elwakil, Clock-driven chaotic pulse-width generators: An overview and demonstration of power supply attack, Int. J. Bifurcation and Chaos, vol. 24, no. 6, pp. 1450079-1450086, 2014. [8] S. Ozoguz, A. S. Elwakil and S. Ergun, Cross-coupled chaotic oscillators and application to random bit generation, IEE Circuits Devices and Syst., vol. 153, pp. 506-510, Oct. 2006. [9] M. L. Barakat, A. S. Mansingka, A. G. Radwan and K. N. Salama, Hardware stream cipher with controllable chaos generator for colour image encryption, IET Image Processing, vol. 8, no. 1, pp. 33-43, 2014. [10] P. K. Shukla, A. Khare, M. A. Rizvi, S. Stalin and S. Kumar, Applied cryptography using chaos function for fast digital logic-based systems in ubiquitous computing, Entropy, vol. 17, pp. 1387-1410, 2015. [11] M. F. Tolba, A. M. AbdelAty, N. S. Soliman, L. A. Said, A. H. Madian, A. T Azar and A. G. Radwan, FPGA implementation of two fractional order chaotic systems, AEU-Int. J. of Electronics and Communications, vol. 78, pp. 162-172, 2017. [12] L. De Micco and H. A. Larrondo, Methodology for FPGA implementation of a chaos-based AWGN generator. Book Chapter in: FieldProgrammable Gate Array (FPGA) Technologies for High Performance Instrumentation, IGI Global, pp. 43-58, 2016 (doi:10.4018/978-1-5225-02999.ch003). [13] B. Karakaya, V. Celik and A. Gulten, Chaotic cellular neural networkbased true random number generator, Int. J. Circuit Theory and Applications, (doi: 10.1002/cta.2374), 2017. (in press) [14] C. Chen, H. Ma. H. Chen, Y. Meng and Q. Ding, FPGA implementation of a UPT chaotic signal generator for image encryption, Pacific Science Review A: Natural Science and Engineering, vol. 17, no. 3, pp. 97-102, Nov. 2015. [15] A. Abid, Q. Nasir and A. S. Elwakil, Implementation of an encrypted wireless communication system using nested chaotic maps, Int. J. Bifurcation and Chaos, vol. 20, pp. 4087-4096, Dec. 2010.

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[16] E. Tlelo-Cuautle, A. Quintas-Valles, L. de la Fraga and J. RangelMagdaleno, VHDL descriptions for the FPGA implementation of PWLfunction-based multi-scroll chaotic oscillators, PLoS ONE, vol. 11, no. 12, pp. e0168300, 2016. [17] M. Qiu, S. Yu, Y. Wen, J. Lu, J. He and Z. Lin, Design and FPGA implementation of a universal chaotic signal generator based on the Verilog HDL fixed-point algorithm and state machine control, Int. J. Bifurcation and Chaos, vol. 27, no. 3, pp. 1750040-1750055, 2017. [18] T. Bonny and J. Henkel, Efficient code compression for embedded processors, IEEE Trans. on Very Large Scale Integration Systems, vol. 16, no. 12, pp. 1696-1707, 2008. [19] J. C. Butcher, Numerical methods for ordinary differential equations, 2nd ed., John Wiley and Sons Ltd., March 2008. [20] L. Dieci, Jacobian Free Computation of Lyapunov Exponents, Journal of Dynamics and Differential Equations. vol. 14, no. 3, pp. 697-717, 2002. [21] Digilent, Inc, www.zedboard.org, 2016. [22] Inc, X.: 7 Series FPGAs Overview, vol. 1. Xilinx (2014). [23] Xilinx, Vivado design suite - hlx editions (2016).

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