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Impact of Edge Encroachment on Programming and Erasing Gate Current in NAND-Type Flash Memory Ji-Ting Liang, Student Member, IEEE, Chun-Hsing Shih, Wei Chang, Yan-Xiang Luo, Ming-Kun Huang, Nguyen Dang Chien, Wen-Fa Wu, Sau-Mou Wu, Chenhsin Lien, Riichiro Shirota, Chiu-Tsung Huang, Su Lu, and Alex Wang
Abstract—The edge encroachment of tunnel oxide is experimentally found to degrade the Fowler–Nordheim (FN) tunneling gate current of NAND-type Flash cells. This work elucidates the impact of edge encroachment on FN tunneling current for use in programming and erasing operations. The fringing field effect and tunnel oxide with trapezoidal edge are considered in the determination of physical gate current in which a conformal-mapping method is used to estimate the contribution of the fringing fields. These analytical results are confirmed using 2-D device simulations and experimental measurements. The results show that the overlapped encroachment causes an exponential degradation of intrinsic FN tunneling current. Preventing the encroachment of lateral edges resulting from overall tunnel-oxide enlargement is critical to ensuring normal programming and erasing speeds in future NAND-type Flash cells. Index Terms—Edge encroachment, Fowler–Nordheim (FN) tunneling, gate current, NAND-type Flash, tunnel oxide.
I. I NTRODUCTION
F
OR THE past decade, NAND-type Flash memory has been the mainstream of the semiconductor industry worldwide [1]. High-quality tunnel oxide is a critical component in achieving cell stability in NAND-type cells under high-field Fowler–Nordheim (FN) tunneling programming and erasing [2]–[4]. Unfortunately, abnormal edge profiles in tunnel oxide have been reported as a potential issue in scaled NAND-type cells [5]–[10]. Dispersed threshold voltage and degraded reliability are observed due to nonuniform enlargement in tunnel
Manuscript received April 7, 2010; revised October 31, 2010, November 17, 2010, and December 17, 2010; accepted December 21, 2010. Date of current version March 23, 2011. This work was supported by the Powerchip Semiconductor Corporation. The review of this brief was arranged by Editor D. Verret. J.-T. Liang, W. Chang, Y.-X. Luo, C. Lien, and R. Shirota are with National Tsing Hua University, Hsinchu 30013, Taiwan (e-mail:
[email protected];
[email protected];
[email protected];
[email protected];
[email protected]). C.-H. Shih is with the Department of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan (e-mail:
[email protected]). M.-K. Huang and N. D. Chien are with the Department of Electrical Engineering, Yuan Ze University, Taoyuan 32003, Taiwan, and also with the Department of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan (e-mail:
[email protected];
[email protected]). W.-F. Wu is with the National Nano Device Laboratories, Hsinchu 30078, Taiwan (e-mail:
[email protected]). S.-M. Wu is with the Department of Electrical Engineering, Yuan Ze University, Taoyuan 32003, Taiwan (e-mail:
[email protected]). C.-T. Huang, S. Lu, and A. Wang are with the Powerchip Semiconductor Corporation, Hsinchu 30078, Taiwan (e-mail:
[email protected];
[email protected];
[email protected]). Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2105492
oxide. Importantly, encroaching on the edges of tunnel oxides deteriorates the intrinsic characteristics of tunneling programming and erasing in memory cells. Because the influence of the edge becomes increasingly conspicuous in scaled cells, a deeper understanding of the effect that edge encroachment has on FN tunneling current is crucial to foreseeing its limitations in the future of NAND-type cell scaling. This work elucidates the impact of edge encroachment on FN tunneling current by developing analytical gate current models. Two-dimensional (2-D) device simulations [11] are first performed to explore the influence of tunnel-oxide edge profiles in the FN tunneling current of scaled memory cells. Various corner profiles are simulated to investigate the effect of the rounded curvature of the edge on variations of gate tunneling current. For reducing mathematics into a manageable level without losing physical insight, the trapezoidal edge of tunnel oxide is used in the modeling of gate FN tunneling current. Fringing field effect is considered in the determination of the physical gate tunneling current of scaled NAND cells. In this brief, the conformal-mapping method [12] is used to predict the contribution from edge fringing fields. The results of analytical FN tunneling current are confirmed by experimental measurements and 2-D device simulations. Dependences of edge encroachment on gate tunneling current are discussed to examine the scaling capability of NAND-type Flash cells under various conditions related to edge profiles.
II. E DGE E FFECTS AND A NALYTICAL M ODELS A. Edge Effects on Gate Current Fig. 1 shows the measured results of a (a) transmission electron microscopy (TEM) image and (b) gate current for the cell devices in sub-70-nm NAND-type Flash technology. The tested devices are fabricated on a p-type substrate with as-grown 8.5-nm tunnel oxide, where abnormal regrowth in the center region and enlargement of edge profiles are observed. Two types of tested devices, i.e., planar capacitor and finger capacitor, are measured to examine the effects of edge encroachment on tunnel oxide using an FN tunneling gate current. “Planar capacitor” is a typical area-type capacitor measuring 20 μm × 1000 μm in total area. “Finger capacitor” is a conventional comb-type capacitor with 1024 70-nm-wide folded fingers comprising a total area of 70 μm × 36.5 μm. By comparing the result of the finger capacitor with that of the planar capacitor in the same unit area, it is found that
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Fig. 1. (a) TEM picture of gate stack structure with as-grown 8.5-nm oxide. (b) Gate current of cell devices in sub-70-nm NAND Flash technology. “Planar capacitor” is an area-type capacitor with a total area of 20 μm × 1000 μm. “Finger capacitor” is a comb-type capacitor with 1024 70-nm-wide folded fingers for a total area of 70 μm × 36.5 μm.
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under edge encroachment. In this example, tunnel oxides with an edge thickness Th = 16 nm and an encroached width wx = 10 nm are used to represent edge-encroached tunnel-oxide profiles. Because the 2-D device simulator is performed based on unit μm, the μm-unit-associated FN tunneling current (in amperes per micrometer) is employed in all simulation plots. The total gate tunneling current can be obtained by multiplying the plotted values against a given cell length. Fig. 2(a) illustrates some radical variations in corner profiles from convex to concave, leading to mild variations in the FN tunneling current. Fig. 2(b) illustrates the simulated results of the gate tunneling current with various lateral-encroached widths. In this example, a linear edge profile with edge thickness Th = 16 nm is adopted to study the effect of encroached widths. Cell devices with larger encroached widths have more obvious reductions in the gate FN current. If the profile of laterally encroached cells deteriorates, causing a broadening of the entire tunnel oxide, a significant degradation in the FN tunneling current is observed in the scaled cells. From Fig. 2(a) and (b), the rounded curvature of the edge profile has a relatively trivial effect on the variations in the resulting gate tunneling current, compared with variations in the current due to a broadening of the tunnel oxide or a lateral-encroached width. Therefore, to reduce mathematical complexity, tunnel oxides with roughly trapezoidal edge corners are used in all subsequent modeling of the gate FN tunneling current. C. Modeling of FN Tunneling Current With Edge Profile For wide cells, the FN tunneling current IFN can be estimated by [2], [13] 2 Vox BTox IFN = AW exp − (1) Tox Vox
Fig. 2. (a) Numerical results of the gate tunneling current for convex, concave, and linear edge profiles (Th = 16 nm, wx = 10 nm). (b) Simulated results of the gate tunneling current with various lateral-encroached widths (linear tunneloxide profile, Th = 16 nm).
the finger capacitor suffers considerable impairment in the FN tunneling current due to edge encroachment. A relatively high gate voltage is required to maintain sufficient current levels in finger-capacitor devices, whereas low gate voltage is sufficient to maintain a similar current in its planar-capacitor counterpart. In clarifying the impact of edge profile on the programming and erasing characteristics of NAND-type cells, we employ a 2-D tunnel-oxide profile to physically analyze the actual FN tunneling current. Before drawing up a formal analytical current model, numerical simulations are performed to investigate the effects of edge profile on the FN gate tunneling current. B. Simulation of FN Tunneling Current With Edge Profile Three different corner profiles (convex, concave, and linear) are numerically studied in scaled cells (cell width = 50 nm) with various degrees of lateral encroachment. Fig. 2(a) presents the numerical results of gate tunneling current for convex, concave, and linear edge profiles. The three profiles represent variations in the corners of tunnel oxide in scaled Flash cells
where Tox is the tunnel-oxide thickness; Vox is the oxide voltage across the tunnel oxide; and W is the cell width. A and B are constants related to the physical properties of electrons and dielectrics, which can be found in [2] and [13]. Notably, the FN tunneling current heavily depends on the tunnel-oxide thickness. Small variations in thickness can cause significant deviations in the tunneling gate current. For narrow cells, the edge-encroached profile and fringing-field effect of tunnel oxide must be included to determine the actual FN tunneling current. The total current comprises three components, including center, edge, and fringe current. Thus IFN = Icenter + Iedge + Ifringe
(2)
where Icenter , Iedge , and Ifringe represent the current components attributed to the center, edge, and fringe regions, respectively. Fig. 3 schematically shows the three current components of the total FN tunneling current. Because the thickness of the tunnel oxide varies in edge-encroached cells, the contribution of the center and edge parts can be integrated by distributed FN tunneling current density JFN , i.e., 2 Vox Tox (x) JFN (x) = A exp −B . (3) Tox (x) Vox
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estimate the encroached tunnel oxide, the associated edge component can be expressed as Iedge −( W 2 −wx )
W
2 =
JFN (x)dx+ W 2
JFN (x) dx
(8)
−W
−wx
2 ⎧ 2⎪ Vox ⎨BTox BTox BTox = 2A (1+ηwx ) −Ei − Ei − Tox ⎪ Vox Vox ⎩ηVox ⎤⎫
⎡ BTox ⎪ ox ⎬ exp − exp − BT (1+ηw ) x Vox Vox ⎦ − −⎣ ⎪ η(1+ηwx ) η ⎭
Fig. 3. Schematic diagram of the cell structure viewed along the width of the cell. (a) Edge enlargement. (b) Overlapped encroachment. Tox is the thickness of the as-grown tunnel oxide. wx is the lateral-encroached width. Th is the regrown tunnelis the thickness of the tunnel oxide at the edge. Tox oxide thickness, and wx is the lateral-encroached width under overlapped encroachment.
Based on the degree of lateral encroachment, we considered two edge profiles. Fig. 3 is a schematic representation of two cell structures viewed along the width of the cell: (a) edge enlargement and (b) overlapped encroachment. Tox is the thickness of the as-grown tunnel oxide. wx is the lateral-encroached width. Th is the tunnel-oxide thickness at the edge corner. When the lateral-encroached width exceeds half of the total cell width W , the lateral edges lead to overlapped encroachment. Under is the regrown tunnel-oxide thicksuch circumstances, Tox ness, and wx is the lateral-encroached width under overlapped encroachment. For very wide cells, the FN tunneling current mainly comes from the center component. Thus, the FN current can be maintained by the 1-D formula in (1), i.e., W 2
IFN ∼ =
JFN (x) dx −W 2
= AW
Vox Tox
2
(4)
BTox exp − . Vox
(5)
(9) where η = (Th − Tox )/wx Tox ; Ei is the Euler’s integral. In addition to the center and edge regions, the fringing electric field could cause considerable fringing current along the sidewall. Assuming that the field distribution is semicircular around the edge of the cell, the fringe current is approximately written as 2 Vox BαTh exp − (10) Ifringe = βA αTh Vox where α and β are the structural parameters related to the edge profile and effective area, respectively. The effective oxide thickness coefficient α can be represented by −1 W + Th 1 2Gh 1 ln 1 + α= (11) + exp π Th π 3Th where Gh is the height of the silicon gate. Here, the conformalmapping method [12] is used to convert the rectangular edge of the sidewall into the structure of a parallel capacitor. Notably, the fringing current is only appreciable under low electric field, becoming saturated at a relatively high oxide voltage. Because both the currents from the edge and center components dramatically increase as the oxide voltage increases, the contribution of the fringing current is negligible in normal programming/erasing FN tunneling operations.
D. FN Tunneling Current With Edge Enlargement For a small NAND-type cell suffering from edge profile, enlargement of the oxide and fringe effects must both be considered to determine the total FN tunneling current. If the edge encroachment is distributed only in the region of the edge without overlapping [Fig. 3(a)], the nonencroached center component is given by −wx
W 2
Icenter =
JFN (x) dx −(
W 2
−wx )
= A(W − 2wx )
(6)
E. FN Tunneling Current With Overlapped Encroachment When the lateral-encroached width wx is greater than half of the total width of the cell, the lateral edges lead to overlapped tunnel-oxide encroachment [Fig. 3(b)]. The function form of the fringe current is the same as that in (10), whereas the edge and center components require alternative expressions. The center component can be expressed from the distributed FN current density (3) as wx −W 2
Vox Tox
2
exp −
BTox Vox
Icenter = (7)
where wx is the lateral-encroached width, which is less than half of the total cell width. By using a linear trapezoid to
JFN (x) dx −W wx 2
−(
= A(2wx
(12)
)
− W)
Vox Tox
2
BTox exp − Vox
. (13)
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The associated edge component can be formulated as Iedge −(wx −W 2 )
W
2 =
JFN (x) dx+
−W wx 2
2
JFN (x) dx
(14)
−W 2
Vox = 2A ⎧ Tox ⎪ ⎨ BT BT ox ox × (1 + η (W − wx )) Ei − ⎪ Vox ⎩ η Vox BTox −Ei − Vox
⎫⎫ ⎧ BTox BTox ⎨exp − V (1+η(W −wx )) ⎬ exp − Vox ⎬⎪ ox − − ⎩ ⎭⎪ η (1+η (W −wx )) η ⎭
Fig. 4. Comparison of analytical and measured FN tunneling currents between finger capacitor and planar capacitor. Experimental results of TEM imagery and gate current shown in Fig. 1 are used to confirm the analytical models.
(15) where η = (Th − Tox )/wx Tox . Notably, the overlapped edge encroachment causes the redefinition of edge and center regions. Because small variations in thickness can cause significant deviations in gate current, the overall broadening of tunnel oxide results in severe degradation in the FN tunneling current.
III. R ESULTS AND D ISCUSSION To explore the usefulness of the model predictions, the results of the analytical FN tunneling current are confirmed by experimental measurements and 2-D device simulations. Fig. 4 presents a comparison of the analytical and measured FN tunneling currents between finger capacitor and planar capacitor. The experimental results of TEM imagery and gate current shown in Fig. 1 are used to confirm the analytical models. Results of “Planar Capacitor” are compared with those of nonencroached cell models with wx = 0 nm, whereas results of “Finger Capacitor” are checked with those of an overlapped encroached cell model with wx = 51.5 nm and Th = 10.8 nm (as-grown 8.5-nm tunnel oxide). Good agreement is observed between the analytical models and measured results. Fig. 5 displays the analytical and simulated results of the programming gate current in NAND-type Flash cells, i.e., (a) 70-nm cell and (b) 50-nm cell, where various lateralencroached widths (wx and wx ) are shown using two encroachment profiles. In Fig. 5(a), an 8-nm tunnel oxide is used with Th = 16 nm to represent a 70-nm-wide edge-encroached cell. In Fig. 5(b), a thinner 7-nm tunnel oxide with Th = 10 nm is employed to reflect a scaled 50-nm-wide edge-encroached cell. A higher degree of encroachment results in more severe degradation of current. Narrower cells are less immune to current degradation resulting from edge encroachment. Notably, two edge effects (edge enlargement and overlapped encroachment) are found to impair the tunneling gate current of NAND Flash cells. If the individually encroached edges are not merged, the edge enlargement causes only a mild linear current degradation in the FN tunneling current because the thickness of the asgrown tunnel oxide is maintained. After the lateral edge en-
Fig. 5. Results of analytical and simulated FN tunneling currents in edgeencroached Flash cells. (a) cell width = 70 nm. (b) cell width = 50 nm.
croachment penetrates into the center of the cell to overlap the entire tunnel oxide, the overall broadening of the tunnel oxide dramatically degrades the tunneling current. In such circumstances, linear variations in the encroached width results in an exponential decay in the tunneling current. Additionally, great agreement between physical models and simulated data is confirmed, justifying the use of analytical predictions for future development of NAND Flash cells. Fig. 6 presents the analytical predictions of the FN gate current in scaled cells using two differing encroachment profiles, where the edge and center components are plotted to demonstrate their proportion of the total current. In Fig. 6(a), profile (a) represents an edge profile with a high degree (30 nm) of encroachment and a thin edge (Th = 10 nm). In Fig. 6(b), profile (b) indicates an edge profile with a small degree (10 nm) of encroachment and a thick edge (Th = 16 nm). Notably, the variation in the FN tunneling current can be divided into two regions (edge enlargement and overlapped encroachment) according to the width of the cell. As the width of the cell is initially scaled down, the center components of the FN current gradually degrade, thereby reducing the total FN tunneling current. For an intermediate cell width, the
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IV. C ONCLUSION This work elucidates the impact of edge encroachment on the FN tunneling current of NAND-type Flash memory cells. Overlapped edge encroachment in scaled cells seriously impairs intrinsic gate current during programming and erasing. Thus, the degree of the lateral encroachment must be minimized to avoid overall tunnel-oxide regrowth in the future development of NAND-type Flash cells. ACKNOWLEDGMENT The authors would like to thank the National Nano Device Laboratories for providing access to their facilities. R EFERENCES
Fig. 6. Variation in FN tunneling current components as a function of cell width for two profiles of encroachment (at a floating gate voltage of 10 V; Profile (a): wide tunnel-oxide edge with long encroached width, Profile (b): narrow tunnel-oxide edge with short encroached width).
components related to the edge current are dominant in the total tunneling gate current. After the edge profiles of narrow cells are merged across the entire width of the cell, the total gate FN current exponentially drops. Under such circumstances, the overall overlapped encroachment deteriorates the operation of the cell causing intrinsic failures in programming and erasing. Importantly, the edge enlargement causes only a mild impairment in the total tunneling gate current, whereas the overlapped encroachment seriously impairs the total tunneling gate current. Because current NAND-type Flash technology suffers from severe abnormal tunnel-oxide enlargement [5], [7], [9], [10], it is crucial to prevent the overall tunnel-oxide regrowth, resulting from encroachment on lateral edges, to attain the expected programming and erasing speeds, and extend the life of scaled NAND -type Flash technology. Furthermore, it can be seen from Fig. 6(b) that, for a 40-nm-cell technology with 7-nm tunnel oxide, one-order-of-magnitude reduction in the gate tunneling current is observed in Flash cell with a half-cell encroachment (wx = 10 nm). As a rule of thumb, the degree of encroachment along the edges of cells cannot exceed the width of a halfcell without an order-of-magnitude degradation in the gate tunneling current. Otherwise, the edge current makes a major contribution to the gate tunneling current, thereby seriously impairing operational speeds.
[1] International Technology Roadmap for Semiconductor, 2007 edition. [2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998. [3] K. Prall, “Scaling non-volatile memory below 30 nm,” in Proc. IEEE NVSMW, 2007, pp. 5–9. [4] H. Yang, H. Kim, S.-I. Park, J. Kim, S.-H. Lee, J.-K. Choi, D. Hwang, C. Kim, M. Park, K.-H. Lee, Y.-K. Park, J. K. Shin, and J.-T. Kong, “Reliability issues and models of sub-90nm NAND Flash memory cells,” in Proc. IEEE Int. Conf. Solid-State Integr.-Circuit Technol., 2006, pp. 760–762. [5] B. Kim, W.-H. Kwon, C.-K. Baek, Y. Son, C.-K. Park, K. Kim, and D. M. Kim, “Edge profile effect of tunnel oxide on erase thresholdvoltage distributions in Flash memory cells,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3012–3019, Dec. 2006. [6] J. Lee, J. Kim, W. Lee, S. Lee, H. Lim, J. Lee, S. Nam, H. Lee, and C. Song, “Effect of STI shape and tunneling oxide thinning on cell Vth variation in the flash memory,” in Proc. IEEE IRPS, 2005, pp. 670–671. [7] M. Park, K. Suh, K. Kim, S.-H. Hur, K. Kim, and W.-S. Lee, “The effect of trapped charge distributions on data retention characteristics of NAND Flash memory cells,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 750– 752, Aug. 2007. [8] H. Watanabe, K. Shimizu, Y. Takeuchi, and S. Aritome, “Corner-rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memories,” in IEDM Tech. Dig., 1996, pp. 833–836. [9] C.-Y. Ho and C.-H. Shih, “Edge encroachments and suppressions of tunnel oxide in Flash memory cells,” IEEE Electron Device Lett., vol. 29, no. 10, pp. 1159–1162, Oct. 2008. [10] M. Park, C.-S. Lee, S.-H. Hur, K. Kim, and W.-S. Lee, “The effect of field oxide recess on cell VTH distribution of NAND Flash cell arrays,” IEEE Electron Device Lett., vol. 29, no. 9, pp. 1050–1052, Sep. 2008. [11] Synopsys MEDICI User’s Manual. Mountain View, CA: Synopsys Inc., 2006. [12] A. Bansal, B. C. Paul, and K. Roy, “An analytical fringe capacitance model for interconnects using conformal mapping,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 12, pp. 2765– 2774, Dec. 2006. [13] D. A. Buchanan, D. J. DiMaria, C.-A. Chang, and Y. Taur, “Defect generation in 3.5 nm silicon dioxide films,” Appl. Phys. Lett., vol. 65, no. 14, pp. 1820–1822, Oct. 1994.
Ji-Ting Liang (S’06) received the B.S. degree in electrical engineering, in 2004, from National Tsing-Hua University, Hsinchu, Taiwan, where she is currently working toward the Ph.D. degree in electronics engineering with the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu. Her current research interests include characterization, modeling, and reliability of nonvolatile floating-gate and charge-trapping memory devices.
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Chun-Hsing Shih was born in Taipei, Taiwan, in 1968. He received the B.S. degree in physics from National Central University, Taoyuan, Taiwan, in 1990 and the M.S. and Ph.D. degrees in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1995 and 2003, respectively. In 1995, he was with Winbond Electronics Corporation, Hsinchu, where he was engaged in the development of static random access memory (RAM), embedded dynamic RAM, nonvolatile memory, and high-voltage technologies. In 2004, he was with the Department of Electrical Engineering, Yuan Ze University, Taoyuan. Since 2010, he has been with the Department of Electrical Engineering, National Chi Nan University, Nantou, Taiwan. His current research interests are advanced CMOS devices and technologies, including Schottky barrier MOSFETs, nonvolatile memory, tunneling field-effect transistor, and power devices.
Wen-Fa Wu was born in Kaohsiung, Taiwan, in 1967. He received the B.S. degree in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1990 and the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, Taiwan, in 1994. In 1994, he joined the National Nano Device Laboratories, Hsinchu, where he has been a Researcher since 2003. He has authored or coauthored more than 120 journal or conference proceeding papers. His research interests include advanced nanocomplementary metal–oxide–semiconductor devices and technologies, thin-film devices and technologies, and nanotechnologies. Dr. Wu is a member of the Electrochemical Society. He was the recipient of the Outstanding Achievement Award in Science and Technology from the National Applied Research Laboratories in 2009.
Wei Chang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering from Nan Jeon Institute of Technology, Tainan, Taiwan, in 2003 and the M.S. degree in electrical engineering from Feng Chia University, Taichung, Taiwan, in 2005. He is currently working toward the Ph.D. degree in electronics engineering with the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan. His current research interests include advanced Schottky barrier complementary metal–oxide– semiconductor devices and nonvolatile memories using metal silicidation techniques.
Yan-Xiang Luo was born in Miaoli, Taiwan, in 1985. He received the B.S. degree in electronic engineering from Chung Yuan Christian University, Chung Li, Taiwan, in 2007 and the M.S. degree in electrical engineering from Yuan Ze University, Taoyuan, Taiwan, in 2009. He is currently working toward the Ph.D. degree in electronics engineering in the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan. His current research interests include advanced complementary metal–oxide–semiconductor devices, Flash memory, and power devices.
Ming-Kun Huang receipted the M.S. degrees in electrical engineering from Minghsin University of Science and Technology, Hsinchu, Taiwan, in 2007. He is currently working toward the Ph.D. degree in electrical engineering in the Department of Electrical Engineering, Yuan Ze University, Taoyuan, Taiwan. His current research interests include fabrication and design of Schottky barrier metal–oxide– semiconductor field-effect transistors and nanocomplementary metal–oxide–semiconductor devices.
Nguyen Dang Chien received the B.S. and M.S. degrees in physics from Dalat University, Dalat, Vietnam, in 2005 and Hanoi National University of Education, Hanoi, Vietnam, in 2008. He is currently working toward the Ph.D. degree in electrical engineering in the Department of Electrical Engineering, Yuan Ze University, Taoyuan, Taiwan. His current research interests include modeling and simulation of tunneling and heterojunction devices.
Sau-Mou Wu received the B.S. degree in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1979 and the M.S. and Ph.D. degrees in electrical engineering from the University of Maryland, College Park, in 1983 and 1987, respectively. During 1986–1992, he was with the Electronic Design Systems Laboratory, IBM, Fishkill, NY. He is currently an Associate Professor with the Department of Electrical Engineering, Yuan Ze University, Taoyuan, Taiwan. His research interests include mixed-signal integrated-circuit (IC) design, power management IC, passive ultrahigh-frequency radio-frequency identification, and complementary metal–oxide–semiconductor sensors.
Chenhsin Lien received the B.S. degree in physics from National Tsing Hua University (NTHU), Hsinchu, Taiwan, in 1975 and the Ph.D. degrees in physics from Ohio State University, Columbus, in 1982. Throughout his career, his research has primarily focused on solid-state devices, ranging from the quantum optoelectronic devices, CMOS devices, nanoelectronic devices to memories. Since 1983, he has been with the Department of Electrical Engineering, NTHU, where he is currently a Professor. From 2004 to 2006, he was the Director of the Institute of Electronic Engineering, NTHU. From 2006 to 2010, he was the Chair of Department of Electrical Engineering, NTHU. During 2010, he was the Acting Dean of the College of Electrical Engineering and Computer Science, NTHU. He is currently the Director of the Center of the Advanced Power Technologies, NTHU. He has authored more than 100 technical papers. His recent research interests include studies on nonvolatile memory such as resistive random-access memory (RRAM) and Schottky barrier SONOS memory. He proposed the use of reactive titanium layer to form a bilayer hafnium oxide RRAM to greatly improve its performances.
LIANG et al.: IMPACT OF EDGE ENCROACHMENT ON PROGRAMMING GATE CURRENT
Riichiro Shirota was born in Hyougo, Japan, in 1954. He received the B.S., M.S., and Ph.D. degrees in physics from Nagoya University, Nagoya, Japan, in 1977, 1979, and 1982, respectively. From 1982 to 2004, he was with Toshiba Corporation, Kawasaki, Japan, where he engaged in research and development on the dynamic randomaccess memory, electrically erasable programmable read-only memory, and Flash memory. He started to develop NAND Flash memory in 1987. He has been the Technical Supervisor of the Research and Development Center. He has developed NAND Flash memory from 0.7-μm to 32-nm design rule. From 2004 to 2006, he was the Chief Specialist of Flash business strategy development in the Memory Division, Toshiba Corporation. In 2005, he became a Guest Professor with Beijing Institute of Technology, Beijing, China. In 2006, he was with National Tsing Hua University (NTHU), Hsinchu, Taiwan. Since 2010, he has become the Chair Professor with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu. His current research interests include the scaling of Flash memory device and physical modeling of memory cell reliability and system of solid-state drive using NAND Flash memory. Prof. Shirota was the recipient of the Ichimura Award in Japan in 2000 for his contribution to large-scale NAND Flash development and pioneering its application, and the Tanahashi Award in the Japanese Electrochemical Society entitled “Development of the Gigabit NAND Flash Memory” in 2005.
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Chiu-Tsung Huang was born in Tainan, Taiwan, in 1967. He received the B.S. degree in physics from Soochow University, Taipei, Taiwan, in 1989 and the M.S. degrees in physics from Fu-Jen Catholic University, Taipei, in 1991, respectively. In 1993, he was with HOLTEK Semiconductor Corporation, Hsinchu, Taiwan, where he was engaged in the SPICE model, technology computeraided design (TCAD), and device reliability. In 1999, he was with UMC, Hsinchu, to work as a Device Engineer to develop silicon-on-insulator device. Since 2002, he was with Powerchip Semiconductor Corporation, Hsinchu, where he was in charge of SPICE model, TCAD, and device reliability.
Su Lu, photograph and biography not available at the time of publication.
Alex Wang, photograph and biography not available at the time of publication.
