IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 12, DECEMBER 2007
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Improved Electronic Performance of HfO2/SiO2 Stacking Gate Dielectric on 4H SiC Kuan Yew Cheong, Member, IEEE, Jeong Hyun Moon, Tae Joo Park, Jeong Hwan Kim, Cheol Seong Hwang, Hyeong Joon Kim, Member, IEEE, Wook Bahng, and Nam-Kyun Kim
Abstract—The MOS characteristics of an atomic layerdeposited HfO2 /N2 O-nitrided SiO2 stacking gate dielectric on n-type 4H SiC (0001) has been investigated. Three different thicknesses of nitrided SiO2 (2, 4, and 6 nm) have been sandwiched between HfO2 and SiC. The electronic performance of the stacking dielectric depends on the thickness of the nitrided SiO2 . Among the stacking dielectrics, the lowest effective oxide charge and interface-trap density as well as the most reliable dielectric has been demonstrated by a sample with the thickest nitrided SiO2 . The reason for this observation is proposed. Index Terms—High dielectric-constant gate, leakage current, nitridation, reliability.
I. INTRODUCTION
T
HE SUPERB intrinsic properties of SiC and the ability of this material to grow native oxide enable it to be used as a substrate for high-power MOS-based devices [1]. To fabricate these devices, the gate oxide must be able to withstand a high electric field (E) and to demonstrate a good reliability, so that leakage current through the gate oxide could be minimized. Up to date, thermally nitrided SiO2 on SiC is still considered the best reported gate oxide [1]–[5], but its relatively low dielectric constant, k, value (kSiO2 = 3.9) compared to SiC (kSiC = 10) could contribute to oxide breakdown and reliability issues. The electric field strength in a dielectric is scaled by a factor of kSiC /k; assuming that a SiO2 gate is used, an approximately 2.5 times higher electric field is being imposed on the oxide rather than on the SiC. This leads to a severe oxide breakdown and reliability problem [1]. One approach to address these issues is to replace the relatively low-κ nitrided SiO2 with a high-κ dielectric [1]. Recently, extensive works have been focused on searching for a suitable alternative high-κ dielectric [6]–[14]. HfO2 is one of the promising candidates as it has demonstrated a relatively Manuscript received May 22, 2007; revised August 10, 2007. The review of this brief was arranged by Editor Y.-J. Chan. K. Yew Cheong is with the School of Materials and Mineral Resources Engineering, Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysia (e-mail:
[email protected]). J. H. Moon, T. J. Park, C. S. Hwang, and H. J. Kim are with the School of Materials Science and Engineering, College of Engineering, Seoul National University, Seoul 151-744, Korea. J. H. Kim was with the School of Materials Science and Engineering, College of Engineering, Seoul National University, Seoul 151-744, Korea. He is now with the Interuniversity Microelectronics Center, B-3001 Leuven, Belgium. W. Bahng and N.-K. Kim are with the Power Semiconductor Research Group, Advanced Materials and Application Research Laboratory, Korea Electrotechnology Research Institute, Changwon, Kyongnam 641-120, Korea. Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.908545
high value of k (∼20) [10]. However, this dielectric has a narrow bandgap (∼5.6 eV) [1], [10], [13], which is attributed to smaller conduction- and valence-band (EC and EV ) offsets in 4H-SiC/HfO2 [1], [13] compared with 4H-SiC/SiO2 [1]. With these small band offset values, the probability of carriers tunneling through the dielectric has been increased significantly and it may deplete the purpose of using this high-κ material. To circumvent this issue, a thin buffer thermal SiO2 has been sandwiched between the HfO2 and SiC and this has been proven effective in this system [10], [11] and in others [9], [15]. The thickness of SiO2 (2–12 nm), type of SiO2 (dry or NO-nitrided thermal oxide) [10], [11], methods of depositing HfO2 and of SiC surface treatment may influence the quality of the gate dielectric [10]–[14], [16]. The best reported room-temperature electronic properties [current density–voltage (J–V ), capacitance–voltage (C–V ), and SiC-dielectric interface trap density (Dit )] were obtained from a nitro-based atomic layer-deposited HfO2 (20 nm)/NOnitrided SiO2 (4 nm) stacked on 4H SiC (0001) [11]. Since NO gas is hazardous, usage of this gas in common laboratories needs to abide by stringent regulations; therefore, it is not a preferable gas to be used for growing the thermal nitrided SiO2 . To solve this issue, a nonhazardous N2 O gas has been suggested. It has been reported [2] that thermally nitrided SiO2 derived from diluted N2 O gas has a comparable quality with its NO-derived counterpart. In this brief, we are reporting an improved electronic characteristic of this stacking dielectric by using a nonhazard diluted N2 O gas to produce the thin nitrided SiO2 (2-, 4-, and 6-nm thick). II. EXPERIMENTAL DETAILS n-type, Si-faced, 4H-SiC substrate with 10-µm thick epilayer (doping level of 5–9 × 1015 cm−3 ) purchased from CREE, Inc. (USA) was used to fabricate the MOS-capacitors. Prior to dielectric deposition, the wafer was cleaned [3]. A thin layer of nitrided SiO2 was grown on the wafer in 10% N2 O ambient at 1175 ◦ C [3]. Three different thicknesses (2, 4, and 6 nm) of nitrided oxide were obtained by adjusting the nitridation time. The wafers were then inserted into a travelingwave type atomic-layer-deposition reactor, so that an approximately 13-nm thick HfO2 could be deposited on the wafers using Hf[N(CH3 )2 ]4 and O3 as the precursor and oxidant, respectively [17]. After the dielectric deposition, a layer of nickel gate electrode was deposited using an RF magnetron sputter system. After that, areas of the MOS capacitors (AG = 1.30 × 10−3 cm2 ) were defined by photolithography. Finally,
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Fig. 1. HF C–V curves of MOS capacitors with HfO2 gate stacked on 0-, 2-, 4-, and 6-nm thick nitrided SiO2 . MOS capacitor with a pure 20.1-nm thick nitrided SiO2 gate is included for comparison. The arrows indicate the gate voltage sweeping directions.
after removing the back oxide, a large area of the aluminum acting as a back contact was sputtered on the n+ substrate. The purpose of applying nickel as gate electrode is to avoid metal diffusion into the gate oxide. Postmetallization annealing was not performed to avoid masking the effects of the dielectrics. A good conductivity could be achieved even without this annealing [2], [5], [18], [19]. Electrical analysis of the dielectrics was performed by 100-kHz and quasi-static capacitance–voltage (C–V ) measurements, using a computer-controlled Keithley 590 C–V analyzer and 595 Quasistatic C–V meter, with a dc swept rate of 0.1 V/s. The SiC-dielectric interface-trap density (Dit ) was acquired by a simultaneous high–low frequency (hi–lo) C–V method at room temperature. The difference between high and low (or quasi-static) frequency C–V measurement as a function of gate voltage were obtained and later converted into Dit as a function of energy trap level. The procedures of acquiring Dit value from this technique has been well explained in [20]. This technique has also been used by other researchers [4], [21], [22]. Current–voltage (I–V ) measurements of the MOS capacitors were conducted using a Semiconductor Parameter Analyzer. The transformation of I–V to J–E plots were performed using J = I/AG and E was approximated by (VG − VFB )/EOT, where VG and EOT were the gate voltage and the equivalent oxide thickness with respect to SiO2 [9]. The EOT of the HfO2 stacked on 0-, 2-, 4-, and 6-nm thick nitrided SiO2 were, 4.2, 6.2, 8.1, and 9.9 nm, respectively. III. RESULTS AND DISCUSSION The positive- and negative-biased high-frequency (HF) C–V curves (Fig. 1) of the three investigated stacking dielectrics did not reveal any hysteresis if compared with the one reported in [11, Fig. 1(b)]. From flatband voltage (VFB ) of the hysteresis, slow-trap density could be estimated [22]. As the hysteresis is extremely small in samples with the stacking dielectrics, it can be concluded that the dielectrics have a relatively low density of slow traps. However, a large hysteresis (0.5 V) has been observed in the nonstacking HfO2 sample; suggesting that the
Fig. 2. Comparison of effective oxide charge, Neff , of HfO2 stacked on different thickness of nitrided oxide. Pure HfO2 and nitrided SiO2 are included for comparison.
slow-trap density is much higher than that obtained from the stacking dielectrics. From the forward biased HF C–V measurement, all of the stacking dielectrics almost have the same (+0.94 to +0.96 V) positive flatband-voltage shift (∆VFB ) from the ideal VFB and it is also smaller than that of the nonstacking HfO2 sample. The ideal VFB value is simulated using the formulas provided in [20]. Even though the ∆VFB of the stacking dielectrics are almost the same, effective oxide charges (Neff ) (Fig. 2) that have been calculated are different. This is because they have different oxide capacitances (Cox ). For 2-, 4, and 6-nm thick nitrided oxides, their Cox values are 705, 592, and 490 pF, respectively. The Neff was deduced from Neff = ∆VFB Cox /qAG , where q is electronic charge. A negative Neff has been revealed in both stacking and nonstacking HfO2 dielectrics, whereas a positive Neff is demonstrated in the sample with pure nitrided SiO2 (20.1-nm thick). It has been observed that the thicker the nitrided oxide in the stacking gate, the smaller the −Neff is. The +Neff value that has been revealed in pure nitrided SiO2 is commonly reported [3] while the −Neff value in HfO2 samples are probably attributed to the extra charges originating from the bulk oxides and interface of SiC/SiO2 , SiC/HfO2 , and HfO2 /SiO2 . Charge trapping properties of the gate dielectric have been investigated by applying a constant gate voltage (VG = 2 to 14 V) for a fixed duration. Fig. 3 exhibits the density of the trapped charge for the investigated dielectrics after they have been stressed at various constant VG for 100 s. The trappedcharge density was deduced from the flatband voltage shift (∆VFB ) between the virgin and stressed samples. Among the stacking dielectrics, the sample with 6-nm thick nitrided SiO2 showed the lowest density in trapped charge. The trapped charge in this sample is even lower than the samples with pure nitrided SiO2 and with pure HfO2 . This indicates that the stacking dielectric is more resistant to electric-field stress than others. In comparison, the pure HfO2 sample demonstrated the least stress-resistant property. This is in agreement with an observed kink near the accumulation level in the HF C–V curve (Fig. 1). The existence of this kink indicates that the amount of
CHEONG et al.: ELECTRONIC PERFORMANCE OF HfO2 /SiO2 STACKING GATE DIELECTRIC ON 4H SiC
Fig. 3. Density of trapped oxide charge as a function of various constant applied electric fields stressed for 100 s in HfO2 stacked on different thickness of nitrided oxide. Results of pure HfO2 and nitrided SiO2 are included for comparison.
Fig. 4. Comparison of energy distribution of SiC-dielectric interface trap density, Dit , for different investigated dielectrics. Pure HfO2 , nitrided SiO2 , and dry oxide are also included for comparison. The total interface-trap density, Nit , as a function of nitrided SiO2 thickness is presented in the inset of the figure. The Dit is measured by simultaneous hi–lo C–V method and Nit is obtained from the area below the plots.
accumulated majority carrier is in equilibrium with the amount of carrier leaks through the oxide. Due to this leakage, the dielectric is unable to resist the injection of electron to the dielectric during the stress test. Since the oxide is leaky, no obvious accumulation level can be observed and therefore the measurement is terminated at +5.0 V. Fig. 4 presents the distribution of he SiC-dielectric interfacetrap density (Dit ) as a function of energy trap level (EC − E). EC and E are the respective energy level of the conduction band edge and of the interface trap. From the area below the Dit − (EC − E) plots, total interface-trap density (Nit ) at the respective investigated energy trap level has been calculated (inset of Fig. 4). The Dit values of the pure nitrided SiO2 film that is shown in Fig. 4 are significantly higher than the value reported in [2]. The difference may be probably due to the dissimilar measurement technique [23]. However, for comparison purposes, Dit values of the nitrided SiO2 film measured
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in this brief is still lower than its nonnitrided counterpart (dry oxide), particularly for those traps located at EC − E ∼ 0.2 and 0.7 eV. For samples having stacking dielectrics, Dit and Nit values are reduced as the nitrided-oxide thickness increases. At a glance, this result seems inconsistent with the HF C–V plots (Fig. 1) because the plots are almost identical. However, in detailed analysis, after taking into consideration the quasistatic frequency C–V plots (not shown), the difference between the high and quasi-static frequency C–V plots enables the differences to be revealed. The reduction of Dit and Nit as a function of nitrided-oxide thickness may be attributed to the reduction of the oxycarbide complex compound [2] at the SiC−SiO2 interface. However, from the analysis of the depth profile using time-of-flight secondary ion mass spectroscopy, no concrete evidence can confirm the chemical compound detected at the interface. Therefore, further chemical analyses are needed to investigate the relationship between the chemical compound formed at the interface as a function of nitrided SiO2 thickness. Another plausible reason for the reduction of these parameters is associated with the dominance of passivation [2] rate compared to depassivation [24] rate of SiC–SiO2 interface by Si ≡ N. The relationship between nitrided-oxide thickness and Nit has been reported in [25] and the result is in agreement with this brief. To verify these assertions, more comprehensive work need to be performed. Fig. 5(a) shows the room-temperature measurement of J–E plots for MOS capacitors with HfO2 gate stacked on 0-, 2-, 4-, and 6-nm thick nitrided SiO2 . The result of MOS capacitors with pure nitrided SiO2 is also included for comparison. The negative value of E in the figure was attributed to the positive ∆VFB of the samples. The dielectric breakdown field, EB , is defined as an electric field that may contribute to J ≥ 10−6 A/cm2 . This breakdown field does not correspond to a permanent oxide breakdown but rather is a safe value for a device to operate. This J–E measurement enables the time-zero dielectric breakdown (TZDB) of the dielectrics to be evaluated [26]. TZDB is a measure of dielectric breakdown induced by ramping up of VG at a constant rate (0.3 V/s). A total of 25 capacitors have been tested and the cumulative dielectric breakdown percentage has been presented in Fig. 5(b). Among the stacking dielectrics, the sample with 6-nm thick nitrided SiO2 demonstrates the highest EB and it is also higher than that reported in [11, Fig. 1(a)]. It is obvious that the reliability of HfO2 gate has been improved when a thin nitrided SiO2 layer is introduced between the HfO2 and SiC. This improvement is more significant when the thickness of the nitrided SiO2 is increased. Interestingly, the reliability of HfO2 gate stacked on 4- and 6-nm thick nitrided SiO2 is even better than that of the pure nitrided SiO2 gate. The improved electronic performance and reliability of the stacking HfO2 compared with nonstacking HfO2 is mainly due to the difference in conduction-band offset, which has been discussed in the Introduction section, and to the reduction of slow-trap density, which is associated with the reduction of −Neff as well as Nit . Unlike previous results [11], this brief has demonstrated that the thicker the nitrided SiO2 , the better the stacking dielectric quality. The discrepancy is probably due to the difference in producing the HfO2 (Hf precursor) and nitrided SiO2 (nitridation source) as well as the
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Fig. 5. (a) Room temperature (25 ◦ C) results of current density (J)-electric field (E) plots of HfO2 stacked on 0-, 2-, 4-, 6-nm thick nitrided SiO2 . The J–E results of a pure 20.1-nm thick nitrided SiO2 is also included for comparison. (b) Cumulative failure percentage of TZDB as a function of dielectric breakdown field, EB , for different types of dielectrics.
thickness of nitrided SiO2 (in [11], 4, 8, and 12 nm were used). Further investigation is needed to verify these. IV. CONCLUSION In this brief, we have reported the improved electronic results of atomic-layer deposited HfO2 /N2 O-nitrided SiO2 stacking gate on n-type 4H-SiC. The effects of nitrided-oxide thickness (2, 4, and 6 nm) on electronic performance were investigated. It has been observed that Nit and Neff values were reduced and dielectric reliability was increased as the nitrided-oxide thickness was increased. Based on the reported results, a stacking gate with 6-nm thick nitrided SiO2 has demonstrated the best dielectric reliability. The reasons for this improvement have been proposed. ACKNOWLEDGMENT One of the authors (K. Y. Cheong) would like to acknowledge the support of The Ministry of Higher Education, Malaysia, through the Fundamental Research Grant Scheme (FRGS). The authors also acknowledge the assistance in performing TOF-SIMS analysis by Korea Institute of Science and Technology.
[1] W. J. Choyke, H. Matsunami and G. Pensl, Eds., Silicon Carbide—Recent Major Advances. Berlin, Germany: Springer-Verlag, pp. 785–812. 373–386, 343–372. [2] P. Jamet, S. Dimitrijev, and P. Tanner, “Effects of nitridation in gate oxides grown on 4H-SiC,” J. Appl. Phys., vol. 90, no. 10, pp. 5058–5063, Nov. 2001. [3] K. Y. Cheong, S. Dimitrijev, J. Han, and H. B. Harrison, “Electrical and physical characterization of gate oxides on 4H-SiC grown in diluted N2 O,” J. Appl. Phys., vol. 93, no. 9, pp. 5682–5686, May 2003. [4] S. Dhar, L. C. Feldman, S. Wang, T. Isaacs-Smith, and J. R. Williams, “Interface trap passivation for SiO2 /(0001) C-terminated 4H-SiC,” J. Appl. Phys., vol. 98, no. 1, pp. 014 902-1–014 902-5, Jul. 2005. [5] J. P. Xu, P. T. Lai, C. L. Chan, B. Li, and Y. C. Cheng, “Improved performance and reliability of N2 O-grown oxynitride on 6H-SiC,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 298–300, Jun. 2000. [6] L. A. Lipkin and J. Palmour, “Insulator investigation on SiC for improved reliability,” IEEE Trans. Electron Devices, vol. 46, no. 3, pp. 525–532, Mar. 1999. [7] S. W. Huang and J. G. Hwu, “Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1877–1882, Nov. 2004. [8] J. H. Moon, D. I. Eom, S. Y. No, H. K. Song, J. H. Yim, H. J. Na, J. B. Lee, and H. J. Kim, “Electric properties of the La2 O3 /4H-SiC interface prepared by atomic layer deposition using La(iPrCp)3 and H2 O,” Mater. Sci. Forum, vol. 527–529, pp. 1083–1087, 2006. [9] K. Y. Cheong, J. H. Moon, D. Eom, H. J. Kim, W. Bahng, and N.-K. Kim, “Electronic properties of atomic-layer-deposited Al2 O3 /thermalnitrided SiO2 stacking dielectric on 4H SiC,” Electrochem. Solid State Lett., vol. 10, no. 2, pp. H69–H71, 2007. [10] V. V. Afanas’ev, A. Stesmans, F. Chen, S. A. Campbell, and R. Smith, “HfO2 -based insulating stacks on 4H-SiC (0001),” Appl. Phys. Lett., vol. 82, no. 6, pp. 922–924, Feb. 2003. [11] V. V. Afanas’ev, S. A. Campbell, K. Y. Cheong, F. Ciobanu, S. Dimitrijev, G. Pensl, A. Stesmans, and L. Zhong, “Electronic properties of SiON/HfO2 insulating stacks on 4H-SiC (0001),” Mater. Sci. Forum, vol. 457–460, pp. 1361–1364, 2004. [12] C. M. Tanner, J. P. Choi, and J. P. Chang, “Structural and morphological properties of atomic layer deposited HfO2 on 4H-SiC,” Mater. Sci. Forum, vol. 527–529, pp. 1075–1078, 2006. [13] C. M. Tanner, J. P. Choi, and J. P. Chang, “Experimental and firstprinciples studies of the electronic properties of HfO2 on 4H-SiC,” Mater. Sci. Forum, vol. 527–529, pp. 1071–1074, 2006. [14] S. Hino, T. Hatayama, N. Miura, T. Ozeki, and E. Tokumitsu, “Low temperature deposition of HfO2 gate insulator on SiC by metalorganic chemical vapor deposition,” Mater. Sci. Forum, vol. 527–529, pp. 1079– 1082, 2006. [15] J. H. Moon, K. Y. Cheong, D. Eom, H. K. Song, J. H. Yim, J. H. Lee, H. J. Na, W. Bahng, N. K. Kim, and H. J. Kim, “Electrical properties of atomic layer deposited La2 O3 /thermal-nitrided SiO2 stacking dielectric on 4H-SiC(0001),” in Mater. Sci. Forum, Newcastle upon Tyne, U.K., vol. 556–557, pp. 643–646, 2007. [16] S. S. Hullavard, D. E. Pugel, E. B. Jones, R. D. Vispute, and T. Venkatesan, “Low leakage current transport and high breakdown strength of pulsed laser deposited HfO2 /SiC metal-insulator-semiconductor device structures,” J. Electron. Mater., vol. 36, no. 6, pp. 648–653, Jun. 2007. [17] J. Park, T. J. Park, M. Cho, S. K. Kim, S. H. Hong, H. Kim, M. Seo, and C. S. Hwang, “Influence of the oxygen concentration of atomiclayer-deposited HfO2 gate dielectric films on the electron mobility of polycrystalline-Si gate transistors,” J. Appl. Phys., vol. 99, no. 9, pp. 094 501-1–094 501-8, May 2006. [18] H. Li, S. Dimitrijev, H. B. Harrison, and D. Sweatman, “Interfacial characteristics of N2 O and NO nitrided SiO2 grown on SiC by rapid thermal processing,” Appl. Phys. Lett., vol. 70, no. 15, pp. 2028–2030, Apr. 1997. [19] P. T. Lai, S. Chakraborty, C. L. Chan, and Y. C. Cheng, “Effects of nitridation and annealing on interface properties of thermally oxidized SiO2 /SiC metal–oxide–semiconductor system,” Appl. Phys. Lett., vol. 76, no. 25, pp. 3744–3746, Jun. 2000. [20] D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York: Wiley, 1998, pp. 337–368, 339–345. [21] K. Fukuda, S. Suzuki, and T. Tanaka, “Reduction of interface-state density in 4H-SiC n-type metal–oxide–semiconductor structures using high temperature hydrogen annealing,” Appl. Phys. Lett., vol. 76, no. 12, pp. 1585– 1587, Mar. 2000. [22] P. T. Lai, J. P. Xu, H. P. Wu, and C. L. Chan, “Interfacial properties and reliability of SiO2 grown on 6H-SiC in dry O2 plus trichloroethylene,” Microelectron. Reliab., vol. 44, no. 4, pp. 577–580, Apr. 2004.
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Kuan Yew Cheong (S’01–M’04) received the B.Eng. and M.Sc. degrees in materials engineering from Universiti Sains Malaysia (USM), Penang, Malaysia, in 1997 and 2001, respectively, and the Ph.D. degree in microelectronic engineering from Griffith University, Brisbane, Australia, in 2004. From 1997 to 1999, he was with a Project Management company and with a semiconductor-devices manufacturing factory in Malaysia, worked as a Project Engineer and Quality Assurance Engineer, respectively. Then, in 1999, he joined the School of Materials and Mineral Resources Engineering, USM, as a member of academic staff. He is currently a Senior Lecturer at the School of Materials and Mineral Resources Engineering, USM. His main research area is focused on Si- and SiC-based gate oxide engineering and synthesis and characterization of nanostructure materials. He has published 26 refereed journals, two book chapters, and more than 30 conference proceedings. Dr. Cheong is one of the Ex-comm of IEEE-Component, Package, and Manufacturing Technology Society, Malaysia Section, a Corporate Member of Institute of Physics (U.K.), a Senior Member of American Society for Quality, a member of Materials Research Society (USA), a Professional Engineer registered under Board of Engineers, Malaysia, and a Corporate Member of the Institution of Engineers, Malaysia. He was awarded a USM academic staff training scheme fellowship, Griffith University Postgraduate Research Scholarship, and Australian Research Council Top-up Grant for his previous studies.
Jeong Hyun Moon received the B.S. degree in metal engineering from Chonbuk National University, Jeon-Ju, Korea, in 2003. He is working toward the Ph.D. degree in materials science and engineering from Seoul National University, Seoul, Korea. His current research activities include fabrication and characterization of SiC devices.
Tae Joo Park was born in Seoul, Korea, on March 31, 1978. He received the B.Eng. degree in materials science and engineering from Seoul National University, Seoul, Korea, in 2002. He is currently working toward the Ph.D. degree at the Seoul National University. His study was focused on the electrical and chemical characterizations of the advanced gate stacks with metal gate/high-κ/high mobility channel.
Jeong Hwan Kim received the Diploma degree and joined the integrated M.A./Ph.D. course in materials science and engineering from Seoul National University, Seoul, Korea, in 2005. His study was focused on the electrical properties and reliability characteristics of atomic-layer-deposited high-κ HfO2 films. He is currently staying at the Interuniversity Microelectronics Center, Leuven, Belgium, working on the reliability problems of DRAM and Flash memory.
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Cheol Seong Hwang received the M.Sc. and Ph.D. degrees from Seoul National University, Seoul, Korea, in 1989 and 1993, respectively. In 1993, he joined the Materials Science and Engineering Laboratory, National Institute of Standards and Technology, Gaithersburg, MD, as a Postdoctoral Research Fellow. Then, he joined Samsung Electronics as a Senior Researcher in 1994 and made contributions to the fields of semiconductor memory devices with research on high-κ dielectrics including (Ba, Sr)TiO3 . Since 1998, he has been an Associate Professor at the Department of Materials Science and Engineering, Seoul National University. He has authored or coauthored more than 180 papers in international peer-reviewed scientific journals, which are cited more than 1900 times, and has given 30 invited presentations in international conferences. His current interests include high-κ gate oxide, DRAM capacitors, new memory devices including RRAM/PRAM, and ferroelectric materials and devices. Dr. Hwang was a recipient of the Alexander von Humboldt Fellowship Award and the 7th Presidential Young Scientist Award of the Korean government.
Hyeong Joon Kim (M’00) received the B.S. degree in inorganic materials engineering from Seoul National University, Seoul, Korea, in 1976, the M.S. degree in materials science from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1978, and the Ph.D. degree in materials engineering from North Carolina State University, Raleigh, in 1985. From 1978 to 1981, he was a Research Engineer at Agency for Defense Development. Since 1986, he has been with Seoul National University, where he is now a Professor in the Department of Materials Science and Engineering. His current interests include high-κ dielectric thin films, epitaxial growth and device fabrication of SiC, protective layers in ac-plasma display panel, and mobile communication devices such as surface acoustic wave and film bulk acoustic resonator.
Wook Bahng received the Master’s and Ph.D. degrees in materials science from Seoul National University, Seoul, Korea, in 1992 and 1997, respectively. From 1991 to 1997, he had researched SiC epitaxy using single precursor. In 1997, he was with Electrotechnical Laboratory, Tsukuba, Japan, as a Research Fellow, where he worked on single crystal growth of SiC. In 2000, he joined Korea Electrotechnology Research Institute, Changwon, Korea, as a member of Integrated Power Supply Group, where he worked on SiC power device fabrication. His recent research interests are epitaxial growth of SiC and defect characterization which causes degradation of SiC-based power devices. He has published 50 scientific papers and holds 30 patents on SiC materials and devices.
Nam-Kyun Kim received the B.S. and Ph.D. degrees in inorganic materials engineering from Seoul National University, Seoul, Korea, in 1984 and 1990, respectively. In 1990, he joined Korea Electrotechnology Research Institute (KERI), Changwon, Korea, as an Electroceramic Researcher. In 1993, he joined power semiconductor research group of KERI to develop high voltage power device and power module package. In 1995, he received JKF fellowship which supported him one-year’s research stay in National Institute for Research in Inorganic Materials, Tsukuba, Japan. In 1999, he became the Project Leader of a national project on silicon carbide power device development. He is Inventor or Coinventor of eight patents on silicon carbide power device. He is currently the Director of Integrated Power Supply Research Group of KERI. Prof. Kim received Minister’s Award of Science and Technology of Korea for his contribution to power semiconductor development, in 2004. His research group was awarded KERI Prize for Outstanding Achievement, in 2005 and in 2006 consecutively.
