Improving a Non-Enumerative Method to Estimate Path Delay Fault Coverage Keerthi Heragu
Center for Reliable and High-Performance Computing University of Illinois at Urbana-Champaign, Urbana, IL 61801
Vishwani D. Agrawal (Contact author)
Bell Labs, Lucent Technologies 700 Mountain Avenue, Room 2C-476, Murray Hill, NJ 07974 Phone: (908) 582-4349, FAX: (908) 582-5857, Email:
[email protected]
Michael L. Bushnell
Dept. of Electrical & Computer Engineering Rutgers University, Piscataway, NJ 08855
Janak H. Patel
Center for Reliable and High-Performance Computing University of Illinois at Urbana-Champaign, Urbana, IL 61801 July 23, 1997
CAD Manuscript No. MS19015 (Accepted)
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Abstract A recently proposed method obtains path delay fault coverages by estimating the count of the number of tested faults instead of actually enumerating them. The estimate become pessimistic when several paths share a set of lines. In this communication, we present a continuum of improved approximations for the counting method, approaching exact fault simulation, to allow trade-o s between accuracy and complexity. Higher accuracy is obtained at the expense of CPU time. We propose the use of ags corresponding to xed-length path-segments. A ag indicates whether or not the segment has been included in a previously detected path fault. A path fault, detected by a pair of vectors, is counted as a new detection only if it includes at least one segment not included in any previously tested path fault. The results show that as the length of segments is increased, the accuracy approaches close to that of the exact fault simulation even with small segment lengths.
1 Introduction An approximate method to estimate path delay fault coverages was proposed by Pomeranz and Reddy [1]. Their method replaces the explicit path enumeration of a fault simulator by a less complex path counting procedure. Line ags are used to keep track of signal lines that are covered by tested path faults. For a path fault to be counted as a new detection, it must include at least one line not included in any previously detected fault. This approximation generally becomes pessimistic when several paths share a line. Referring to this procedure as the 0-order approximation, the authors give higher order approximations using circuit partitioning. The accuracy of estimation and, as expected, the complexity of computation increase. In this communication, we present an alternative method of improving the accuracy of the linear complexity counting procedure [2, 3, 4].
2 Main Idea Suppose we count a path delay fault as a newly detected fault only if it covers at least one pair of lines that was not included in any previously detected fault. The results show a signi cant improvement over the 0-order approximation [2, 3]. The estimate is further improved if we maintain detectability status over longer path segments whose length can be set anywhere between 1 and the maximum logic depth [4]. In the extreme case, the detectability status of each path fault would be explicitly stored like a fault simulator. Let us examine the circuit graph of Figure 1 where, for simplicity, we consider only rising transitions at the origin of the path faults being tested. We assign ags to segments of pre-speci ed length to indicate whether or not they have been included in previously detected path faults. A CAD Manuscript No. MS19015 (Accepted)
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Figure 1: A circuit graph for path fault analysis
rising-segment-flag corresponding to a segment s, RSF (s), is 1 if s has not been included in a previously detected path delay fault with a rising transition at the origin of s. It is 0, otherwise.
Separate, but similar, ags would be used for falling transitions. All ags are initialized to 1 at the beginning of simulation. In Figure 1, let us assume that path faults I-(1-4-5-7-10), II-(3-5-7-9), and III-(3-5-8) have been detected on earlier vector pairs. We count a detected path fault as a new detection only if it includes at least one path-segment which has not been included in any previously detected path fault. Path-segments of various lengths, which have their RSF ags equal to 0, are given below: Length 1: Length 2: Length 3: Length 4:
1, 3, 4, 5, 7, 8, 9, 10 1-4, 4-5, 5-7, 7-10, 3-5, 7-9, 5-8 1-4-5, 4-5-7, 5-7-10, 3-5-7, 5-7-9, 3-5-8 1-4-5-7, 4-5-7-10, 3-5-7-9, 3-5-8
Note that when a complete path is shorter than the length of agged path-segments, we use the complete path itself. For example path (3-5-8) is stored in the list of segments of length 4. Next, consider a new vector pair that detects path faults IV-(1-4-5-8) and V-(1-4-5-7-9). Given below are path-segments of various lengths for each path fault, with the segments having RSF ags equal to 1 identi ed in bold: Path Fault IV (1-4-5-8) Length 1: 1, 4, 5, 8 Length 2: 1-4, 4-5, 5-8 Length 3: 1-4-5, 4-5-8 Length 4: 1-4-5-8
Path Fault V (1-4-5-7-9) Length 1: 1, 4, 5, 7, 9 Length 2: 1-4, 4-5, 5-7, 7-9 Length 3: 1-4-5, 4-5-7, 5-7-9 Length 4: 1-4-5-7, 4-5-7-9
Notice that an approximation using path-segments of length 1 or 2 will fail to identify fault IV CAD Manuscript No. MS19015 (Accepted)
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and V as new detections. Segments of length 3 identify path IV but fail to identify path V as a new path fault. Finally, segments of length 4 identify both path IV and V as new detections. This example illustrates that the accuracy of estimation can be improved by increasing the length of path-segments over which detectability information is maintained. If path-segments span entire paths, the coverage will be exact and the complexity will match that of fault simulation. The improved estimation technique will be practical if reasonable accuracy is obtainable with a small segment length that does not have to be increased with the circuit size.
3 Experiment We perform robust simulation of vector pairs. Following the simulation of a vector pair, we make a backward pass over the circuit and compute two parameters for each line i. Let new-lines(i) denote the number of newly detected sub-paths on which transitions propagate robustly between line i and a primary output (PO) for the current vector pair. Similarly, old-lines(i) denotes the number of sub-paths between line i and a PO, that are included in previously detected faults. Lines with no transition on a given vector pair have their new-lines and old-lines values set to 0. Consider the computation of new-lines(x) where x is an input of a gate. If x has a transition robustly propagated to a PO, the number of new sub-paths originating from it and ending at a PO is at least equal to the sum of the new sub-paths originating from the endpoints of the pathsegments of length l and ending at POs. In addition, if a path-segment has not been included in a previously detected path fault for the corresponding transition, the old sub-paths originating from the endpoints of the path-segment also add to the number of new sub-paths of the line under consideration. This information about the path-segments is maintained in ags on signal lines. The detailed algorithm [4] is derived as an extension of the path fault counting procedure of Pomeranz and Reddy [1]. We ran our estimator by varying the length of path-segments for which detectability status was maintained, from 1 to 3. Table 1 shows the robust path delay fault coverages. For ISCAS-85 circuits, a set of 10,000 random vector pairs, and for combinational parts of the ISCAS-89 circuits, a set of deterministic vector pairs was used. Column 2 shows the total number of vector pairs simulated. Column 3 shows the total number of path faults. Column 4 gives the maximum depth, i.e., the number of signal lines on the longest path in the circuit. The next column gives the estimated coverage obtained by the 0-order estimator of Pomeranz and Reddy [1]. In this case, the segment length (SL) is 1. Comparing with the result of exact fault simulation given in the last column, we notice large inaccuracies in the 0-order estimates. The improved estimates for CAD Manuscript No. MS19015 (Accepted)
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Table 1: Robust coverages of path delay faults Circuit No. of Total No. Max. Estimated detected faults Faults Name vector path delay depth 0-order [1] SL = 2 SL = 3 det. by pairs faults SL = 1
t. sim. c880 10000 17284 25 176 680 744 749 c1355 10000 8346432 25 15 15 16 16 c1908 10000 1458114 41 159 421 495 506 c2670 10000 1359768 33 511 1389 1494 1536 c3540 10000 57353342 48 109 410 441 446 c5315 10000 2682610 50 913 3883 4248 4409 c6288 10000 1.981020 125 19 20 20 23 c7552 10000 1452986 44 470 2397 2895 2936 s298 94 462 10 239 299 333 343 s526 206 820 10 379 593 680 694 s820 405 984 11 452 896 957 980 s832 409 1012 11 521 910 954 984 s1488 601 1924 18 609 1613 1787 1875 s1494 602 1952 18 617 1621 1794 1882 SL { Segment length larger segment lengths (SL = 2 and 3) are signi cantly closer to the exact result, even though these segment lengths are much smaller than the total depth. In all cases, estimates are pessimistic. The accuracy of estimates can be further improved by increasing the length of the path-segments over which detectability status is maintained. The CPU time of a path delay fault simulator depends on the number of detected faults, and not on the total number of faults, which can be an exponential function of the circuit size. For a given segment length L, the CPU time of our count-based estimator is a function of the number of segments of length L in the circuit. For small segment lengths, the CPU time is approximately a linear function of the circuit size, irrespective of the number of paths. In our experiment, we measured robust coverage and, as is typical, very few paths were activated. We found the CPU time of the exact fault simulation to be of the same order as that taken by the estimator. In cases, where the number of detected faults is exponential in the circuit size, the estimator will have a signi cant advantage of speed. Such may be the case where, for example, the circuit has high non-robust or robust testability. CAD Manuscript No. MS19015 (Accepted)
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Figure 2: A circuit with an exponential number of paths We conducted another experiment on an example suggested by Pomeranz and Reddy [1]. The circuit has the structure shown in Figure 2. The basic block, shown in the dashed line box, is repeated to obtain circuits of di erent sizes. The number of paths in a circuit, Ck , where the block is repeated k times is 3 2k ? 2. We use the label un to denote the upper input of the nth block, ln to denote the lower input of the nth block, and i to denote the center input of the rst block. We ran our estimator on C25 and C30 . We applied four vector pairs that detect a subset of falling path faults originating at input i. The vector pairs and the number of detected faults corresponding to each vector pair for C25 and C30 are given in Table 2. Table 2: Vector pairs and number of detected faults for C25 and C30
i u1 l1 u2 l2 Remaining inputs 1 0 1 0 1 0 1 0
0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1
1 1 0 0 1 1 0 0
11111... 11111... 11111... 11111... 11111... 11111... 11111... 11111...
# det. (C25 )
# det. (C30 )
223 = 8; 388; 608 228 = 268; 435; 456 223 = 8; 388; 608 228 = 268; 435; 456 223 = 8; 388; 608 228 = 268; 435; 456 223 = 8; 388; 608 228 = 268; 435; 456
Table 3 shows the results of the estimator run on a HP 9000 J200 workstation with 256MB of memory. Our estimator gives the exact result for both circuits. The time taken by the estimator is negligible and is independent of the number of detected faults. In contrast, the time and memory requirements for fault simulation are dependent on the number of detected faults. The fault simulaCAD Manuscript No. MS19015 (Accepted)
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Table 3: Coverage estimation for circuits with exponential number of paths Circuit # Vec Fault coverage estimators Fault simulator pairs # det. [1] # det. (SL = 3) CPU(s) # det. CPU (s) C25 4 25,165,824 33,554,432 0.4 33,554,432 642 C30 4 805,306,368 1,073,741,824 0.5 SL { Segment length tor was able to compute the number of detected path faults in C25 in a reasonable amount of time. However, it could not handle C30 due to the large number of detected faults. The 0-order approximation method [1] grossly underestimated the coverage. This is because all relevant signal lines are covered by tested path faults during the simulation of the rst three vector pairs. No additional faults are counted as detected on the fourth vector pair. Re-ordering of vector pairs, as suggested for improving the accuracy of the 0-order estimate [1], will not change the accuracy. The SL = 3 estimation in this case is exact and remains so for any arbitrary vector-pair ordering. Higher order approximations by taking cutsets such as all primary inputs [1] will also not improve the 0-order estimate. This experiment shows the limitation of a fault simulator in computing coverages of test sets that detect a large number of path faults. It also shows that the 0-order estimates become too pessimistic when several paths share a set of lines. In some cases, test set reordering [1] and polynomial time algorithms to nd maximum cardinality cutsets [5] can be used to improve the estimates. An alternate way, as described in this communication, is to increase the length of segments over which detectability status is maintained. Although the estimate will always remain pessimistic, the pessimism decreases with increasing lengths of segments.
4 Conclusion The proposed improvements to the count-based estimation of path delay fault coverage appear practical. The accuracy of estimation can be brought arbitrarily close to exact fault simulation by increasing the length of the path-segments over which detectability status is maintained. The results show that while a segment length of 1 or 2 may not be adequate, path-segments of length 3 provide reasonable accuracy. If a higher accuracy is desired, segment length 4 or larger may be used. In the limit the complexity of the estimation procedure reaches that of a fault simulator. However, it appears that we can obtain reasonable estimates and yet restrict the complexity close to linear in the number of lines, since the segment length does not have to be increased with the CAD Manuscript No. MS19015 (Accepted)
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circuit depth. The segment length can be reduced by using an ecient graph representation of the circuit where non-fanout nodes have been collapsed. Such a graph preserves the path structure [6]. An interesting problem is to nd the optimum segment length for a given circuit structure such that the estimation error is minimized or eliminated. Test set reordering [1] and polynomial time algorithms to nd maximum cardinality cutsets [5] are other alternatives to improve the accuracy of count-based estimators. However, our method of improving the accuracy of the estimation procedure is less susceptible to the nature of the circuit and the test set used, and hence, may be a viable alternative.
References [1] I. Pomeranz and S. M. Reddy, \An Ecient Non-Enumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits," IEEE Trans. CAD, vol. 13, pp. 240{250, Feb. 1994. [2] K. Heragu, Approximate and Statistical Methods to Compute Delay Fault Coverage. Master's Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, May 1994. [3] K. Heragu, M. Bushnell, and V. D. Agrawal, \An Ecent Path Delay Fault Coverage Estimator," in Proc. 31st Design Automation Conf., pp. 516{521, Jun. 1994. [4] K. Heragu, J. H. Patel, and V. D. Agrawal, \Improving Accuracy in Path Delay Fault Coverage Estimation," in Proc. 9th International Conf. on VLSI Design, pp. 422{425, Jan. 1996. [5] D. Kagaris, S. Tragoudas, and D. Karayiannis, \Improved Nonenumerative Path-Delay FaultCoverage Estimation Based on Optimal Polynomial-Time Algorithms," IEEE Trans. on CAD, vol. 16, pp. 309{315, Mar. 1997. [6] M. Gharaybeh, M. Bushnell, and V. D. Agrawal, \An Exact Non-Enumerative Fault Simulator for Path-Delay Faults," in Proc. International. Test Conf., pp. 276{285, Oct. 1996.
CAD Manuscript No. MS19015 (Accepted)
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Figure Captions
Fig. 1.
A circuit graph for path fault analysis
Fig. 2.
A circuit with an exponential number of paths
Table Headings
Table 1:
Robust coverages of path delay faults
Table 2:
Vector pairs and number of detected faults for C25 and C30
Table 3:
Coverage estimation for circuits with exponential number of paths
Footnotes
K. Heragu is with the Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL 61801, USA. V. D. Agrawal is with Bell Labs, Lucent Technologies, Murray Hill, NJ 07974, USA. M. L. Bushnell is with the Electrical and Computer Engineering Department, Rutgers University, Piscataway, NJ 08855, USA. J. H. Patel is with the Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL 61801, USA.
CAD Manuscript No. MS19015 (Accepted)
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CAD Manuscript No. MS19015: Heragu et al., Figure 1
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CAD Manuscript No. MS19015: Heragu et al., Figure 2
Circuit No. of Total No. Max. Estimated detected faults Faults Name vector path delay depth 0-order [1] SL = 2 SL = 3 det. by pairs faults SL = 1
t. sim. c880 10000 17284 25 176 680 744 749 c1355 10000 8346432 25 15 15 16 16 c1908 10000 1458114 41 159 421 495 506 c2670 10000 1359768 33 511 1389 1494 1536 c3540 10000 57353342 48 109 410 441 446 c5315 10000 2682610 50 913 3883 4248 4409 20 c6288 10000 1.9810 125 19 20 20 23 c7552 10000 1452986 44 470 2397 2895 2936 s298 94 462 10 239 299 333 343 s526 206 820 10 379 593 680 694 s820 405 984 11 452 896 957 980 s832 409 1012 11 521 910 954 984 s1488 601 1924 18 609 1613 1787 1875 s1494 602 1952 18 617 1621 1794 1882 SL { Segment length
CAD Manuscript No. MS19015: Heragu et al., Table 1
i u1 l1 u2 l2 Remaining inputs 1 0 1 0 1 0 1 0
0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1
1 1 0 0 1 1 0 0
11111... 11111... 11111... 11111... 11111... 11111... 11111... 11111...
# det. (C25 )
# det. (C30 )
223 = 8; 388; 608 228 = 268; 435; 456 223 = 8; 388; 608 228 = 268; 435; 456 223 = 8; 388; 608 228 = 268; 435; 456 223 = 8; 388; 608 228 = 268; 435; 456
CAD Manuscript No. MS19015: Heragu et al., Table 2
Circuit # Vec Fault coverage estimators Fault simulator pairs # det. [1] # det. (SL = 3) CPU(s) # det. CPU (s) C25 4 25,165,824 33,554,432 0.4 33,554,432 642 C30 4 805,306,368 1,073,741,824 0.5 SL { Segment length
CAD Manuscript No. MS19015: Heragu et al., Table 3
