The Last Byte
Is System in Package the Panacea for Integration? T.M. Mak Intel PEOPLE SELLING to the mobile communications
market have largely embraced the technology to try to reduce the form factor of ever smaller, fancier, and, should I say, sexier cell phones that have won over the hearts (and purses) of customers worldwide. (This is less so in the US, but that’s the subject for another discussion.) If you walked into a store in Hong Kong, Japan, or any major European city, you would be amazed at the mix of functionality these cell phones offer. Beyond the basic phone, they contain PDA-like functions, cameras and music players, and various data services. The newer ones have 802.11x, radios, and GPS; TV and video are around the corner. To support that level of integration, system-in-package (SiP) technology is probably buried somewhere in these products. With technology scaling, nature has not been kind to conventional analog circuit design. Although we can pack tens of billions of digital transistors on a chip, analog designers might wince at hearing integration at .13 μm or 90 nm, not to mention 65 nm or below. So, why don’t we let analog be analog and stay with its best process technology, be it .25 μm CMOS, or SiGe, or whatever analog is happy with, and integrate the chips within the package? By the way, flash memory and DRAM both require different processes, too. It’s hard to imagine that anyone can deal with the integration of these technologies onto a single piece of silicon. So, SiP becomes the obvious way to go, and the bean counter will also tell you that it is the most effective way to integrate. It seems that you can build a powerful system based on chips off the shelf. Is this so? In reality, it may be much harder to do so than it seems. SiP is not new. Its predecessor was the multichip module, and basically, all the problems are still there. There is the system integration issue (off-the-shelf functionality seldom matches what is needed for a system),
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and while glue logic is common for board design, glue logic for SiP is not feasible. Imagine the occasional need for a gate here and there to make a system work. There is also the known good die (KGD) issue (a bad die assembled into a SiP would render the whole stack unusable). Then there are the manufacturing test issues after the whole stack is put together. Ad hoc DFT may or may not exist for individual dies, if you buy existing dies. Therefore, SiP testing is usually done at the system level. Coverage and cost are the two horns of the bull with which test engineers have to wrestle. SiP is essentially an integration of a full set of custom designs. Mixing and matching existing dies is difficult if not impossible.
SO, WHERE SHOULD WE GO on the road of integra-
tion? To me, it would seem we cannot avoid the analog design issues from technology scaling. We just have to bite the bullet to figure how to design analog functionality with scaled technology. Much research, such as that conducted at the FCRP (Focus Center Research Program), is heading in this direction. The road to monolithic heterogeneous integration is not smooth and uneventful, but, if history is a guide, I’m sure that we’ll be able to overcome the challenges and continue to do wonderful things. ■ T.M. Mak is a research scientist responsible for conducting test research at Intel. Contact him at
[email protected].
Direct questions, comments, and contributions for this department to Scott Davidson, Sun Microsystems, 910 Hermosa Court, M/S USUN05-217, Sunnyvale, CA 94085;
[email protected].
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