Low-Power Digital Signal Processor Design for a ...

2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

Low-Power Digital Signal Processor Design for a Hearing Aid Lama Shaer

Ihab Nahlus

Jawad Merhi

Ayman Kayssi

Ali Chehab

Department of Electrical and Computer Engineering American University of Beirut Beirut 1107 2020, Lebanon {las24,inn02,jrm02,ayman,chehab}@aub.edu.lb Abstract — A new low-power digital signal processor (DSP) design for a hearing aid system is proposed. A stochastic method was applied to the DSP in order to fulfill the needs of the hearing aid system, considered to be an error-tolerant system. The different blocks that form the DSP are presented in this paper. The implementation and layout were performed and simulated using a 90 nm CMOS process. Simulation results showed excellent energy consumption savings in the range of 4.5x to 10x of the proposed DSP design when compared to similar DSPs.

battery life and thus further satisfy hearing aid users. We utilize a method that has been used in our previous work for a low-power adder [19]. We investigate the design of each of the different building blocks of this processor and then apply our low-power technique to the DSP, and verify its correctness using HSPICE and VHDL. The overall DSP design was then implemented using Cadence. The results show the practicality of this DSP for error-tolerant applications.

Keywords: digital signal processor, low power, stochastic, error-tolerant, energy consumption, hearing aid system.

The rest of the paper is organized as follows: Section II discusses related work. The design of our system is presented in section III. Section IV discusses the implementation of the system, and section V presents the testing results. We conclude with a summary and potential future work in section VI.

I.

INTRODUCTION

Despite the continuous aggressive scaling of CMOS technology and integrated circuits, the progression of battery technology at the hardware level is relatively very slow. The shortness of battery lifetime has been raised as a critical issue as batteries are used in almost all portable and wearable electronic devices. As a result, the low energy aspect has become an essential design factor for almost all such devices.

II.

There are many different architectures and design structures for a digital signal processor. Some methods are based on generic core architectures for a DSP processor. The authors of [2] presented a DSP circuit that was built according to a generic architecture and included analog-todigital and digital-to-analog converters for hearing instruments. Also, P. Mosch et al. [3] described a generic technique to build a low-power DSP.

This paper focuses on reducing energy consumption for hearing aid systems through the use of stochastic low power digital signal processors (DSP). DSPs are considered essential blocks in hearing aid systems and reducing power dissipation in them reduces the total energy consumed by the device. Although a stochastic DSP produces inaccurate results, this does not create problems when the target application is error-tolerant. Any application where results are perceived by human hearing and vision systems is error resilient and can be based on a stochastic processor [1]. The errors associated with voice do not cause problems to users as witnessed by multimedia applications such as Skype.

Other methods rely on building Fast Fourier Transform (FFT) and Interpolated Finite Impulse Response (IFIR) processors. K. Chone et al. [4] described an FFT processor and an inverse FFT processor for low-voltage and energycritical hearing aid systems. L. S. Nielsen and J. Sparsoe [5] presented an IFIR processor that relies on a filter bank structure for the use in low power devices. Most designs however rely on Application Specific Integrated Circuit (ASIC) designs for the DSP processor.

In this paper, we present a DSP processor that operates at low power while introducing some inaccuracies in the computations. The purpose of this processor is to reduce the energy consumption of hearing aid systems to prolong the

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RELATED WORK

The authors of [6-8] present designs that include the use of a filter bank structure where the frequency band is split

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2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

into multiple bands, and then each band is processed individually. R. Brennan and T. Schneider [6] describe a flexible filter bank structure for hearing aid applications taking into consideration the following requirements: limited memory, low power, and low delay. K. Chong et al. [7] present an FIR filter bank core with micro energy consumption and small area, with the advantages of a higher stop band attenuation and linear phase frequency response as compared to other designs. The authors of [8] present a low power design of a filter bank for digital hearing aids whereby a multi-rate FIR filter bank algorithm was developed and it showed that in comparison with a straightforward FIR filter bank, 96% of the multiplications and additions are saved.

power and requires a large area [17]. We still need multipliers for the volume control and the gains, however.

Although the use of a filter bank structure as presented in [6-8] grants a higher control over the different bands, two bands are usually enough: a high band and a low band. The most common designs consist of a band split filter that splits the frequency band into a high band and a low band as presented in [9-12]. Each band is then processed by itself; it is multiplied by a gain whose value can be manipulated through a serial interface or imported from memory, hence making the hearing aid tunable. Some designs use an automatic gain control (AGC) to ensure that the gain does not overshoot as in [10]. Other designs have a serial interface combined with the RAM instead of having them separated as in [11]. In addition, some designs have a volume control to digitally control the gain of the aid as in [9-11].

Figure 1: Digital Filter [11]

III. A.

The transfer function of this filter is expressed in[11] as follows: ‫ܪ‬ሺ‫ݖ‬ሻ ൌ ܸ‫ܥ‬ൣͲǤͷሺͳ ൅ ‫ܩ‬଴ ሻሺͳ ൅ ‫ି ݖ‬ସ ሻ െ ൫‫ܩܭ‬ଵ ൅ ‫ܩ‬ଶ ሺ‫ ܰܫ‬െ ‫ܭ‬ሻ൯ሺͲǤͷ െ ͲǤͷ‫ି ݖ‬ସ ሻ௣ ൧ B. Adder In order to make the DSP stochastic, we apply a method that we previously used for the design of a ripple carry adder and whereby we achieved 167% savings in energy consumption [19]. The method consists of applying multiple supply voltage levels to different parts of the circuit and making sure that the voltage level is adequate on the critical path in order not to affect performance. The parts that are affected might generate some errors but are associated with the least significant bits. Hence, we achieve substantial energy savings while allowing for small errors only (in the low-order bits) to be introduced.

SYSTEM DESIGN

Digital Filter

In our design, we are targeting a simple hearing aid that provides a basic functionality with minimal energy consumption.

C. Multiplier The multiplier is the most critical component of the DSP since it is the slowest and therefore, it will define the frequency of operation. Sequential multipliers were used in the DSP design whereby we are either multiplying 16 bits by 4 bits or 20 bits by 4 bits. Therefore, we used 16×4 and 20×4 sequential multipliers that consist of a maximum of 3 additions. These multipliers perform much less computations than other commonly used multipliers and hence consume much less energy.

The digital filter used is shown in Figure 1. This filter uses a band-pass filter and a notch filter [17]. In contrast to the traditional band-splitting scheme with a low-pass and a high-pass infinite impulse response (IIR) filters, this structure uses an FIR filter and reduces both power consumption and physical size while obtaining comparable results. This is because the IIR filter suffers from finite word-length problems and consumes more power than the FIR filter [18]. Moreover, the IIR filter has inevitable error accumulation and phase non-linearity. Another reason why this transfer function is widely used is because the coefficients of the filter are powers of 2; consequently, we can do hardwired shifting for most parts instead of using many multipliers whereby each multiplier consumes a high

In our sequential 16×4 multiplier, we multiply the 16 bits by 2, 4, and 8 and we obtain 4 modified versions of the input (including itself), which are then fed to multiplexers. The other 4 bits serve as control signals to these multiplexers. Finally, The 4 outputs of the multiplexers are

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2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

added using three 20-bit ripple-carry adders. The same is done for the 20×4 multiplier. D. Delay Unit We have used several delay units in the DSP design that were implemented using D flip-flops. The DSP was implemented using static CMOS since it leads to relatively lower energy consumption and most importantly it leads to a more robust design. Robustness is a very important characteristic because while applying the stochastic technique, the noise margins will shrink due to reduced supply voltage levels. E. Multi VDD Design We already know that reducing the voltage supply will reduce power consumption but will increase delay. Some components in the DSP processor might need to be fast while others are more elastic when it comes to speed. This is why we chose to have multiple voltage supplies in our circuit so we can satisfy both the speed and energy requirements.

Figure 3: DSP Schematic We also extracted the design to HSPICE after setting the minimum parasitic resistance value to 250 ȍ and the minimum parasitic capacitance value to 10-15 F. This extraction had around 450 resistors and 10,000 capacitors. The area occupied by the DSP layout (shown in Figure 4) is roughly 39000 nm2.

Typically, the availability of different supplies on one chip is not a problem due to voltage islands and DC-to-DC converters already present on the chip. As stated in [20], two to four supplies are more than enough. We chose to use two voltage supplies, referred to as VDDHIGH and VDDLOW IV.

SYSTEM IMPLEMENTATION

The DSP consists of several blocks and sub-blocks as shown in Figure 3 (as extracted from Cadence): (A) twelve 16-bit flip-flops (B) five 16-bit ripple carry adders (RCAs) (C) three 20-bit RCAs (D) three 16x4 multipliers (E) one 20x4 multiplier (F) two 16-bit multiplexers (G) one 16-bit multiplexer.

Figure 4: DSP Layout

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2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

V.

TESTING RESULTS

TABLE I. Case I Results

We generated a vector file for the inputs of the DSP using JAVA’s pseudo random number generator. Our target was to vary VDDHIGH and VDDLOW to reach maximum savings in power consumption, even if this incurs some errors in the system. The clock frequency used was set to 10 MHz.

Supply Voltage (V) 0.8 0.7 0.6 0.5 0.4 0.3

There are two major steps in checking for the validity of the DSP design. We need to check the correctness of the design itself and the post simulation results. To establish the first step, we designed the filter using VHDL and simulated it while inputting a raw audio file and outputting the modified raw audio file. Then, the modified raw audio file was converted into a usable format (MP3) and compared to the original MP3 file. This is summarized in Figure 5.

Power Consumption (ȝW) 120 86.22 57.36 37.08 21.93 9.841

When the two supplies were further reduced to 0.3 V, the digital signal processor started producing some errors. If we are to use this supply level, we can save an additional 10% in power consumption, summing up to a total 92%. The percentages of errors in each bit in the output O are presented in Table II, where O23 is the most significant bit (MSB) and O0 is the least significant bit (LSB) of the output.

Figure 5: Verifying Correctness (step1)

TABLE II. Percentage Errors in Bits

After validating the design, we proceeded to the second step, which is verifying the correctness at the bit level by comparing the output of the HSPICE simulator to the output of the VHDL simulator. We simulated the random vectors coming out of JAVA’s pseudo random number generator. This is illustrated in Figure 6.

O0

O1

O2

O3

O4

O5

O6

O7

25%

15%

25%

60%

60%

10%

25%

35%

O8

O9

O10

O11

O12

O13

O14

O15

25%

15%

25%

35%

20%

10%

40%

15%

O16

O17

O18

O19

O20

O21

O22

O23

20%

25%

15%

15%

10%

10%

10%

10%

B. Case II: Scaling VDDLOW In this case, several combinations for VDDHIGH and VDDLOW were tested in order to achieve a good reduction in energy consumption yet with reasonable errors that do not affect the most significant bits, as was the case in the previous test scenario. The results are summarized in Table III.

Figure 6: Verification (step 2)

Here, two cases were tested. The first is the case in which both supply voltages were scaled down, and the second is the case where only VDDLOW was scaled down.

TABLE III. Case II Results

A. Case I: Scaling Both Supply Voltages In this case, both voltage supply voltages were gradually scaled down from 1 V to 0.3 V. The results are summarized in Table I. We can see that there is a 90% reduction in power consumption from the case of normal VDD (1 V) to the case where both supply voltages were set to 0.4 V. In this specific case, the system was fully functional without errors.

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Test

VDDHIGH

VDDLOW

Power Consumption (uW)

1

0.8

0.7

118.5

2

0.8

0.6

98.6

3

0.8

0.3

92.1

4

0.7

0.5

87.32

2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

[6] Brennan, R.; Schneider, T.; "A flexible filterbank structure for extensive signal manipulations in digital hearing aids,", IEEE International Symposium on Circuits and Systems, (ISCAS’98) pp.569-572, 31 May-3 Jun 1998. [7] Kwen-Siong Chong; Bah-HweeGwee; Chang, J.S.; "A 16Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids," IEEE Transactions on Circuits and Systems II: Express Briefs, , vol.53, no.9, pp.853-857, Sept. 2006. [8] Yu-Ting Kuo; Tay-Jyi Lin; Yueh-Tai Li; Chih-Wei Liu;, "Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids," IEEE Transactions on Circuits and Systems I,, vol.57, no.7, pp.1684-1696, July 2010. [9] Sunyoung Kim; Namjun Cho; Seong-Jun Song; Donghyun Kim; Kwanho Kim; Hoi-Jun Yoo;, "A Sub 1V 96 ȝW Fully Operational Digital Hearing Aid Chip With Internal Status Controller," the 32nd European Solid-State Circuits Conference (ESSCIRC’06), pp.231-234, 19-21 Sept. 2006. [10] Gata, D.G.; Sjursen, W.; Hochschild, J.R.; Fattaruso, J.W.; Fang, L.; Iannelli, G.R.; Jiang, Z.; Branch, C.M.; Holmes, J.A.; Skorcz, M.L.; Petilli, E.M.; Chen, S.; Wakeman, G.; Preves, D.A.; Severin, W.A.; "A 1.1-V 270-ȝA mixed-signal hearing aid chip," IEEE Journal of Solid-State Circuits, ,vol.37, no.12, pp. 1670- 1678, Dec 2002. [11] Yoo, J.; Sunyoung Kim; Namjun Cho; Seong-Jun Song; HoiJun Yoo; "A 10ȝW digital signal processor with adaptiveSNR monitoring for a sub-1V digital hearing aid," IEEEInternational Symposium on Circuits and Systems. (ISCAS’06), 21-24 May 2006. [12] Sunyoung Kim; Namjun Cho; Seong-Jun Song; Donghyun Kim; Kwanho Kim; Hoi-Jun Yoo; "Clearphone: A 0.9 V 96 ȝW digital hearing aid system," IEEE Biomedical Circuits and Systems Conference (BioCAS’06), pp.182-185, Nov. 29 2006-Dec. 1 2006. [13] Jan M. Rabaey, ANanthaChandrakasan, and BorivojeNikolic “Digital Integrated Circuits”, Prenticehall, 1996. [14] MoumitaGhosh ,“Design And Implementation Of Different Multipliers Using VHDL”. http://ethesis.nitrkl.ac.in/66/1/moumita.pdf [15] Ko-Chi Kuo; Carlson, B.S.; "High performance CMOS static logic circuit design," the 44th IEEE Midwest Symposium on Circuits and Systems, (MWSCAS’01),pp.598-601, 2001. [16] Linfeng Li; Jianping Hu; "A transmission gate flip-flop based on dual-threshold CMOS techniques," the 52nd IEEE International Midwest Symposium on Circuits and Systems, pp.539-542, 2-5 Aug. 2009. [17] Walter P. Sjursen, “Hearing aid digital filter”, U.S. Patent 6 292 571 B1, Sep. 2001. [18] Emmanuel C. Ifeachor and Barrie W. Jervis, “Digital Signal Processing 2nd Edition”, Pretence Hall,. [19] I. Nahlus, L. Shaer, A. Chehab, A. Kayssi, M. Mansour, “Low-power adder design techniques for noise-tolerant applications” in IEEEWorkshop on Signal Processing Systems (SIPS), October 4-7, 2011, Beirut, Lebanon. [20] Rabaey, J.; “Low Power Design Essentials”, Springer 2009.

As seen from Table III, the power consumption was reduced in tests 2, 3 and 4. For test 1, the reduction in power compared to Case I (at 0.8 V) is negligible. Moreover, in case 3, we started having erroneous results. Although the errors were mostly present in the least significant bits, as expected, the power consumption was still higher than what we got in Case I. Comparing our design to other designs in literature, the results show a major improvement. It was previously reported that a similar DSP consumes 100 ȝW as in [10] and [11]. Comparing this value with the values of Case I corresponding to the 0.4 V level and the 0.3 V level, we can see a 78% and 90% reduction in power consumption, respectively. VI.

CONCLUSIONS AND FUTURE WORK

We presented a hearing aid design that minimizes energy consumption by utilizing stochastic techniques, which translates into higher battery lifetime. Simulation results showed 78% to 90% savings in energy consumption when compared to similar DSPs. The design can also be used for other error-tolerant applications. For future work, different variations of this DSP design for other error-tolerant applications will be investigated.

ACKNOWLEDGMENTS This work was supported by Intel’s Middle East Energy Research (MER) Program.

REFERENCES [1] Roundtable Discussion, “Designing Chips without Guarantees,” IEEE Design & Test of Computers, Vol. 27, No. 5, pp. 60-67, 2010. [2] H. Neuteboom, B.M. Kup&M.Janssens, "A DSP-Based Hearing Instrument IC" IEEE J. Solid-state Circuits, vol. 32, no. 11, pp. 1790–1806, Nov. 1997. [3] Mosch, P.; van Oerle, G.; Menzl, S.; Rougnon-Glasson, N.; Van Nieuwenhove, K.; Wezelenburg, M.; , "A 660-ȝW 50Mops 1-V DSP for a hearing aid chipset," IEEE Journal of Solid-State Circuits, , vol.35, no.11, pp.1705-1712, Nov 2000. [4] Kwen-Siong Chong; Bah-HweeGwee; Chang, J.S.;, "EnergyEfficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors," IEEE Journal of Solid-State Circuit,, vol.42, no.9, pp.2034-2045, Sept. 2007. [5] Nielsen, L.S.; Sparso, J.; "Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid," Proceedings of the IEEE, vol.87, no.2, pp.268-281, Feb. 1999;DOI: 10.1109/5.740020.

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