Low power ECRL logic based parallel self-timed adder

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

Low power ECRL logic based parallel self-timed adder A N Jayanthi1 , D.Prabhu2, B.Sibiram3

1

2,3

Associate professor, Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India,

UG Students-Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India.

Abstract: fan-outs A

parallel

self-timed

adder

suitable for adoption in fast adder

recursive formulation and uses half and

performing addition.

multiplexers multi-bit

implementation

for

performance

binary

Theoretically

the

is

approach

attains

the

new

logarithmic

propagation

using tool

SPICE by

circuit linear

and

better

power

optimization is also achieved using the proposed system of Effective

implementation of the design along

charge recovery logic(ECRL) by

with completion detection unit is design

The

adders. A constant time carry

schema. The corresponding CMOS

The

processors.

its superiority over cascaded circuit

speed-up circuitry or look-ahead

presented.

high-

technology. Simulation results show

performance without any special

also

tested

simulation

that do not need any carry chain Thus

in

performance of the implementation

operation is parallel for those bits

propagation.

complex

interconnections. Thus it is more

(PASTA) is designed. It is based on

adders

or

tuning the CMOS parameters.

is

regular and does not have any

Keywords:Logarithmic

practical limitations of fan-ins or

performance , CMOS implementation ,SPICE,ECRL.

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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

dissipation Simulations have been

Introduction

performed using Tanner EDA tool

Binary addition is the single most

that verify the improvement made by

important operation that a processor performs. Most of the adders have

the proposed approach over existing

been

asynchronous adders.The design of

designed

for

synchronous

PASTA is regular and uses half-

circuits even though there is a strong

adders (HAs) along with multiplexers

interest in clockless asynchronous circuits.

requiring minimal interconnections.

The proposed heuristic

Thus,

approach also forms the basis for

it

is

suitable

for

VLSI

implementation. The design works in

realizing many self-timed adders. The

a parallel manner for independent

performance potential of single-bit adder blocks, which adopt widely

carry

preferred

data

implementation in this brief is unique

encoding styles, are analyzed on the

as it employs feedback through XOR

basis

of

homogeneous

the

self-timed

chain

blocks.

The

logic gates to constitute a dual-rail

adder

cyclic asynchronous sequential adder.

architecture. The operation is parallel for those bits that do not need any

Cyclic circuits can be more resource

carry chain propagation. But it has

efficient

than

their

acyclic

counterparts. On the other hand, wave

practical limitations of high fan-outs

pipelining

which makes continuous transitions.

(or

maximal

rate

To overcome continuous transitions

pipelining) is a technique that can

ECRL gates are used which acquire

apply pipelined inputs before the outputs are stabilized. The proposed

power and become active only when

circuit manages automatic dual-rail

performing useful computations, and idle ECRL gates are not powered and

pipelining

of

the

carry

inputs

thus have negligible leakage power

separated by propagation and inertial delays of the gates in the circuit path. 12495

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

General Block Diagram

Fig(a)8bit parallel self timed adder

The selection input for two-input multiplexers corresponds to the Requesthandshake signal and will be a single 0 to 1 transition denoted by SEL. It will initially select the actual operands during SEL = 0 and will switch to feedback/carry paths for subsequent iterations using SEL = 1. The feedback path from the HAs enables the multipleiterations to continue until the completion when all carry signals will assume zero values.

Fig(b) Multiplexer

Existing System The architecture and theory behind PASTA ispresented. The adder first accepts two input operands to perform half additions for each bit. Subsequently, it iterates using earlier generated carry and sums to perform half-additions repeatedly until all carry bits are consumed and settled at zero level.Here 8-bit adder is designed by using tanner EDA software by using single rail logic.

Fig(c) Half adder’s sum operation

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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

Fig(d) Half adder’s carry operation Fig(g) Power report

IMPLEMENTATION A CMOS implementation for the recursive circuit is shown in Fig(a). For multiplexers and AND gates we have used TSMC library implementations while for the XOR gate we have used the faster tentransistor implementation based on transmission gate XOR to match the delay with AND gates The completion detection following is negated to obtain an active high completion signal (TERM)

Fig(e) Completion detection unit

Fig(f) Simulation waveform for input a7a6a5a4a3a2a1a0=00010000

Proposed System The architecture and theory behind PASTA ispresented. The adder first accepts two input operands to perform halfadditions for each bit. Subsequently, it iterates using earlier generated carry and sums to perform half-additions repeatedly until all carry bits are consumed and settled at

b7b6b5b4b3b2b1b0=00001100

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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

zero level.Here 8-bit adder is designed by using tanner EDA software by using Effective charge recovery logic.

power-gating technique, stacking transistor techniques, Variable Threshold CMOS (VTCMOS) and Input Vector Control (IVC) have been proposed to reduce sub-threshold leakage.

Effective charge recovery logic

The dynamic power dissipation of adiabatic logic circuits can be reduced effectively by using adiabatic computing for node capacitances. However, the previously proposed leakage reduction techniques focus mainly on conventional CMOS circuits. In adiabatic circuits, there also exist leakage dissipations similar to the traditional CMOS circuits. To the best of our knowledge, the logic circuits based on adiabatic computing with DTCMOS and gate-length biasing techniques have not been presented. In present study, an Effective Charge Recovery Logic (ECRL) based on adiabatic computing with dual-threshold CMOS (DTCMOS) and gate-length biasing techniques is proposed. In the ECRL circuits, combinational logic blocks are supplied by a single-phase power clock, while flip-flops are driven with two-phase non-overlap power clocks. In order to reduce sub-threshold leakage dissipations, DTCMOS and gate-length biasing technique are used for the ECLR circuits. The ECRL flip-flops are also presented. An ISCAS s27 benchmark circuit using DTCMOS and gate-length biasing techniques is verified.

Adiabatic computing (also known as charge recovery logic) utilizes AC power clock to recover effectively the charge delivered by the clock instead of being dissipated to the ground. In order to reduce dynamic power consumption, many new logic circuits based on adiabatic computing, such as Complementary Pass-transistor Adiabatic Logic (CPAL) Clocked Adiabatic Logic (CAL) Effective Charge Recovery Logic (ECRL) have been proposed. They all obtained significant dynamic energy dissipations savings by recycling the energy stored in circuit nodes. With the feature size continuing to reduce, the leakage dissipation caused by leakage catches up with the dynamic power consumption gradually. There are several leakage sources in nanometer CMOS processes: Sub-threshold leakage current, gate leakage current and band-to-band tunneling leakage current .Sub-threshold leakage currents are the main sources of static power consumptions in recent nanometer CMOS processes. Several leakage reduction techniques, such as Dual-Threshold CMOS (DTCMOS), Multi-Threshold CMOS (MTCMOS) 12498

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

• The energy dissipation of combinational logic can be made arbitrarily small • Information loading into memory circuits consume small amount of energy • Erasing last copy of a piece of information inevitably dissipates an irreducible finite amount of energy • Inputs of one stage needs to be stable before they are applied • While inputs are asserted, the supply is in evaluation mode • Outputs of one stage needs to be stable while evaluated by the next stage • Energy is recovered during the ramp-down of the power supply. • While output is de-energized, the power supply is idle

Fig(ii)ECRL based

Multiplexer INTERNAL STRUCTURE OF MULTIPLEXER

Fig(ii)(a) ECRL based AND gate

Fig(i) ECRL based 8bit parallel self timed adder

Fig(ii)(b) ECRL based OR gate

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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

Fig(iii) ECRL based xor gate for sum operation

Fig(g) Power report

Conclusion This brief presents an efficient implementation of a PASTA.Initially, the theoretical foundation for a dualrail wave-pipelined adder is established. Subsequently, the architectural design and CMOS implementations are presented. The design achieves a very simple 8-bit adder that is area and interconnectionwise equivalent to the simplest adder namely the RCA. Moreover, the circuit works in a parallel manner for independent carry chains, and thus achieves logarithmic average time performance over random input values. The completion detection unit for the proposed adder is also practical and efficient. Simulation results are used to verify the advantages of the proposed approach. And the power consumed in existing system is about 1.97 *10^(-3) has been reduced to 0.42*10^(-3) in the proposed system.

Fig(iv) ECRL based AND gate for carry operation

Fig(v)Simulation waveform for input a7a6a5a4a3a2a1a0=00010000 b7b6b5b4b3b2b1b0=00001100

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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 16 (2015) © Research India Publications ::: http://www.ripublication.com

Reference [1] M. Z. Rahman, L. Kleeman and M.A.Habib “Recursive approach to the design of a parallel self-timed adder”, IEEE Trans. VLSI.,vol.23,NO.1.Jan. 2015.

[2]S. Nowick, “Design of a lowlatency asynchronous adder using speculative completion,” IEE Proc. Comput. Digital Tech., vol. 143, no. 5, pp. 301–307, Sep. 1996.

[3]M. Anis, S. Member, M. Allam, and M. Elmasry, “Impact oftechnology scaling on CMOS logic styles,” IEEE Trans. CircuitsSyst., Analog Digital Signal Process., vol. 49, no. 8, pp. 577–588,Aug. 2002. [4] D. Geer, “Is it time for clockless chips? [Asynchronousprocessor chips],” IEEE Comput., vol. 38, no. 3, pp. 18–19,Mar. 2005.

[5] A. N. Jayanthi and C .S. Ravichandran, „Performance Optimization of Carry Select Adders Using Variable Latency Design Style‟ in Journal of Scientific & Industrial Research, vol. 73, May 2014, pp.290293.

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