Methods for Reducing Events in Sequential Circuit Fault Simulation

Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 546-549, November 1991

Methods for Reducing Events in Sequential Circuit Fault Simulation Elizabeth M. Rudnick

Center for Reliable and High-Performance Computing University of Illinois Urbana, IL 61801

Thomas M. Niermann

Janak H. Patel

Sunrise Test Systems Inc. Sunnyvale, CA 94086

Abstract

Methods are investigated for reducing events in sequential circuit fault simulation by reducing the number of faults simulated for each test vector. Inactive faults, which are guaranteed to have no eect on the output or the next state, are identi ed using local information from the fault-free circuit in one technique. In a second technique, the StarAlgorithm is extended to handle sequential circuits and provide global information about inactive faults, based on the fault-free circuit state. Both techniques are integrated into the PROOFS synchronous sequential circuit fault simulator. An average 28% reduction in faulty circuit gate evaluations is obtained for the 19 ISCAS-89 benchmark circuits studied using the rst technique, and 33% reduction for the two techniques combined. Execution times decrease by an average of 17% when the rst technique is used. For the largest circuits, further improvements in execution time are made when the Star-Algorithm is included.

1 Introduction

Fault simulators are used extensively in the design of electronic circuits. A typical application is to nd all faults detected by a given test vector after the computationintensive test generation process. Initially, a list of all faults in the circuit is obtained; we will consider the single stuck-at fault model, in which a faulty machine is the circuit with one line xed at logic 1 (stuck-at-1 fault) or xed at logic 0 (stuck-at-0 fault). For each test vector, the good machine (fault-free circuit) and the faulty machines are simulated; if the output responses of a faulty machine dier from those of the good machine, then the corresponding fault is detected, and the fault is removed from the list of undetected faults. Only undetected faults are simulated for subsequent test vectors. Fault dropping is possible in concurrent [1, 2] and deductive [3] fault simulation, as well as in the PROOFS fault simulator [4], since each faulty machine depends only on the state of the same faulty machine in the previous time frame and the good machine state. With dierential fault simulation [5], fault dropping is more dicult, since each faulty machine depends on the previous faulty machine for its simulation. With parallel fault simulation [6], faulty machines are grouped statically, and fault dropping is not possible. Further reductions can be made in the number of faults simulated for each test vector. In one technique, local information from the fault-free circuit is used in deciding  This research was supported by the Semiconductor Research Corporation under Contract SRC 90-DP-109.

Center for Reliable and High-Performance Computing University of Illinois Urbana, IL 61801

whether to simulate each fault. In the Star-Algorithm [7] as de ned for combinational circuits, global information about the fault-free circuit is used to determine the nodes which do not aect the output values, and therefore, the faults which cannot be detected with a given vector. In this work, we extend the Star-Algorithm to sequential circuits and integrate the two inactive fault identi cation techniques into the PROOFS sequential circuit fault simulator. First we will explain the notion of inactive faults. The PROOFS fault simulation algorithm will then be described brie y, followed by discussions of inactive fault identi cation. Results of fault simulation runs for several ISCAS benchmark circuits [8] are then given.

2 Inactive Faults

A fault which has no eect on the terminal behavior of a machine will be termed inactive and need not be simulated, since the terminal behavior of the faulty machine is the same as that of the good machine. Let us consider the behavior of a sequential machine at time t under the input vector V (t), as shown in Figure 1. Let the present state and the next state be denoted SG (t) and SG (t + 1) for the good (fault-free) machine and SF (t) and SF (t + 1) for the faulty machine, respectively. Similarly let YG (t) and YF (t) be the outputs of the good machine and the faulty machine. V(t)

S (t)

V(t)

S (t+1) G

G

Good Machine YG (t)

S (t) F

S (t+1) F

Faulty Machine Y (t) F

Figure 1: Sequential Machine De nition: A fault is considered inactive at time t if (i) YG (t) = YF (t) and (ii) SG (t + 1) = SF (t + 1) In general, the Y and S vectors are boolean cubes containing 0, 1, and X values, and equality means the boolean cubes are identical. In particular, an X in one cube must match an X in the other. In sequential circuits, even if the input vectors are fully speci ed, unknowns occur due to uninitialized state variables. Considering that the output Y also may contain X values, when do we say that a fault is propagated to an output? Two commonly accepted

de nitions for fault detection exist. A fault is considered detected if YG (t) 6= YF (t) and there exists at least one bit position in which YG (t) has a 0 and YF (t) has a 1, or YG (t) has a 1 and YF (t) has a 0. A fault is considered potentially detected if it is not detected by the above de nition but YG (t) 6= YF (t) and YF (t)  YG (t); i.e., the good output contains a known 0 or 1 value, while the faulty output has an X in the corresponding position. Restricting our attention to the de nitely detectable faults, we can relax the de nition of inactive faults. De nition: A fault is considered weakly inactive at time t if (i) YF (t)  YG (t) and (ii) SG (t + 1) = SF (t + 1) Potential detections are useful in situations where it is impossible to have a de nite detection, e.g., faults on global reset or other control lines. The physical device under test always provides a measurable voltage level, and when a large number of test vectors are applied, there is a high probability that the faulty value is dierent from the known good value for at least one vector. Therefore, we will use the (strongly) inactive de nition where potential detectability matters, but the numeric results for fault coverage will report only the de nitely detected faults.

3 PROOFS

The PROOFS [4] fault simulator combines the advantages of the concurrent, parallel, and dierential fault simulation algorithms to provide fault dropping while exploiting the word-level parallelism of the computer and retaining a low memory requirement. Several faulty machines are simulated at once, with one bit space of the computer word used for each faulty machine, and faults are grouped dynamically with each test vector applied in order to fully utilize all the bit spaces in the computer word. Detected faults are removed from the fault list. Faults are injected by modifying the circuit to re ect the active faults, rather than by using faulty bit masks at every line, avoiding the extra computation overhead. For each faulty machine in the fault list, a linked list of state nodes which are dierent from the good circuit is maintained. Corresponding values are inserted into the circuit with the next test vector. The dynamic fault grouping strategy divides the faulty machines into groups of 32 for each test vector applied. To choose the next group of 32 faults from a statically ordered fault list, the list of undetected faults is traversed linearly, and a fault is added to the fault group only if it cannot be determined to be inactive. It is important that the group of 32 faults be very similar in their activity. In the best case, all 32 faults behave identically, and the number of gate evaluations required is the same as that for simulating a single fault. A speedup of 32 results. In the worst case, none of the 32 faults have common events, and the number of gate evaluations is equal to the sum of gate evaluations for serial simulation of the 32 faults. The fault order obtained by traversing the circuit from the primary outputs in a depth- rst order reduced the number of gate evaluations in half compared to a random order [4]. The removal of inactive faults results in further reduction in gate evaluations. The following two sections give methods of identifying inactive faults.

4 Zero-, One-, and Two-Level Inactive Fault Identi cation In this section, we give three related algorithms for identifying many inactive faults using local information from the fault-free circuit. Theorem: A fault is inactive, in the current time frame, if the states of the good and faulty machines are the same at the beginning of the time frame and one of the following three conditions (also shown in Figure 2) is met. 1. The good machine value is the same as the stuck-at value (e.g., a good machine value of 0 on line L for fault L s-a-0). 2. The fault is excited but not propagated one gate level, i.e., the gate has one of its inputs set to a controlling value. 3. The fault is propagated one gate level but not through the second level of gates, i.e., each gate connected to the output of the rst-level gate has one of its inputs set to its controlling value. stuck-at 0 0

(1) Fault not excited stuck-at 0 1

0 stuck-at 0 1 1 1

0

(2) Fault excited but not propagated 1 level

(3) Fault excited but not propagated 2 levels

Figure 2: Inactive Fault Classes

Proof: Since present states in both machines are the same and the fault eect does not travel beyond two levels, the next state and the outputs for both machines will be the same. 2 Removal of faults meeting these conditions will be referred to as zero-, one-, and two-level inactive fault removal.

5 Inactive Fault Identi cation with the Star-Algorithm

Akers, Krishnamurthy, et al. [7] present several algorithms for identifying inactive faults in combinational circuits; we extend one of their algorithms for sequential circuits. Only Algorithm 1, which we will refer to as the Star-Algorithm, is applicable to sequential circuits. Beginning with a test vector and the good circuit values on every node, the Star-Algorithm generates a subset of nodes, marked star (*), whose logic values adequately justify all of the primary output values. The values on all nodes not marked star have no eect on the output, and hence faults on these nodes are inactive in a combinational circuit. In the original paper, nodes not marked were assigned an X. To avoid the confusion between an unknown X and a don't care X, we will use two distinct symbols: u for unknown and d for don't care. In the Star-Algorithm, all nodes not marked star are truly don't care and hence will be marked d. The original algorithm did not handle unknowns. Here we give a brief description of the modi ed Star-Algorithm which includes 0, 1, and u values. Stars are placed at all primary outputs and are backtraced through the circuit to the primary inputs. Star

backtracing is shown in Figure 3 for AND and OR gates. The node values shown are those evaluated for the good * 11 * 1 *

1

d 1 * 0u d

0

* 1u * * u

* * u

*

* 00 * * 0

0

*

* 1 d 0 d u

1

* u0 * u

u

*

* *

Figure 3: Star Backtracing in the Star-Algorithm

circuit with the current test vector and circuit state. For AND gates with output values of 0, one 0-input is selected as the controlling value, and a star is placed on that input. Similarly, for an OR gate with an output value of 1, a star is placed on one 1-input. If the output value of an AND gate is 1 or unknown, then a change in any input may aect the output value, so stars must be placed at all inputs. Stars at the outputs of NAND and NOR gates are backtraced in a similar manner, while stars at the outputs of all other components are backtraced directly to the inputs. After backtracing of stars is complete, d's are placed on lines with no stars. For sequential circuits, stars must be placed at all ip

op inputs, in addition to primary outputs, since changes in the state may be detected at the primary outputs in later time frames. Stars are then backtraced to the primary inputs and to the outputs of ip ops, as for combinational circuits, and d's are placed on lines without stars. Theorem: A given fault is inactive in the current time frame if its Star-Algorithm value at that node is a d and the present state of the faulty circuit matches the present state of the good circuit. (The good and faulty circuit states match if any state nodes having dierent good and faulty circuit values also have Star-Algorithm d's.) Proof: Since the don't care nodes have no eect on the outputs or the next state and since the present states of both machines are eectively identical, the outputs and next states of the two machines are the same. 2 If more than one gate input has a controlling value, then one is chosen for star propagation. Various heuristics can be used to select a controlling input; the best choice will propagate the fewest number of stars throughout the circuit, thus maximizing don't cares. The most controllable input is likely to constrain the fewest number of nodes. A star may already exist on a line if it is on a fanout branch; selection of such a line will minimize the propagation of stars. Also, if a fault is already detected, then it will not be injected; therefore it is not useful to identify the fault as inactive, and placing a star on the line may be bene cial. Note that the Star-Algorithm executes the same independent of how many faults remain to be simulated. In contrast, the algorithm of the previous section spends time proportional to the number of faults remaining.

6 Results

The Star-Algorithm and zero-, one-, and two-level inactive fault removal techniques were implemented in C++ and integrated into the PROOFS sequential circuit fault simulator. The fault simulator was run on a SUN 4/280 for several ISCAS benchmark circuits [8] with test vectors

generated by the sequential circuit test generator STG3 [9]. The circuits and test vectors are described in [4]. The fault simulator was run for each of the following cases: 0: original algorithm, 0-level inactive fault removal 1: 1-level fault removal 1,2: 1- & 2-level fault removal *1: Star-Algorithm, star on most controllable input *2: Star-Algorithm, star on fanout branch having star *3: Star-Algorithm, star on input with detected fault *4: Star-Algorithm, combine *2, *3, *1 *1+: 1- & 2-level, Star-Algorithm, *1 *2+: 1- & 2-level, Star-Algorithm, *2 *3+: 1- & 2-level, Star-Algorithm, *3 *4+: 1- & 2-level, Star-Algorithm, combine *2, *3, *1 In an event-driven fault simulation, performance is dominated by the number of gate evaluations, not by the number of faults simulated. Inactive faults do not cause many events, so the number of injected faults is an inaccurate measure. Execution time alone can be used as a performance measure, but it is hard to separate the inherent merit of a heuristic from programming style and eciency. Therefore, we present data on both gate evaluations and execution time. The number of gate evaluations in the faulty circuits for each case are shown in Table 1. Removal of one- and twolevel inactive faults results in the greatest reduction in gate evaluations for most circuits. For the largest circuits, however, the number of gate evaluations was less when inactive faults were removed with the Star-Algorithm. Combining the Star-Algorithm with one- and two-level inactive fault removal resulted in the lowest number of gate evaluations. Faulty circuit gate evaluation counts for groups of 10 test vectors are shown for the s35932 circuit in Figure 4. 1400 1200

Faulty 1000 Circuit 800 Gate Evaluations (1000’s) 600

0-level fault removal only 1- and 2-level fault removal Star-Algorithm + 1- and 2-level

400 200 10 20 30 40 50 60 70 80

Test Vectors Applied

Figure 4: Number of Gate Evaluations vs. Test Vectors Applied for s35932

Fault simulation execution times are shown in Table 2 for the PROOFS algorithm with zero-level inactive fault removal, one-level inactive fault removal, one- and twolevel inactive fault removal, the Star-Algorithm, and the Star-Algorithm combined with one- and two-level inactive fault removal. Execution times decrease an average of 17% with one- and two-level inactive fault removal, but increase for many of the smaller circuits when the Star-Algorithm is added, due to the extra computations involved. For the largest circuits, however, both techniques contribute equally to reducing execution time, and combination of the two techniques can provide further improvements.

Circuit s298 s344 s349 s382 s400 s420 s444 s526 s641 s713 s820 s832 s953 s1238 s1423 s1488 s1494 s5378 s35932

0 1 1,2 36 28 25 24 21 20 24 21 21 581 538 530 495 424 409 107 77 69 725 638 618 575 399 343 55 34 31 63 40 33 269 171 139 255 159 130 72 67 64 178 105 82 127 113 110 621 476 446 535 402 370 2401 2104 2003 6218 5548 5284

*1 *2 *3 *4 32 32 32 32 22 21 22 22 22 22 22 22 557 554 557 553 467 465 468 465 77 77 76 75 660 658 661 658 496 493 496 493 42 41 38 38 49 48 45 44 222 213 216 209 211 203 206 200 69 69 69 69 110 104 128 120 106 105 107 107 575 563 566 556 492 482 484 472 1939 1914 1983 1924 4898 4898 5140 4975

*1+ *2+ *3+ *4+ 25 25 25 25 20 20 20 20 20 20 20 20 528 527 528 527 407 407 408 407 58 58 57 56 614 613 615 613 340 340 340 340 29 29 29 29 31 31 31 31 128 125 127 125 119 117 119 117 63 63 63 63 56 53 67 63 97 97 98 97 428 424 427 423 354 350 352 347 1790 1785 1810 1795 4513 4513 4705 4561

Table 1: Number of Gate Evaluations in Faulty Circuit (1000's)

7 Conclusion

Sequential circuit fault simulator performance can be improved by temporarily removing inactive faults from the fault list. Knowledge of the good circuit state can be used locally to identify inactive faults. The Star-Algorithm provides global information about inactive faults, based on the fault-free circuit state, and further reduces the faulty circuit event count. For the largest circuits, improvements in execution time were also obtained, despite the computation overhead. The best heuristic for selecting a circuit line on which to backtrace the Star-Algorithm star values is implementation-dependent; for the PROOFS fault simulator, selection of the most controllable input gave the best results.

References

[1] E. G. Ulrich and T. Baker, \The Concurrent Simulation of Nearly Identical Digital Networks," Proc. 10th Design Automation Workshop, Vol. 6, June 1973, pp. 145-150. [2] P. Goel, H. Lichaa, T. E. Rosser, T. J. Stroh, and E. B. Eichelberger, \LSSD Fault Simulation Using Conjunctive Combinational and Sequential Methods," Proc. Intn'l Test Conf., November 1980, pp. 371-376. [3] D. B. Armstrong, \A Deductive Method for Simulating Faults in Logic Circuits," IEEE Trans. Comput., Vol. C21, No. 5, May 1972, pp. 464-471. [4] T. M. Niermann, W. -T. Cheng, and J. H. Patel, \PROOFS: A Fast, Memory Ecient Sequential Circuit Fault Simulator," Proc. 27th Design Automation Conf., June 1990, pp. 535-540. [5] W. -T. Cheng and M. -L. Yu, \Dierential Fault Simulation - A Fast Method Using Minimal Memory," Proc. 26th Design Automation Conf., June 1989, pp. 424-428. [6] S. Seshu, \On An Improved Diagnosis Program," IEEE Trans. Electron. Comput., Vol. EC-14, February 1965, pp. 76-79.

[7] S. B. Akers, B. Krishnamurthy, S. Park, and A. Swaminathan, \Why is Less Information From Logic Simulation More Useful in Fault Simulation?" Proc. Intn'l Test Conf., September 1990, pp. 786-800. [8] F. Brglez, D. Bryan, and K. Kozminski, \Combinational Pro les of Sequential Benchmark Circuits," Intn'l Symposium of Circuits & Systems, May 1989, pp. 1929-1934. [9] W. -T. Cheng and S. Davidson, \Sequential Circuit Test Generator (STG) Benchmark Results," Intn'l Symposium of Circuits & Systems, May 1989, pp. 1938-1941. Circuit s298 s344 s349 s382 s400 s420 s444 s526 s641 s713 s820 s832 s953 s1238 s1423 s1488 s1494 s5378 s35932

0 1.9 1.3 1.3 25.2 20.0 4.2 31.1 23.5 2.9 3.1 10.7 10.2 3.2 9.1 6.2 22.5 19.5 84.6 382

1 1.9 1.4 1.4 29.5 21.7 3.9 32.8 21.5 2.6 2.7 9.3 8.9 3.1 7.9 5.8 20.5 17.7 76.5 342

1,2 1.6 1.2 1.2 23.2 17.4 3.2 27.7 16.7 2.2 2.2 7.2 6.9 3.0 6.4 5.8 18.1 15.3 73.5 330

*1 1.8 1.4 1.5 28.6 22.0 3.6 31.3 22.1 2.8 2.9 11.0 10.3 3.2 8.2 5.8 23.3 20.3 77.5 314

*1+ 1.7 1.3 1.4 27.3 19.9 3.2 29.6 17.8 2.4 2.5 8.4 7.8 3.1 6.9 5.6 19.6 16.8 74.7 295

Table 2: PROOFS Execution Time (sec)