Microcontroller based precision variable-phase phase-shifter

Microcontroller based precision variable-phase phase-shifter K. Sudhakar Rao, V. Jagadeesh Kumar and P. Sankaran Department of Electrical Engineering, Indian Institute of Technology, Madras 600 036, India. Abstract A n analog

digital feedback cornpensofion technique employi~igai1 active-RC uII-pass filter is described for obtainbig a freqirency mid amplihide independent, dry(-ftee phase-shift for siniisoidal signals. Wliile the analog feedback for realising the active-R is of conrwrtional fype, flie digital feedback for controlling C is intpleniented with a rnodijied successive approximatio~i(SA) technique. The irnpfemc~ttafior~ of Ilie SA schctne employing discrete digital ICs as well as a nricrocontroller is descnbed. A prorofype built works well over a frequency range of 20112 IO 50 kHz and has apliose s!abiIifyof rtO.29 ail d

1. Introduction There arises a number of situations wherein two sinusoidal signals with a precisely known phase-displacement between them is required. In early years, special polyphase alternators or wound rotor phase-shifters [I] were employed for this purpose. Later, phase-shifters employing passive and active circuits were proposed [2-41. The problems associated with these phase-shifteis are: 0 The phase shift varies with variation in the frequency of the input. 0 T h e phase shift changes when the amplitude of the input changes. 0 T h e amplitude of the phase-shifted sinusoid is not stablc over rhe required frequency range. Several schemes have been proposed for over -coming one or more of the above problems 15-81. In all such schemes, the phase-shift obtained at the output is still dependent on passive component values and hence, inaccuracies exist due to component tolerances and rlrirt in component values due to ageing. We now propose a dual feedback method for realizing a precision phase-shifter. The phase-angle obtained depends only on the ratio of two dc voltages. Deriving these voltages from a single high stability source, a high degree of accuracy can be obtained for thr phase.

2. The feedback-compensated

phaseshifter scheme

The block diagram shown in Fig. 1 illustratcs the proposed feedhack-compennated phasc-shifting scheme employing 3 first-order, ac[rve-RC, single opamp, groundi-d-R, a l l - p , ~filter. The phase-

vi

Fig. 1:Block diagram of the phase-shifter displacement introduced between the output vo of the all-pass filter and its input vi is given by (81 p = K -2t a n - l o ~ ~ ( 1) where w is the frequency of operation and R and C are the values of the resistance and capcitancc determining the pole-zero location of the all-pass filter. It can be concluded from the above equation that a stable ‘p would be obtained over a wide frequcny range, if the product wRC is maintained constant by varying both R and C as w varies. This necessitates a dual feedback scheme. Such a scheme is illustrated by the block diagram of Fig. 1. Here p is first sensed by a suitably modfied Phase Sensitive Detector (PSD)[9]. Deviation in p, if any from the set value, is detected and fed back to control R and C in such a way that the deviation reduces to zero. The scheme was implemented with analog and digital ICs. The analog portion is detailed in the circuh of Fig. 2. Variation in R is obtained by a FET operating as a Voltage Controlled Resistor (VCR), with additional opamps for expanding the VCRs linear working range(l01. The resistance R between the drain terminal of the FET and the ground G in Fig. 2 would be

R = where VdG is the drain-to-ground voltage, VdS the drain-to-source voltage, the drain-to-source current, Ids the drain to source resistance of FET, Rds = (1 R,/R,) , and a By making a small, K can be made several times Rds. At the same time, VdS would be a small Lraction of VdG This ensures that even with an

-

306 0-8186-7085-1/95 $04.00 0 1995 IEEE

Fig. 2. Analog section o f the phase-shifter.

applied ac voltage of appreciable magnitude, the FET works in the linear region. To increase the stability and decrease steady state errors, a proportional integral (PI) configuration is employed for the inner feedback loop. The integrator introduces a dominant pole in the feedback, ensuring stability. Larger the time constant, better is the stability of the analog closed loop. The integrator time constant also rues the time taken for the closed loop vo stabilize. Smaller the time constant, faster will the closed loop stabilize. As a compromise between these two conflicting requirements, an optimum value is chosen for the integrator time constant.

3. Principle of operation of the analog feedback In Fig. 2 the sub-block B is a scaler providing as output, a square wave of amplitude fVsand shifted in time by 7 with respect to the square wave of the input v,. With T being the period of the input, the PSD output is given by (10 1

vpsu=

(I

'-

4r -)

T

vs

where; 7

=-f-T. 360

(3)

VPsD is compared with a dc voltage Vr and the difference, if any, is fed back to control the RC product value;. The feedback loop stabilizes for 'PSD

=

(4

- r'

From equations (2) (3) and

(4, we get

307

p = (1

Vr + -)W.

vs

(5

Equation ( 5 ) indicates that the phase displacement between the input and output of the all-pass fdter is independent of the R-C values but depends just on two dc voltages, namely, V, and V..By deriving these voltages from a single source, high stability in p can be obtained. For a given cp at a certain U , the required R may turn out to be outside the range of the VCR with a particular value of C. In that case, the inner feedback loop will go into saturation. If such a condition arises, then the C-value should be changed to bring in the needed R value inside the working range of the VCR. As the inner feedback loop for R variation is a PI feedback scheme that continuously compensates for possible variations in the input as well as small drifts in the component lalues, it would be more than adequate even if the variation in capacitance is carried out in discrete steps. This is effected by choosing a proper combination out of a bank of capacitors, by a Digital Control Logic Unit (DCLU). For the FET to operate as a linear VCR, the gate voltage V, should be between -6 V ( V ) and zero (V+). If the integrator output is greater than V + or less than V-, a new capacitor value has to be selected by the DCLU. These two conditions a r e indicated t o t h e D C L U by a window comparator-cum-level shifter(F in Fig 2). The selection of capacitance by the DCLU is explained in the following section.

4 Capacitance selection logic To cover the audio frequency range arid the required range of phase-shift, a minimum of 200 steps are required in the capacitance values. Hence, the pole-zero fixing capacitancc C is constituted by a bank made up of 8 individual capacitances CO to C, and controlled digitally through analog switches SWO to SW7, as shown in Fig 2. By closing (switching it ON) a particular switch, say SW,, the corresponding capacitance value C, is added to make the C, that is connected to the all-pass filtcr. With eight switches, a total of 255 possible binary combinations (value zero is not utilized) uf the eight individual capacitors IS achieved I f this selection is effected by the usual incrementing and decrement ing technique, trawxsing of the entire 255 combinations will require as many steps The settling time of the digital feedback circuit will be consequently large. To reduce thc settling time, the set of eight capacitors arc controlled by employing a modificd Successive Approximation (SA) technique. The methoJ reduces the number of steps needed to select dny rcquircd capacitance combination, 10 less than or equal to eight Every time the inner analog loop goes out of its linear working range, the SA logic comes into operation, selects an appropriate capacitance combination and brings the inner feedback loop back into its linear opeiatirig range.

5 The modified successive approximation logic As in a Successive Approximation Register (EAR) of the corresponding analog-to-digital converter, switches SWo to SW, in Fig. 2 are kept in the OFF condition at start. The switch SW7 alone is closed. This brings capacitor C7 into the circuit (C = C7). After allowing a specified time for the inner loop to stabilize, its condition is tcsted by sensing the output of the window comparator. If V + of the window compararor is actite, it indicates that the set capacitor C7 is more than that required tiy the inner loop. SW7 is then switched OFF and sw6 switched ON, bringing c6 into the circuit (C = C6).If the V' output of the window comparator is active, SW, is left in the ON condition and SW, is C,). also switched ON (C = C7 This process is continued till both V + and \'- are at logic zero (inactive slatc 1, indicating t h ~ tthe inner loop has stabilized and that the required phase-shiftcd output is available at vui. Once V' and V go to logical 'rero' condition, thc SA procedure is halted. Hence, unlike the conventional SAR, the numbcr of steps will not be always eight. Depending on !he capacitance value to be selected, the number of steps will vary and will be less than or equal to eight. For exarnple, if Cpelection itself brings the inner feedback loop

-

308

4%

e

(011

Fig. 3: Next state diagrams (a) Conventional SA technique (b) modified SA technique. into stable operation, the SA stops with just one step. If due to some reason, the inner loop does not pull into its lincv working range for any of the possible 255 combinations of the capacitance values, i.e., at the end of controlling of switch SW,, the SA logic starts all over again. The SA procedure resumes also when the inner feedback loop pulls out of its working range after achieving stabilization. The difference between the logic of the SAR of ADCs and that of the modified SA technique applied to the capacitor selection is clearly illustrated by the 'next state' diagrams shown in Fig. 3. For the s.&e of clarity, the state diagrams are compared for a 3-bit ADC and a 3-bit modified SA logic. The proposed SA technique can either be implemented with hardwired logic or using a microcontroller and associated software. The former method is first illustrated in the following section.

6 Implementation of SA by

hardwired logic

The SA technique can be implemented using discrete digital components like gates and flip-flops is shown in the circuit of Fig. 4, wherein, rhe various components and their interconnection details are given. The circuit contains eight D flip-flops (FF7 - FFO) cascaded together and connected to a 12-bit ring counter realizing Ihe SAR. The outputs U1 to Q8 of the ring counter are in turn connected to the clock inputs of Ihe

Fig. 4. hludilied Successive Aapproximation by discrete hardware. flip-flops FF7 to FFO respectively. A clock generator with additional control circuitry for restarting, realized with another D flip-flop FF8 and NAND and XOR gates, drives the ring counter. The inputs to the hardwired DCLU are the outputs of the window comparator V+ and V-. The V+ signal of the window comparator is given after an inversion to the D-inputs of all the flipflops. The ’set’inputs of the flip-flops FF6 to FFU and the ’reset’ input of FF7 are all tied together and connected to an appropriate logical combination of the V signal of the window-comparator and the reset logic of the SAR. After the circuit resets, the flipflop FF7 (which corresponds to the MSB of the 8-bit number that controls the capacitor C,) is set at logic ’one,’ closing SW,. The other flipflops FF6 - FFO are reset to logic ’zero’ so that, switches sw, to Sw6 are kept in the OFF condition. Thus the output of t h e flipflops, which is an 8-bit binary data-1000 0000, selects C7 from the capacitor bank. The analog feedback circuit now tries to stabilize by varying the resistance of the VCR for the selected capacitance. The next clock cycle increments the ring counter and enables the clock of FF7. If the inte rator output is greater than zero at that instant, V 4 would be active at logic ’one’, forcing the D-inputs 10 the flip-flops FFO to FF7 to logic “zero”; a “zero” would be latched at the output of FF7. As the clock to the flipflop FF7 and the “set” input of FF6 flipflop are tied togethcr, FF6 will be set to “one” at the end of the first clock cycle, closing SW6. The &bit data now becomes 0100 oo00. The capacitance C will then become

equal to c6. On the other hand, if the integrator output is less than 6 V, then V- will be at logical ’one’ and V+ will be at logical ‘zero’ and hence, all the D-inputs of FFO to FF7 will continue to be at logical ’one’. A ’one’ will be latched at the output of FF7, and FF6 will be set to ’one’ as before. The 8-bit data then will be 1100 0000. Hence both C,and C, will be switched in to make the C. The sequence of operations are repeated till both V+ and V* are at logic ‘zero’. Once such a condition is obtained, the clock input to the ring counter is disabled and the SA procedure halts, indicating the proper working of the feedback loop(s). If for any reason, the above condition is not obtained even after the clock to FFO k given (after eight clock periods), then the succeeding clock resets the SAR and the whole process is repeated. Due to change in any of the input conditions, namely, phase value set (change in Vr),applied frequency, resistance of VCR or the capacitance, the inner loop may go out of its linear working range. Under such a condition, V+ or V- will become active and hence the SA process would be resumed. The control circuitry for resetting, restarting and resuming the SA has been realized by applying the expression RST = [(M‘? N), (M N)”+I] 09 , where, M = V+. N = V-, n = nth clock state, and Q9 is the 9th bit of the ring counter. The required phase was set by a ten-turn helical potentiometer, Though the scheme works well, the absence of a ’user-interface’ restricts its usefulness. Additional

e*

309

-

~

facility is needed to annunciate the set phase value. The addition of an user-friendly interface would enhance the applicability of the phase-shifter. With this in mind, a microcontroller based circuit has been developed. Apart from providing the enhanced user interface, the same microcontroller is also made to switch in the required capacitance by the SA technique. The operation of the microcontroller basecd phase-shifter is described in the following section.

7 Modified SA implementation with a Microcontroller The block diagram of the microcontroller set-up developed for implementing the user-friendly interface and SA procedure is shown in Fig. 5. The heart of the scheme is an INTEL, 8749 microcontroller, which controls through appropriate interface circuits, a four-digit seven segment display, a 12-bit multiplying type digital-to-analog converter (DAC) and the capacitance bank of Fig. 2. The output of the DAC is connected to the input V , ofthe summer of the analog part of the phase-shifter. While the seven-segment display shows the sct phase-displacement, the DAC is employed to generate the V,. The microcontroller writes a proportional 12-bit binary number on thc DAC port for this purpose. Apart from the V + and Vsignals from the analog feedback loop, the states of the three switches SI,S, and S3 are given as input signals to the microcontroller. The microconiroller is programmed to work in two different modes, namely, DCLU and user interface. The necessary program for controlling the microcontroller, written in assembly language, is translated into machine code through a cross assembler on the PC environment. The machine c o d e is then permanently burnt into the eprom of the 8749 The program sequence is illustrated in flowchart form in Fig. 6a and 6b for the two modes of operation. After power-on-reset, the microconiroller initializes the various ports, sets the phase displacement to 90.00 and writes this value on the display unit. After loading an appropriate 1Zbit binary value into the DAC, it enters the DCLU mode. 7.1 DCLU mode of operation In t h e DCLU mode, the microcontroller continuously senses the V + and V’ signals. If any one of these signals become active, indicating that the capacitance selection i\ to be modified, the microcontroller branches to the program that implements the SA proccdure. The SA method and selection of the proper capacitance is similar to that of the hardwired logic but for the difference that the logic is now implemented through ’stored program’ logic. The microcontroller returns to the DCLU mode after executing the SA subroutine.

310

Fig. 5 Block digram of the microcontroller set-up In the DCLU mode, the controller always polls the signals V + and V-. At any given instant, closing of SI (ON) interrupts the controller, bringing DCLU mode to a temporary halt a n d the microcontroller then enters the user interface mode. 7 2 User interface mode The user interface mode facilitates the set phase value to be changed by the user. Once the microcontroller is interrupted for this purpose, the user is allowed to alter the value of the phase shift required. To this end, the four BCD numbers that represent the phase value are modified, one digit at a time. The most significant digit MSD (‘‘tens’’position in the digit structure DID2 . D3D4) is fist selected and annunciated by blinlung it at a rate of 0.5 Hz. The selected digit D, can now be incremented by activating switch S2 or decremented using S3. Enabling SI one more time shifts the position of the selected digit down by one. Now, digit D, is selected and the same is indicated to the user by blinking it at 0.5 Hz,with D, continuously lit. The process is repeated for all the four digits. While the tens and units positions are incremented or decremented by unit step, the decimal part of the phase value (last two digits, viz., D, and D,J are together incremented and decremented with a step size of 0.05. Alter the last digit is set (ie. SI activated for the fourth time), the microcontroller converts the set phase-shift to an equivalent voltage and loads the DAC with a suitable binary value to generate the computed V,. It then returns to the DCLU mode to select the proper value of capacitance from the capacitance bank. While the jump from the DCLU mode to the user i n t e r f a c e mode is through t h e asynchronoushardware interrupt enabled by SI,rhe shifting of the digits inside the user interface program and the return to the DCLU mode is achieved by polling SI. This procedure is implemented by controlling 1 he status of the interrupt in the microcontroller by

Q Reset

Blink D1

Compule DACb and loa to 74 Ls 373

RO = R1

-

80H

Write RO to PORT2

V- c -G

+I

IRO = RO-R1

-

V + >(I

-

Fig. 6a Flowchart DCLU mode

software. In the DCLU mode, the hardware interrupt is enabled and the interrupt vector is initialized to point the user interface segment of the program. As soon as an interrupt occurs and the microcontroller jumps to the user interface program segment, the interrupt is disabled and the INT pin is polled by software. After all the digits of the phase are set, the hardware interrupt is once again enabled and the microcontroller instructed to re-enter the DCLU mode, thus enabling the user to interrupt the DCLU mode again, if required. 7.3 Generation of reference voltage After the user sets the required phase-shift on the display unit, the microcontroller, before rcturning to the DCLU mode, calculates the voltage to be given to the summer as

The input to the DAC, a 12-bit binary data to generate V, is obtained by converting the BCD number resulting from equation (6) into equivalent binary value. The microcontroller is programmed to make this BCD-to-binary conversion in such a way that the LSB corresponds to 00.05. To represent the range from 00.00 to 90.00 in steps of 00.05, 1800 counts are needed. Hence the binary number DAC, to be loaded into the DAC to generate V, is Vr

DACb =

V,X

1800

(7)

-

Fig. 6b Flow chart User-interface mode

It should be noted here that when V, is zero, the phase obtained is 90.00 and is 00.00 when V, = V, Hence the reference pin of the DAC is supplied with a voltage Vr of [V, x (2047/1800)]V.

8 Salient features of the microcontroller scheme. In the microcontroller scheme, the user has in his control, three quantities to vary. The three possibilities are: (i). The phase shift desired can be changed at any frequency. (ii) For a given phase shift, the user can vary the frequency of operation. (iii) The magnitude of the input voltage may then be changed. If the user changes the frequency of the input signal, instability in the inner loop, if any, is reflected at the output of the window comparator. Depending o n t h e s t a t u s of t h e window comparator, the microcontroller performs the successive approximation procedure to select a new capacitance combination t o get a constant phase-shift. The effect of variations of the input voltage on the phase-shift obtained is minimal. The feedback scheme takes care of these variations in the FET performance due to input voltage variations.

9 Experimental results and

conclusions

The efficacy of the scheme is verified by building a prototype unit. The prototype unit w o r k well over a frequency range of 20 Hz to 50 kHz The oscillogram of Fig. 7 illustrates the working of the analog and digital feedback loops. The waveforms were taken on a Tektronix 7623A storage oscilloscope. Fig. 7 shows the capacitor seicction as well as the control for the VCR at 150 Hz and 90 degree phase shift. The switching sequence of the first 4 Most Significant Bits (MSB) for the capacitance selection is shoain. With MSB at logic 'one' condition, and the circuit switches ON MSB-1 when Vc crosses V . Still the outputs of the window comparator are not at logic 'zero'. With MSB-2 at 'one', the circuit gcts stabilized, bringing C7, C, and C5 into the feedback loop. Table 1 shows a comparison of the phase-displaccments obtained on the prototype with those measured using a PMG624 Phillips 5u) MHz timer-counter. The readings are givun for various phase-shifts ranging from 90" to 5" lag at different frequencies. The basic stability (4 the prototype is f(iunc1to be 0.2" The actual phdse shift obtincd at [he output v0 differs slightly from that of the value set by thc user due to 0 steady state e r r o r i n the feedback compensation scheme. inaccuracies, asymnirtry and drift in +Vs and 4;. inaccuracy and non-linearity of the DAC employed for reference voltage generation. offset and slew rate limitations of the opamps and comparators. The scheme ar, such provides phase displacement in the I1 quadrant only ( 90" to 180" ). Addition of a simple inverter would provide phase displacement in the I\' quadrant. If phase displacement in either I or 111 quadrant is required, the same may be achieved b y simply making V, a negative voltage. Phase-shifters of this type find application in the field of component measuremcnl and calibration of Instruments

Sensitivity : X-axis To trace OtLs

- ls/cm -

10V/cm 5 Vlcm

Fig. 7 Oscillqrslm of V,, V , V + and 4 MSBits uf capacitance selection logic Tablel: Characteristics of the prototype. Phase-shift (de rees) (fa,, 1

References Wound rulor 3-phme phiibe bhiflrr. Typc IODPI. Iiubner Gicsscn, Bcrlin. Germany. 1970. F. Alton Everest. "Phnse shifting uplo 3GO degrees", Electronics, vol. 14, p. 46, Nov.1941. W. Gosling. "Sysleni which produces cunslitnl p1i:i.c~shirt of w sinusoid irrespecliee of frequency". Eleclrun. LclL, vol. 7, pp. 116 -147. Apr. 1966. G . Dehmcl and D.l.ukoschus, "I*Jiii\e sltiflcr wiltt high amplilude accurncy", Eleclrun. lcll.. v0I IO. pp 22 23. Jan 1972.

3 12

5.

Phase-shift degrees) measured by PM6624$imer counter at a frequency of 100Hz 1 kHz 1 10kHz

I

M. Madihian, K Waianabe, and T.Yamamoto. "A frequency-independenl phase shlNcr", J. Phys E: ScL Instrum., vol. 12, pp 1031-1032,1979.

E. W. Tay and V. G. K Murcr. "Unity-gain frequency-independent quadrature phase shifter". Electron. LelL. vol. 20, pp. 431432. May 1984. 7. J . Auslin and I. R Forest, "A precise diglhl phase s h i h r using a phnse-locked loop", Electron. LelL, vol. 14, pp. 254- 255. Apr.1978. 8. C. A. Karybakas and G. A. Micholitsis, "A circuit l o r conslnnl phusc shift using n narrow pulse duly cycle ell-pnss filler", IEEE Trnns. InslrunL Mens.. vol. IM-3), pp. 594-598. Aug. 1990. V. K. L. Smith, "The ublquilous phnse sensitive detector. npplicolions and principle of operolion", Wireless world, pp. 367-370, Aug. 1972. 6.

lo' ~1~~~~~

~~,"nu,4~~'r~,',u',",t~~~~

I N N Circuits sysl.. vol. CAS-30, pp. 770.772, OCI 1980.