Modeling of the Substrate Coupling Path for Direct Power Injection in Integrated Circuits Ali Alaeldine∗† , Richard Perdriau∗ , Mohamed Ramdani∗ , Etienne Sicard¶ , Ali Massoud Haidark and M’hamed Drissi† ∗ ESEO-LATTIS
- 4, rue Merlet-de-la-Boulaye - BP 30926 - 49009 Angers Cedex 01 - France (e-mail :
[email protected]) - INSA de Rennes - 20, avenue des Buttes de Coësmes - 35043 Rennes Cedex - France k BAU - faculty of engineering - PO Box 11-5020, Beirut - Lebanon ¶ LATTIS - INSA de Toulouse - 135, avenue de Rangueil - 31077 Toulouse Cedex 04 - France
† IETR
Abstract—This paper presents a substrate coupling path model for the direct power injection (DPI) of EMI disturbances into the substrate of an integrated circuit (IC). This modeling is achieved on a 0.18 µm test chip composed of several functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate), and takes into account these different strategies. The comparison between simulation results and related measurements demonstrates that, once combined with the complete model of the injection set-up itself, these models are helpful to choose the best protection strategy against electromagnetic disturbances.
I. I NTRODUCTION For many years, integrated circuits (ICs), and digital blocks in particular, have been the source of ever increasing electromagnetic interference (EMI), due to higher clock frequencies and data rates as well as decreased node capacitances. In parallel, their immunity to EMI has decreased at the same pace, due to a steady reduction in power supply voltage and, consequently, noise margin. Therefore, the characterization and modeling of their susceptibility is a topical demand. For that purpose, several measurement methods have been developed and standardized by the IEC, including direct power injection (DPI) [1] and bulk current injection (BCI) [2]. Both methods reproduce operating conditions, however, DPI is easier to set up and, therefore, was chosen for this study. In particular, substrate noise generated in an IC by either internal logic or external sources can dramatically disturb the operation of other analog and digital blocks, due to the low resistivity of the substrate in modern ICs [3]. Various solutions [4] have been pointed out in order to enhance substrate shielding against electromagnetic interference. Moreover, previous authors [5] have already mentioned the use of substrate injection to characterize the behavior of an IC towards EMI. Later, this experiment was standardized using DPI test benches [6], and made it possible to identify the efficiency of substrate shielding techniques through measurements. However, these "a posteriori" experiments require the fabrication of a test chip. Conversely, the use of simulation for the prediction of immunity to substrate injection would avoid this fabrication. Simulation models for DPI tests on ICs have already been developed [7], but only for Vdd injection. In order to establish accurate simulation models of substrate DPI, modeling substrate coupling paths in ICs is a required additional task.
Therefore, this paper aims at introducing suitable simulation models for different EMI protection strategies in ICs, with comparisons between simulations and measurements. For that purpose, a special test chip (CESAME) [8] will be used. The paper is organized as follows. First of all, the internal structure of the CESAME test chip is introduced in Sect. II. Then, Sect. III presents the DPI measurement set-up used in this study, along with its simulation model. The different substrate models for the internal cores of the IC are described in Sect. IV. Finally, Sect. V provides a comparison between measurements and simulations, along with comparisons among the efficiencies of different EMI protection strategies. II. T EST CHIP A. Structure The integrated circuit used in this study (CESAME) was designed and fabricated by ST-Microelectronics in 0.18 µm CMOS technology (1.8 V supply voltage), and was initially intended for the validation of low-emission design techniques [6] [8]. It consists of six logic cores which are identical from a functional point of view and are located on the same die, but differ only by their protection strategies. All these cores are based on D flip-flops, a clock tree and standard gates, and are intended to reflect the activity of a typical logic core [8]. Each core includes 240 identical synchronous base cells, and each base cell consists of 400 transistors (5 D-flip-flops, 25 NAND gates and 4 buffers). This IC is mounted on a custom printed circuit board (PCB), called ALI, which is displayed in Fig. 1 (left). For the sake of simplicity, only 3 different cores (NORM, ISO and RC) out of 6 are used, which are highlighted in dotted boxes in the right half of the same figure. 4 cores (NORM, RC, NOR and GRID) are built in the global substrate of the IC, while the other ones (ISO and ISV) are built in a local isolated substrate. a) NORM core: The NORM core is built in the global substrate of the IC. The only EMI protection strategy used in this core consists of two small 1.7 Ω series resistors, one on each power supply rail. These resistors, along with the metal and MOS capacitances of the logic core, build up a RC filter, with a high cutoff frequency (about 200 MHz). The structure of this core is depicted in Fig.3 (left).
the data output overshooting 20 % of its nominal voltage, or its jitter overshooting 10 % of the period. The transmitted power PT rans dissipated into the substrate of the circuit under test can be expressed from the measured incident power PInc : 2
PT rans = (1 − |S11 | ) PInc
Fig. 1. ALI test board and CESAME test chip with the 3 cores under test (NORM, ISO and RC) in dotted boxes
b) ISO core: The ISO core uses a different EMI protection strategy. It is embedded in its own local substrate, isolated from the rest of the chip thanks to a triple-well technique (Fig.4, left). This strategy has already been pointed out as very interesting for EMI shielding [4]. c) RC core: In the RC core, built in the global substrate like the NORM core, an additional 1-nF integrated decoupling capacitor is inserted between both supply rails (Fig.5, right). This distributed on-chip capacitor is made from several poly1/poly2 capacitors, and increases the area of the RC core by 40 % compared with the NORM core. By lowering the cutoff frequency of the RC filter (about 40 MHz), this technique allows the reduction of the power distribution noise arising from multiple drivers switching simultaneously [9]. B. Modeling and measurement conditions The different cores of the CESAME chip can be activated separately. In order to simplify modeling, only one core will be activated for each measurement and will be subject to power injection. Therefore, the DPI injection set-up used in this study (and described in the following section) can be considered the only source of the noise dissipated into the substrate of the logic core under measurement. III. DPI SET- UP A. DPI measurement method The DPI injection method used in this paper has already been introduced in a previous paper [6] for the same setup. Conducted-mode interference is injected through a probe connected to the Vss pin of each logic core under test through a 1 nF capacitor. This probe is fed by a 10 W power amplifier through a directional coupler, allowing the measurement of incident and reflected powers through a dual-channel power meter. However, only the incident power will be used in this study for the representation of the measured and simulated immunity plots of each core. The data output of the circuit under test is connected to an oscilloscope (adapted to 1 MΩ) through a 1 MΩ passive probe, which makes possible to observe a malfunction of the circuit during the experiment. This malfunction is characterized by the immunity criterion described in [6], namely, the ripple of
(1)
where S11 is the reflection factor and PInc the incident power injected into the system under test. By replacing the reflection factor by its expression, Eq. 2 is obtained : à ¯ ¯ ! ¯ ZDU T − Z0 ¯2 ¯ PT rans = 1 − ¯¯ PInc (2) ZDU T + Z0 ¯ in which ZDU T is the impedance of the device under test and Z0 the characteristic impedance of the sine-wave generator (50 Ω). By separating the real and imaginary parts of ZDU T , the exact expression of the transmitted power can be obtained : PT rans =
4 Z0 Re(ZDU T ) |ZDU T + Z0 |
2
PInc
(3)
The expression in Eq. 3 is well suited to the calculation of PT rans from measurements, owing to the use of power meters in DPI experiments. However, it is unusable for DPI electrical modeling and simulation, since power generators are not available in common circuit simulators. A convenient solution consists in using a RF voltage source, and expressing the transmitted power as a function of source voltage instead of injected power(Eq. 4): PT rans =
4 Z0 2
|ZDU T + Z0 |
VInc 2
(4)
These expressions will be used in Sect. V in order to build up immunity plots (in dBm) from electrical simulation results (in V). B. Modeling of the DPI set-up In order to predict the immunity of the cores, a comprehensive model must now be developed for the injection set-up and the device under test (PCB and IC). The model used for the injection set-up itself is a generic one suggested in [7], depending on the length of the directional coupler and its associated cables. The latter are represented by a transmission line adapted to 50 Ω, with a delay time Td given by Eq.5: l 76.08 · 10−2 = = 2538 · 10−12 s (5) c 3 · 108 in which l is the total length of the directional coupler and its cables, and c the speed of light. Likewise, the models of the PCB, the IC and the injection probe have already been introduced in [8] and [7], respectively, and are being re-used in this study. However, in this case, injection is performed on the Vss pins of the IC instead of the Vdd pins. Therefore, the 1.2 Ω resistor, used for VDE conducted emission measurements [10] on the ALI board, is Td =
Fig. 2.
Complete electrical model of the DPI experiment (without any substrate model)
modeled accurately with its parasitic inductance. The global model of the DPI experiment is depicted in Fig. 2. However, this model still does not take into account the substrate injection path itself.
Device Repi−N ORM RGRID RRC RN OR
Value 30 Ω 30 Ω 30 Ω 30 Ω
Device Cpcb LGRID LRC LN OR
Value 500 fF 3.57 nH 3.67 nH 3.67 nH
TABLE I D EVICE VALUES FOR THE SUBSTRATE MODEL OF THE NORM
CORE
IV. S UBSTRATE MODELING FOR THE 3 CORES UNDER TEST A. NORM core In the case of the NORM core, power is injected straight into its substrate (which is indeed the global substrate of the circuit) through the Vss pin. Fig. 3 (left) depicts the architecture of an inverter of the NORM core. As can be seen, the global epitaxial substrate is modeled in the vertical direction by a resistance, designated by Repi−N ORM . Then, the substrate is coupled to the PCB ground through a capacitance (Cpcb ) representing the spacing between the chip and the PCB itself. It can be noted that the model of the bonding and package of the Vss pin of the NORM core is not represented here, but in the global model already presented in Fig. 2. However, it is also necessary to take into account the coupling paths to the PCB ground through the Vss rails of the 3 other cores (NOR, RC and GRID) built in the same substrate (the ISO and ISV cores, built in their own substrate, were neglected in this first-order approximation). Each rail is modeled by a series RL network representing the substrate resistance (same as the one of the PCB core) and the inductance of the package and the bonding of the corresponding IC pin. Therefore, the complete model of the substrate coupling path for the NORM core can be built (Fig. 3, right) ; the corresponding values of the equivalent passive devices of this model are shown in Tab. I. In order to perform the immunity simulation, the model of the NORM substrate is added to the model of the system under test already shown in Fig. 2. In order to speed up simulations, the actual transistor netlist of one base cell of the core is used,
while the other ones are replaced by their equivalent parallel RC model.
B. ISO core The ISO core bears a more complex model, with the addition of the NISO isolation layer between the local substrate of the core and the global substrate of the integrated circuit. Indeed, two coupling capacitances must be taken into account: the first one (Cpwell1 ) is located between the global P substrate and the NISO layer, while the second one (Cpwell2 ) is located between the NISO layer and the local P substrate of the ISO core, as can be seen in Fig. 4. Moreover, Rnwell models the actual resistance of the N-well which allows the buried NISO layer to be connected to the Vdd rail. Repi−ISO represents the equivalent resistance of the epitaxial substrate (analogous to the NORM core) ; however, its value is lower than the one of the NORM core, due to the reduced equivalent thickness of the substrate under the NISO layer. The rest of the model is identical to the NORM core, namely, the coupling path to the PCB ground through the Cpcb capacitance, and the Vss pins of the other cores built in the global substrate (NORM, RC, NOR and GRID). The complete model of the substrate of the ISO core is depicted in Fig. 4 (right), while the values of its equivalent devices are printed in Tab. II.
Fig. 3.
Structure of an inverter of the NORM core (left) and electrical model of the substrate of the NORM core (right)
Fig. 4.
Structure of an inverter of the ISO core (left) and electrical model of the substrate of the ISO core (right)
Fig. 5.
Structure of an inverter of the RC core (left) and electrical model of the substrate of the RC core (right)
Device Repi−ISO Cpwell1
Value 22 Ω 270 pF
Device Rnwell Cpwell2
Value 2Ω 348 pF
TABLE II D EVICE VALUES FOR THE SUBSTRATE MODEL OF THE ISO
CORE
C. RC core The RC core is almost identical to the NORM core, apart from the inclusion of a 1 nF on-chip decoupling capacitor located between both Vdd and Vss power supply rails. It is modeled and represented by the series RC network Cdecoup and Rdecoup . Moreover, another resistance (Rsub−RC ) is added to the vertical resistance (Rsub−RC ), and represents the sub-
strate resistance of the path starting from the Vdd input. Like in the NORM model, the coupling paths to the PCB ground through the Vss rails of the 3 other cores (NORM, NOR and GRID) built in the same substrate are taken into account. The complete model of the substrate of the ISO core is depicted in Fig. 5 (right), while the values of its equivalent devices are printed in Tab. III. Device Repi−RC Cdecoup
Value 30 Ω 1 nF
Device Rsub−RC Rdecoup
Value 34 Ω 1Ω
TABLE III D EVICE VALUES FOR THE SUBSTRATE MODEL OF THE RC CORE
V. R ESULTS
40
A. Comparison between simulations and measurements for each core 35
Injected power (dBm)
A first immunity simulation was performed from 10 MHz to 1 GHz for each core. This time-domain simulation is performed for each frequency step (10 MHz); as stated in Sect. III, a failure in the IC is characterized by the ripple of the output signal reaching 20 % of the logic "1" voltage level, or by the jitter of this output signal reaching 10 % of the period. Fig. 6, 7 and 8 depict the comparisons between experimental measurements and simulation results for the susceptibility of the NORM, ISO and RC cores, respectively.
Measurement Simulation
30
25
20 DPI into the substrate of the RC core: −Output signal susceptibility 15 0
100
200
300
400 500 600 Frequency (MHz)
700
800
900
1000
40 Measurement Simulation
Fig. 8. Susceptibility of the RC core : measurement (solid) and simulation (dotted)
Injected power (dBm)
35
30
25
20
15 DPI into the substrate of the NORM core: −Output signal susceptibility 10 0
100
200
300
400 500 600 Frequency (MHz)
700
800
900
1000
Fig. 6. Susceptibility of the NORM core : measurement (solid) and simulation (dotted)
It can be noted that all cores are immune to a 10-watt incident power below 60 MHz. Above this frequency, they are becoming more and more susceptible. Low- and high-immunity frequencies are almost identical between measurement and simulation results. Moreover, the simulation is generally "pessimistic", namely, the simulated immunity is lower than the measured one ; this is the most favorable case for immunity prediction. Conversely, in the 460-640 MHz frequency range, the difference is greater then 6 dBm with the simulation being more "optimistic". These discrepancies may be due to power losses [11] which haven’t been included so far in the simulation model and remain to be studied. B. Discussion and comparison among simulation results
40 Measurement Simulation
Another interesting result consists in comparing simulation results for the 3 cores on the same diagram (Fig. 9), in order to assess the relative efficiencies of the protection strategies and compare them with the ones obtained from measurements.
Injected power (dBm)
35
Previous studies [3] have pointed out the efficiency of reduction techniques for substrate noise. Moreover, measurements for the 3 cores under test have already been presented in [6] ; they demonstrated that the RC core is the most immune to DPI, followed by the ISO core and, finally, the NORM core. As far as simulations are concerned, it is important to notice that the hierarchy among the 3 cores is exactly identical. This result thus confirms the previous studies conducted on this topic.
30
25
20
15 DPI into the substrate of the ISO core: −Output signal susceptibility 10 0
100
200
300
400 500 600 Frequency (MHz)
VI. C ONCLUSION 700
800
900
1000
Fig. 7. Susceptibility of the ISO core : measurement (solid) and simulation (dotted)
In this paper, coupling paths for direct power injection into the substrate of an IC were identified and modeled for 3 different cores of the IC (plain, isolated substrate, integrated decoupling capacitor). These models were added to a comprehensive simulation model of a DPI set-up, making
R EFERENCES
40 Simulation: NORM core Simulation: ISO core Simualtion: RC core
Injected power (dBm)
35
30
25
20 DPI into the substrate of the three cores (NORM, ISO and RC): −Output signal susceptibility 15 0
100
200
300
400 500 600 Frequency (MHz)
700
800
900
1000
Fig. 9. Comparison among the simulated susceptibilities of the NORM, ISO and RC cores
it possible to perform immunity simulations. The classification obtained from simulations for these different protection strategies matches the one obtained from measurements, and demonstrates that the integrated decoupling capacitor seems to be the best EMI protection method against external sources of substrate noise. In order to improve the matching between simulations and measurements, power losses may be included into the simulation models. The characterization of the coupling path between the power supply rails and the IC output itself may be also useful to avoid the use of the IC netlist in simulations.
[1] IEC EMC Task Force. IEC62132-3 : Direct RF power injection to measure the immunity against conducted RF-disturbances of integrated circuits up to 1 GHz. Draft technical report, IEC, August 2001. [2] IEC EMC Task Force. IEC62132-2 : Immunity test to narrowband disturbances by bulk current injection (BCI), 10 kHz-400 MHz. Draft technical report, IEC, 2001. [3] S. Ardalan and M. Sachdev. An overview of substrate noise reduction techniques. In International Symposium on Quality Electronic Design (ISQED04), USA, pages 291–296, 2004. [4] R. Rossi, G. Torelli, and V. Liberali. Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICs. In ESSDERC, Portugal, September 2003. [5] T. Tsukagoshi, T. Kuriyama, H. Wabuka, and T. Watanabe. LSI immunity test by direct GND pin injection. In IEEE International Symposium on Electromagnetic Compatibility (EMC2003), USA, pages 248–251, August 2003. [6] A. Alaeldine, N. Lacrampe, J.L. Levant, R. Perdriau, M. Ramdani, F. Caignet, M. Bafleur, E. Sicard, and M. Drissi. Efficiency of embedded on-chip EMI protections to continuous harmonic and fast transient pulses with respect to substrate injection. In IEEE International Symposium on Electromagnetic Compatibility (EMC2007), Hawaii, USA, July 2007. [7] M. Ramdani, A. Alaeldine, and R. Perdriau. A direct power injection model for immunity prediction in integrated circuits. In EMC Europe, September 2006. [8] B. Vrignon, S. Ben Dhia, E. Lamoureux, and E. Sicard. Characterization and modeling of parasitic emission in deep submicron CMOS. IEEE Transactions on Electromagnetic Compatibility, 47(2):382–387, May 2005. [9] P. Chahal, R. Tummala, M. Allen, and M. Swaminathan. A novel integrated decoupling capacitor for MCM-L technology. IEEE Transactions on Components, Packaging and Manufacturing Technology, 21(2):184– 193, May 1998. [10] IEC EMC Task Force. IEC61967-4 : Integrated circuits, measurement of electromagnetic emissions, 150 kHz to 1 GHz - part 4: Measurement of conducted emissions - 1 Ω/150 Ω direct coupling method. Technical report, IEC, 2006. [11] A. Alaeldine, R. Perdriau, M. Ramdani, and V. Veeragandham. Electrical model for power losses in direct power injection. IET Science, Measurement and Technology, 1(5):284–289, September 2007.
