DESIGN METHODOLOGY OF MULTIPLE-VALUED LOGIC VOLTAGE-MODE STORAGE CIRCUITS I. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis, T. Stouraitis* Laboratory of Electrical and Electronic Materials Technology Dept. of Electrical and Computer Eng. Democritus University of Thrace 671 00 Xanthi, Greece,
[email protected] *VLSI Design Lab, Dept. of Electrical and Computer Eng. University of Patras, 26110, Patras, Greece
ABSTRACT A novel methodology designing for Multiple-Valued Logic voltage-mode storage circuits is introduced. Using the proposed inverter-based unit, uni-signal controlled pass gates and True Single-Phase Clocked Logic-based output units, efficient r-ary (where r is the radix) dynamic and pseudo-static latches can be designed. They exhibit regular, modular, and iterative structure, which means that the for Multiple-Valued Logic circuits are VLSI implementable. Also, These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode. Since we use only clock signal, additional contribution to low power dissipation of the derived circuits is been made. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.
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Comparing the quaternary pseudo-static produced by the proposed methodology with an existing circuit [11], it is concluded that the former circuit exhibits substantially-improved features.
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THE DESIGN METHODOLOGY
Applying the proposed methodology r-ary latches, where r is the radix, can be designed. Their general structures are shown in Fig. 1. They consist of three basic building blocks, namely the inverter-based unit (level-corrector), the uni-signal controlled pass gate, and the TSPCL-based output unit. The main features of these building blocks are presented in the next paragraphs. It should be noted that, both enhancement and depletion transistors are used [12].
INTRODUCTION
Multiple-Valued Logic (MVL) circuits have been attracting researchers in recent years, the reason arises from the fact that some critical features related to the reduction of the number of the interconnections and the increased information content per unit area [1-3]. Two kinds of MVL circuits based on MOS technology have been developed, namely the current-mode MVL circuits [4] and the voltage-mode MVL circuits [5-8, 10, 12]. In this paper, a methodology for designing MVL voltage-mode dynamic and pseudo-static latches is presented. Efficient new building blocks, namely, inverter-based unit (level-corrector), the uni-signal controlled pass gate, and the True Single-Phase Clocked Logic (TSPCL)-based output unit, for r-ary logic implementations, are introduced. Combining the first circuit with the TSPCL-based output unit or the uni-signal controlled pass gates, which are also introduced, an r-ary latch can be designed. As an application, the implementation of the above MVL latches in quaternary logic (r=4) is provided. The proposed MVL circuits are characterized by two threshold voltages for each type of MOS transistor and can function with only one control signal (usually a clock), i.e., its complementary form is not needed. Exploiting the latter useful feature, one can design MVL data paths similar to the True Single-Phase Clocked Logic (TSPCL) [9] approach of the binary logic, which avoids race condition problems. Also, the existence of TSPCL design style results into MVL circuits with low power consumption.
INVERTERBASED UNIT
x
TSPCL-BASED OUTPUT UNIT
(a)
z
clock
Uni-signal controlled pass gate x
INVERTER-BASED UNIT
clock (b)
z
Uni-signal controlled pass gate
Figure 1. The structure of MVL latches, (a) dynamic and (b) pseudo-static.
0-7803-4455-3/98/$10.00 (c) 1998 IEEE
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Inverter-based unit
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The inverter-based unit performs voltage level correction, i.e., it produces the exact logic level voltage, when the input voltage value has small difference from the precise voltage value of the associated logic level. For a given radix r, the proposed inverter-base unit (levelcorrector) has the structure shown in Fig. 2. It comprises two aary Logic Level-Correction Module (aLLCM), where 0
