Multiple logic functions from extended blockade region in a silicon quantum-dot transistor Youngmin Lee, Sejoon Lee, Hyunsik Im, and Toshiro Hiramoto Citation: Journal of Applied Physics 117, 064501 (2015); doi: 10.1063/1.4907799 View online: http://dx.doi.org/10.1063/1.4907799 View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/117/6?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Fabrication of a germanium quantum-dot single-electron transistor with large Coulomb-blockade oscillations at room temperature Appl. Phys. Lett. 85, 1532 (2004); 10.1063/1.1785870 Coulomb blockade in a silicon/silicon–germanium two-dimensional electron gas quantum dot Appl. Phys. Lett. 84, 4047 (2004); 10.1063/1.1751612 Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature Appl. Phys. Lett. 84, 3172 (2004); 10.1063/1.1710709 Fabrication and room-temperature characterization of a silicon self-assembled quantum-dot transistor Appl. Phys. Lett. 73, 3129 (1998); 10.1063/1.122695 Silicon single-electron quantum-dot transistor switch operating at room temperature Appl. Phys. Lett. 72, 1205 (1998); 10.1063/1.121014
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JOURNAL OF APPLIED PHYSICS 117, 064501 (2015)
Multiple logic functions from extended blockade region in a silicon quantum-dot transistor Youngmin Lee,1 Sejoon Lee,1,a) Hyunsik Im,1 and Toshiro Hiramoto2 1
Department of Semiconductor Science, Dongguk University-Seoul, Seoul 100-715, South Korea Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan
2
(Received 16 October 2014; accepted 28 January 2015; published online 9 February 2015) We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio 200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multiC 2015 functional one-transistor logic gate with AND, OR, NAND, and XOR functions. V AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4907799]
I. INTRODUCTION
The single electron transistor (SET) is one of the most promising device-schemes that can be utilized for future ultra large-scale-integration (ULSI) technology.1,2 Because of the unique features and the peculiar functionalities of the SET, the applications for the SET-based analog and digital circuits have become more attractive, particularly, for the realization of the post complementary metal-oxide-semiconductor (CMOS) technology. A fascinative advantage is the multi-functionality, arising from the quantum nature of the ultra small dot embedded in the single-electron device system. For instance, multiple logic functions in a chemically assembled Au SET3 and half-adder binary arithmetic functions in a Si SET4,5 are the typical examples that can move the SET closer to future ULSI technology. However, the circuits proposed above only operate at the cryogenic temperature below 10 K. For the practical application, the room temperature (RT)-operation of the SET is essential; accordingly, many research groups have tried to demonstrate the RT-operating SETs. Owing to recent advances in nanofabrication technologies, several types of RT-operating SETs have been demonstrated, particularly, on Si quantum-dot (QD) device systems,6–15 some of which showed not only clear Coulomb blockade oscillation (CBO) characteristics but also negative differential conductance (NDC) features in a unit device.7–13 Moreover, very recently, possible applications of the Si SET-based digital circuits have been proposed; for example, one-transistor (TR) XOR and XNOR logic gates,16–19 multi-valued logic circuits,20,21 and even half-adder circuits.4,5 Except for just few examples,18,19 however, the operation temperatures (TO) of those circuits are still far from RT (i.e., TO < 77 K). Furthermore, most of the circuits include multiple gates so as to perform the shift of CBO peaks, requiring for the logic application. The usage of multiple gates would inevitably modify the junction capacitances of the tunnel barriers and may change the a)
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charging energy in the QD. This could reduce the stability of the circuits; therefore, the self-controllability of the CBO/NDC peak shift is desired for both points of views in simplifying the circuit configuration and in improving the circuit stability. In this paper, we report on RT-demonstration of the multiple logic-functions using a single device of the Si SET, for which we only use two input terminals (i.e., gate and drain) without any extra junctions and/or additional electrodes. The device is prepared by our CMOS-compatible stateof-the-art Si nanowire-channel metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication techniques,8–12 and the demonstrations of the multiple logic-functions are achieved through utilizing the unique feature of the extended blockage characteristics in our device. The electrical characteristics and the logic functionalities of the fabricated device are examined and discussed. II. EXPERIMENTAL DETAILS
The Si SET is composed of an electron-beam-lithographically patterned [110] Si nanowire channel [Fig. 1(a)], where Si QDs are self-formed with multiple barriers through the volumetric undulation by isotropic-etching (NH4OH:H2O2:H2O ¼ 1:1:6) [Fig. 1(b)]. Since the as-fabricated Si nanowire-channel is narrower than 15 nm and is suspended from the buried oxide layer, the diameter of the completed Si nanowire would be shrunken down to 5 nm after further oxidation for creating the all-around gate-oxide.12 The gate stack is created with the gateall-around (GAA) structure by deposition of poly-crystalline nþ-Si. Thereafter, the nþ (1020 cm3) source/drain reservoirs are formed by Pþ ion implantation. Here, it should be noted that, during the aforementioned undulation process, the Si nanowire will show surface fluctuations along the nanowire direction [Fig. 1(c)] because chemical etching leads to volumetric squeezings at arbitrary positions. In our previous studies,8,12 the diameter of the completed Si nanowire-channel was confirmed to be 5 nm when adopting same fabrication procedures. Thus, the diameter of self-formed Si QDs (i.e., ddot in separated areas) and
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FIG. 1. (a) Schematic of the Si SET in the form of a Si nanowire-channel MOSFET. (b) Scanning electron microscopy image of the undulated [110] Si nanowire after isotropic wet-etching using NH4OH/H2O2/H2O. (c) Schematic of the undulated Si nanowire. (d) Expected potential profiles in the energy-band scheme (i.e., conduction band) for the multi-dot SET system formed along the undulated Si nanowire-channel.
the diameter of barrier regions (i.e., dbar in squeezed areas), which are formed in series along the Si nanowire, are expected to be ddot 3–4 nm and dbar 2 nm, respectively. In this case, since the subband modulation (i.e., quantum confinement effect) at the squeezed regions (dbar 2 nm) is much stronger than that in the separated dome regions (ddot 3–4 nm);8 one can expect that the squeezed regions will act as tunneling barriers while the dome regions will show QD features [Fig. 1(d)]. According to theoretical calculations,22,23 the quantum level spacings and the tunnel barrier heights are expected to be no less than 500 meV and 75 meV, respectively, when dbar 2 nm and ddot 3–4 nm. These allow the fabricated device to behave as a RToperating multi-dot Si SET. III. RESULTS AND DISCUSSION
Figure 2(a) shows the gate voltage vs. drain current (ID-VG) characteristic curves at RT when the drain voltage (VD) of 20 mV is applied. The SET exhibits a large CBO at VG 1.75 V with a few of shoulders and humps (i.e., vertical arrows in Fig. 2(a)). The appearance of the shoulders and/or the humps depicts that the SET is composed of multiple dots because, for a multi-dot system, a slight difference in the dot size between multiple dots would lead to stochastic tunneling events due to both different charging-energies and fluctuated
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FIG. 2. CB characteristics of the fabricated SET at RT. (a) ID-VG characteristic curves at VD ¼ 20 mV for the SET. (b) ID-VG characteristic curves at VD ¼ 0.1–0.7 V for the SET.
potential-barrier profiles (i.e., array of arbitrarily shaped dots). This can be confirmed through examining the evolution of CBO peaks at various VD points. As shown in Fig. 2(b), the main CBO peak becomes split by two peaks as VD increases. In addition, VD-dependent shifts of two separatedpeaks are not parallel. When the SET comprises multiple dots, the CBO peak could be separated or combined at high VD because the large source-drain voltage induces a large potential gradient along “source-dots-drain.” In other words, for a multi-dot system, the large potential gradient between source and drain causes an additional contribution of other dots and/or diminishes the main dots. Therefore, the separation of CBO peaks at high VD verifies the fabricated SET to compose of multiple dots. Ohkura et al. suggested that the co-tunneling probability is considerably reduced when the SET is constructed with the multi-dot system.24 Namely, the co-tunneling process giving rise to the leakage current (i.e., valley current) could be suppressed by arraying multiples dots along the channel direction; i.e., the probability of electron-tunneling from an initial state to a final state via virtual intermediate states can be significantly decreased.24 Owing to the formation of the multi-dot system in our device, therefore, we obtained the high performance SET that shows clear CBO peaks with the large peak-to-valley ratio (PVCR) 200 [Fig. 2(a)]. This can improve the functionality of the SET-based logic circuits. However, the increased valley current (i.e., increase in elastic cotunneling) at higher VD somewhat degrades the noise
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margin of the circuits, as discussed later. To minimize this effect, thus, a more sophisticated design of the multiple dot array and a further process optimization are necessary. Figure 3(a) displays the contour plot of ID at RT as functions of VG and VD. As clearly appeared in the charge diagram, Coulomb blockade (CB) regions are partly overlapped along the VG direction. This further corroborates that the fabricated device is composed of multiple QDs. As indicated by four different rhombuses, the device is expected to comprise three small dots (e.g., solid rhombuses) and one big dot (e.g., dashed rhombus). Using the single-electron charging energy model,12 we determined the dot sizes of three small dots to be 3.5 nm, 5.7 nm, and 3.7 nm. Here, we note that Si QDs in our SET are in the form of [110]-directional Si ellipsoidal QD because they are created from volumetric undulation of [110] Si nanowire. In the [110] Si nanowire, the magnitude of quantum level spacing
FIG. 3. (a) Measured contour plot of ID as functions of VG and VD at RT. (b) Highlightened Coulomb diagram at VD region. The blue, red, green, and orange dots indicated in the contour plot represent the bias points for performing the multiple logic functions of AND, OR, NAND, and XOR, respectively. (c) Definition of the bias points and the circuit configuration of the SET-based one-TR logic gate.
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becomes large (>75 meV) when the cross-sectional size shrinks down to be CD), the applied VD changes the drain Fermi potential while the dot potential is grabbed by VG. This allows the independent control of the Fermi potential at the drain reservoir by applying VD but regardless of VG. In this case, the Fermi level varying by VD will discontinuously meet the discrete quantum states, resulting in both on- and off-resonance behaviors. Hence, clear NDC peaks appear in the extended CB region. From the voltage gap in the NDC region, the quantum level spacing in the main dot is expected to be more than 90 meV. This is approximately 3.5-times-greater than the thermal energy at RT (¼ 26 meV); hence, the clear NDC peak is observable at RT. Using the NDC and CBO characteristics, we demonstrate the one-TR logic functions including AND, OR, NAND, and XOR logic functions. The NAND logic gate is highly needed for the application of CMOS-compatible digital circuits,25 and the XOR logic gate is a key element to realize the Boolean arithmetic circuits.4 Thus, first, we show one-TR NAND and one-TR XOR logic functions. As highlightened by red and blue thick-curves [Fig. 4(a)], the ID curves at two VG (i.e., VG ¼ 0.88 V ¼ LOW and VG ¼ 1.84 V ¼ HIGH) are crossing at ID ¼ 1 nA ( ¼ L) when VD is 0.55 V ( ¼ L). However,
the magnitudes of ID are different at VG ¼ L and VG ¼ H when VD of 0.2 V (¼ H) is applied. By applying VG and VD as the two input voltages, therefore, ID will behave as a NAND output source, as summarized in the left-hand-side inset of Fig. 4(a). Here, we also note that the output resistance (RO) of 10 MX from the active load of an additional MOSFET is used to convert the output current to the voltage output (VO) [right-hand-side inset of Fig. 4(a)]. Figure 4(b) shows the measured transient waveforms of VO with varying VG (¼ VIN1) and VD (¼ VIN2). The waveform of VO clearly reveals the NAND operation. The small and noisy voltage offsets at the ON/OFF state are attributed to offset charges at the extended CB state. In other words, the increased valley current at high VD causes the small and noisy offset-voltage at ON and/or OFF states, and this may degrade the noise margin of the circuit. In the same way, we also demonstrate the XOR logic function by utilizing the identical device used above. Considering the fact that NDC curves are crossing at two different VG points (i.e., VG ¼ 0.92 V ¼ LOW and VG ¼ 1.66 V ¼ HIGH), we can take four output points by choosing VD of 0.73 V (¼ LOW) and 0.31 V (HIGH) [Fig. 5(a)]. As summarized in the left-hand-side inset in Fig.
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the Coulomb gap and the slopes of the Coulomb diagram. Thus, the time constant ( RjCdot) of our SET can be estimated to be less than 1 ns, from which the intrinsic speed of the device is deduced to be no less than GHz. However, it should be noticed that the actual speed of the CMOS-compatible Si SET would be much degraded because of the inevitable resistances and capacitances from parasitic MOSFETs underlying the actual device of the SET. Due to these factors, the best operating speed of the Si SETbased analog and digital circuits is still less than a few of hundreds MHz.1,2,26 According to Ono et al.’s review on Si single-electron devices, some research groups have reported junctionless SETs, where no tunnel junctions are required; hence, the operational speed is not limited by the tunnel resistances and/or capacitances. Thus, implementing such a concept in our device structure can be the next step to improve the speed of the multi-functional Si SET-based oneTR logic circuit. IV. CONCLUSION
FIG. 6. (a) Transient waveforms of the one-TR AND gate at RT. (b) Transient waveforms of the onexTR OR gate at RT.
5(a), the selected bias points provide the output characteristics of the XOR logic gate. Figure 5(b) shows the measured transient waveforms of VO when the square pulses of VG and VD are applied as VIN1 and VIN2, respectively. The transient characteristics of VO depict that the SET behaves as the oneTR XOR logic gate. Through mimicking the above manners, we also demonstrated AND and OR logic functions [Figs. 6(a) and 6(b)]. Consequently, we clearly observed the multiple logic functions in a single device of the RT-operating Si SET. The demonstration of the multi-functionality is ascribed to the remarkable extension of the CB regime, originating from both the large quantum-level spacing in the dot and the large voltage gain of the device. Although the magnitude of VO is quite low because of CBO/NDC’s low current levels, the device can be effectively used for highly sensitive currentdriving low-power sensors in future ULSI circuits. Finally, we state that the speed of the SET-based logic circuits would be limited by the magnitudes of both resistances and capacitances of the tunnel junctions. Basically, the SET consists of a single QD or multiple QDs, and those are capacitively coupled to the electron reservoirs through the tunneling barriers. This makes an electron tunneling through the tunnel junctions of “barrier-QD-barrier”. In our device, the channel conductance near the CBO peak is in the order of 10 s nS, which corresponds to the junction resistance (Rj) of a few of hundreds MX. In addition, the dot capacitance (Cdot) is determined to be 1.2 aF, in average, from
Multiple logic functions were demonstrated at RT on a unit device of the Si SET. The SET showed the clear CBO peak with a large PVCR 200, resulting from the formation of the multi-dot system. The device clearly revealed the strongly extended CB region, where the NDC peak positions are systematically shifted to various VD points by changing VG. This enables the fabricated SET to act as a one-TR logic gate. By using these futures, we eventually demonstrated the multiple logic functions in a single device of the SET; for example, AND, OR, NAND, and XOR logic functions were achieved by choosing the specific bias points near the extended CB region. ACKNOWLEDGMENTS
This research was supported by the National Research Foundation of Korea through the Basic Science Research Program (NRF-2014R1A2A1A11050882) funded by the Korean government (MSIP) and the Basic Science Research Program (NRF-2014R1A6A3A01009566) funded by the Korean government (MoE). 1
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