On using IEEE 1500 standard for functional testing (PDF Download ...

On Using IEEE 1500 Standard for Functional Testing Ghazanfar Ali, Fawnizu Azmadi Hussin, Noohul Basheer Zain Ali, Nor Hisham Hamid Centre for Intelligent Signal and Imaging Research (CISIR), Electrical and Electronic Engineering Department, Universiti Teknologi Petronas, Perak, Malaysia. [email protected], {fawnizu, noohul.z, hishmid}@petronas.com.my Michael Higgins et-al. [5], proposed a novel test controller, System on Chip Embedded Core Test (SoCECT) that allows multiple IEEE1500-compliant cores to be tested concurrently by configuring them in test mode. To operate the test controller, the proposed design used the IEEE 1149.1 JTAG state machine to allow the future integration with onchip instrumentation interface. Po-lin et-al [6], proposed a new embedded delay test framework with a new modified Wrapper Boundary Register (WBR) architecture of IEEE 1500 standard for at-speed delay testing. So far all the developments in IEEE 1500 standard are for testing application in the test mode. No development in IEEE 1500 standard is proposed where IEEE1500-compliant cores can be tested in functional mode of operation like by using software based self-testing (SBST) technique. There are instructions like INTEST and SAMPLE supported by the current IEEE 1500 standard [1] which makes functional as well as structural testing possible but these instructions can be used only in test mode. With the use of these instructions a way to carry out functional test is proposed in [2], [4] and [5] where the test vectors are applied on the CUT by the onchip tester, by isolating it from the functional environment. The limitation of test mode testing is that some faults that crop up only in the functional mode may not be detected. In this research, an improvement to the IEEE 1500 standard for functional testing has been proposed. The proposed enhancement will allow the same modified IEEE 1500 standard to be used in functional mode as well as in test mode, increasing its reusability. Our proposed improvement to the IEEE 1500 standard also increases the observability as it allows the on-chip tester to take snapshots of all the internal states during the functional mode. To make functional mode testing possible, the proposed IEEE 1500 standard is used with the SBST which is one of the very special on-chip functional testing techniques [7]. In SBST, the basic idea is to generate test vectors by executing instruction sequences. The processor itself detects the possible faults by looking at the responses [8]. In SBST technique, observable points are very important. Test programs are written in a way that faults are propagated to the observable points [9]. By using this approach getting high fault coverage becomes a very challenging job when it comes to a complex processor as they have low internal observability especially for detecting defects in control paths [10]. Use of proposed enhanced IEEE 1500 standard in SBST also can increase the observability that can result high fault coverage. The paper is organized as follows; in section-2, the methodology is explained that includes explanation of development of each block of IEEE 1500 standard. In section-3 the case study is explained where arithmetic logic

Abstract In core based design (i.e. System on Chip) testing, IEEE 1500 standard has become a widely used option because of its completeness and easy to use approach, but this standard is only supported in the test mode as it stays transparent in the functional mode. In this paper, a proposed method to enhance the IEEE 1500 standard for functional testing in order to increase observability during functional test is discussed. As a case study, the proposed enhanced IEEE 1500 standard is implemented and validated on SAYEH processor in order to test it using embedded Software Based Self-Testing (SBST) technique. The case study demonstrated that the modification to the IEEE 1500 standard enables it to be used for functional testing, with increased observability.

Keywords IEEE 1500 Standard; Functional Testing; SBST

1. Introduction

System on chip (SOC) makes it possible to design a complex system in a short period of time by using intellectual property (IP) blocks. The complexity of the design makes testing of the SOC a very difficult task. To alleviate this test access issue, IEEE 1500 has been introduced in 2005 to standardize design for testability (DFT) strategy of SOC [1]. This standard allows the embedded cores to be tested by the external tester i.e. automatic test equipment (ATE), or the internal tester by isolating it from the functional environment and putting it in test mode. The isolation boundary allows the reuse of test for the circuit under test (CUT) as well as the logic circuit between two wrapped cores [1]. Different techniques have been developed to test IEEE1500-compliant SOC. Mathhieu Tuna et-al., proposed an embedded Micro-Tester architecture that executes the test program from an external memory to test IEEE1500compliant cores at-speed by isolating the wrapped core from functional environment [2]. Laung-Terng et-al., proposed TurboIEEE1500 that serves as an automation tool by automatically connecting all the IEEE1500-compliant cores [3]. Kuen et-al. [4], proposed an on-chip at-speed test platform for IEEE1500-compliant cores to eliminate the use of expensive ATE. The proposed platform can handle various types of embedded cores that include built in selftest (BIST) based memory cores, scan-based logic cores, BIST-based mixed-signal devices, and hierarchical cores. To generate the control signals for different cores, a centralized test access mechanism (TAM) was introduced.

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unit (ALU) of SAYEH (Simple Architecture Yet Enough Hardware) processor is wrapped with our modified IEEE 1500 standard and is tested by using SBST while in section4, simulation results are discussed in detail.

2. Methodology

The IEEE 1500 wrapper design is shown in the Figure 1. There are three major components of this standard namely Wrapper Instruction Register (WIR), Wrapper Boundary Register (WBR) and Wrapper Bypass Register (WBY) [1]. Current IEEE 1500 architecture (Figure 1) can be used only in test mode where CUT is isolated from the functional environment and test vectors are applied by an external or internal tester. There are three basic testing modes supported by the current design known as intest, extest and bypass mode. In intest mode, all the vectors are applied on CUT itself to test CUT. In extest mode, logic circuit between two wrapped cores is tested. In bypass mode, test data is bypassed by using WBY to reduce the test time.

Figure 1: DFT for test application using IEEE 1500 standard

Figure 2: Enhanced IEEE 1500 standard architecture (highlighted modules are the new addition to the standard)

Complete architecture level diagram of the proposed modification of the IEEE 1500 standard is shown in Figure 2. For functional testing, a new mode of testing is introduced, called as ‘functional testing mode’. In functional testing mode, instead of isolating CUT from the functional environment and applying test vectors from external tester, CUT is allowed to work in functional mode. All the functional data either coming on the input port of CUT or coming out from CUT on its output port, is snooped by MISR (multiple input shift register) modules through WBR cells. For this purpose WBR has been modified. These MISR blocks are initialized with a seed value to set them in a known state. After initializing the MISR, it takes the data from the respective port and generates a signature. This generated signature can be sent out for comparison purpose. This modified design of IEEE 1500 standard supports testing in both modes i.e. test mode and functional mode. In order to set the IEEE 1500 standard in functional mode or test mode some control signals are applied externally i.e. WRSTN, CaptureWR, SelectWIR, ShiftWR and UpdateWR.

when ‘updateWR’ signal goes high. These control signals set the IEEE 1500 wrapper in intest, extest, bypass and functional testing mode. There are two new control signals added to the current IEEE 1500 standard i.e. ‘wir_snooping’ and ‘wir_signature’. Addition of these control signals although increases the area overhead but it is justified as it allows the IEEE 1500 standard to perform testing in functional mode. In order to set the wrapper in functional testing mode, two new instructions have been introduced as shown in Table 1.

2.2. Wrapper Boundary Register (WBR) WBR controls the inputs and outputs of the CUT. It allows the wrapper to execute functional mode, test mode or functional test mode. WBR is placed between the input and output of the circuit as shown in Figure 2. During the functional mode, WBR stays transparent and do not interfere with incoming or outgoing data. In test mode, it isolates the CUT from the functional environment and applies the test vector on the CUT that is shifted into WBR through WSI from the tester. The WBR that is connected at the output of CUT captures the response and it is shifted out through WSO. In the functional testing mode, the incoming and outgoing data is snooped on every clock cycle and sent to the MISR block.

2.1. Wrapper Instruction Register (WIR) WIR is the brain of IEEE 1500 standard. It generates all the control signals to control other IEEE 1500 wrapper components i.e. WBY, WBR, MISR blocks and the multiplexer (MUXES). In order to generate the control signals, 4-bit OPCODE is serially shifted into WIR through the WSI port. This OPCODE is decoded and control signals are generated, same as in [1]. Figure 3 shows the block level diagram of WIR.

Figure 4: Modified WBR cell To operate in functional mode, test mode and functional test mode, WBR cell is configured into five different states. These states are called functional, hold/apply, capture, shift and functional snooping as shown in Figure 4a. The signals A, B, C, D, E, S, T, V and W represents CFI, CFO, CFTO, CTI, CTO, wir_snooping, wir_shift, hold_enable and SE respectively in Figure 4a. These states are set by controlling two multiplexers and three buffers in the WBR from the WIR. In the design, main focus is on the functional test mode. When ‘wir_snooping’ is set high, data coming on CUT’s input or going out from CUT, is snooped.

Figure 3: Wrapper Instruction Register (WIR) In the Figure 3, “4 Bit Shift Register” is a four bit shift register, controlled with a control signal ‘ShiftWR’ when SelectWIR signal is set high. After the OPCODE is successfully shifted into the shift register, it is decoded and the control signals are generated with instructions decode logic circuit. These generated control signals are applied Table 1: Table of instructions used in functional testing Instruction Name

OPCODE

Control Signals se

hold_enable

wir_shift

wir_snooping

wir_signature

WS_FUNCTIONAL_SNOOPING

1101

0

0

0

1

0

WS_SIGNATURE_OUT

1110

x

x

x

x

1

Figure 5: Wrapper Bypass Register

2.4. Multiple Input Shift Register (MISR) The purpose of Multiple Input Shift Register (MISR) blocks is to generate the signature for each input and it updates its signature on the clock edge. There are 2 MISR blocks shown in the general architecture of enhanced IEEE 1500 wrapper. The output of MISR blocks is controlled by a control signal ‘wir_signature’. The output MISR is useful in testing the wrapped core while the input MISR can identify whether the data-path through which the wrapped core is taking input is faulty or not. MISRs have flexibility to be set on a known state by loading an initial seed value. When the wrapper is in functional testing mode, all the snooped data goes to the MISR blocks through the WBR. These MISR blocks forms signature for respective data and update it on every clock cycle. This signature accumulation allows the internal or external tester to validate that CUT is working without any error over a long period of time, without closely monitoring all the internal states. There are two types of cells used while building the MISR block. Cells with feedback consists of one 2 to 1 MUX, two XOR gates and one Flip Flop (FF) as shown in Figure 6a (1) while Cells without feedback consists of one 2 to 1 MUX, one XOR gate and one Flip Flop (FF) as shown in Figure 6a (2). Figure 6 illustrates the complete 16-bit MISR block that is built by using above mentioned cells. Any time during the signature formation, the signature can be loaded into the registers I and O as shown in the Figure 2 and can be sent to the tester for signature comparison over the test bus. This is done by loading the instruction “Signature out” into the WIR.

Figure 4a: (1) Functional, (2) Hold/Apply, (3) Capture, (4) Shift, (5) Functional snooping

2.3. Wrapper Bypass Register (WBY) WBY is used to bypass the circuit under test (CUT). It reduces the overall test time by providing the shortest path between two wrapped cores. Bypass operation is controlled by a control signal ‘WBY-shift’. WBY block consists of a MUX and a D flip flop as shown below in Figure 5, same as presented in [1].

Figure 6a: MISR cells, with feedback (1) and without feedback

Figure 6: 16 bit Multiple Input Shift Register (MISR)

3. Case Study

15 12 11 10 09 08 07 00 As a motivation for the proposed software-based selftesting (SBST) methodology, we have applied our enhanced OPCODE Left Right Immediate IEEE 1500 wrapper on a processor core SAYEH, which is a Figure 7: SAYEH Instruction format free opencore processor for educational purpose. SAYEH has a 16-bit data bus and address bus. This processor supports 29 different instructions that include addition, subtraction, multiplication and jump instructions. There are two types of instructions used in this processor, one is 8-bits and the other one is 16-bits. General format of the instruction is shown in Figure 7. In the instruction format, first 8-bits are for immediate data, bit-8 and bit-9 are for source register selection, bit-10 and bit-11 are for destination register selection and the last 4bits are for OPCODE. Immediate field is only required in case of 16-bit instructions; in case of 8bit instructions, this field is filled with code 0F. ‘Left’ and ‘Right’ portions in the instruction format are 2-bit code to select R0 through R3 as destination and source registers respectively. The last four bits are for OPCODE (bit-12 to bit15) and the initial 8 bits are for immediate data. Figure 8: Microarchitecture of SAYEH processor with the proposed DFT for enhanced functional testing

In this case study, ‘Arithmetic Unit (AU)’ of SAYEH processor is wrapped with our modified IEEE 1500 wrapper and connected with another embedded module ‘Tester’. The architecture of ‘Tester’ can be modified to allow external or internal tester to test the processor in the test mode. In this paper, our emphasis is only on functional testing so the architecture of ‘Tester’ is kept simple; the ‘Tester’ only generates control signals for enhanced IEEE 1500 standard and compares the signature received from the wrapped module over the test bus with the pre-computed signature. A test program is loaded in the memory to be executed by the SAYEH processor. To control the wrapper and to set it into functional testing mode, ‘Tester’ generates the control signals, i.e. WRSTN, CaptureWR, SelectWIR, ShiftWR and UpdateWR and loads the instruction through WSI port. After the complete execution of the test program, it receives the signature data from the wrapper over the ‘Test bus’. This received signature is then compared with the pre-determined known good signature.

Figure 7: Functional test flow diagram of SAYEH processor with enhanced IEEE 1500 standard

Figure 8: Test program

4. Result and Discussion

Simulation results are shown in Figure 11 and Figure 12. In the simulation results, ‘clk’ is the system clock, ‘Addressbus’ and ‘Databus’ are 16-bit system busses on which the processor sends and receives address and data respectively. ‘ExternalReset’ is the external reset signal that resets the processor when it goes to logic value ‘high’. ‘ReadMem’ and ‘WriteMem’ enables the processor to read and write memory. ‘AaddB’, ‘AmulB’, ‘AsubB’ indicate addition, multiplication and subtraction operations, respectively. Since our objective is to test the AU, all the instructions used in this example test program involved only the AU operations as shown in Figure 10. By executing this test program, test vectors are applied on the AU by using two 16-bit system registers R0 and R1. ‘A’, ‘B’ and ‘aluout’ are the signals that appear on the inputs and output of AU. These signals are snooped by our modified IEEE 1500 standard and signature is generated for each input and output of the AU. For this specific case study 3 MISR blocks are used, 2 for inputs (A and B) and 1 for the output (aluout). To control the operation of enhanced IEEE 1500 standard, control signals are generated by the embedded tester ‘Tester’. In order to make the system synchronous, the processor and the proposed enhanced IEEE 1500 standard share the same clock i.e. clk and WRCK are same. To configure the system in functional testing mode, ‘Tester’ generates ‘WRSTN’, ‘CaptureWR’, ‘SelectWIR’, ‘ShiftWR’ and ‘UpdateWR’. Signal transitions of these control signals between first two markers (116ns and 405 ns) in the Figure 11 and Figure 12 explain how these control signals are generated. To initiate the MISR blocks with a known state, it is loaded with a seed value ‘a011h’. Loading of this seed value depends on the ‘wir_sig’. In this case study ‘wir_sig’ is independent of any instruction. As the system starts, ‘wir_sig’ goes high on the 3rd negative edge of the clock as shown in Figure 11 and Figure 12. By default the state of IEEE 1500 standard is in functional mode. So in order to configure it in functional testing mode, opcode ‘1101’ is shifted into the WIR through WSI. It is decoded inside the WIR and the control signals to control the enhanced IEEE 1500 standard are generated. Major control signal is ‘wir_snooping’ that goes high when this instruction is decoded, allowing the WBR cells to snoop the data and send it to the respective MISR block. MISR blocks generate signature and update it on every negative edge of the clock. After a specific time ‘Tester’ sent another instruction ‘1110’ through ‘WSI’ to transport out the signature. When this instruction is decoded in WIR, control signal ‘wir_signature’ is set to logic value ‘high’ that update the three registers—‘Signature_A1’, ‘Signature_B1’ and ‘Signature_S1’--with the current MISR state as shown in the Figure 11 an Figure 12. The same control signal i.e. wir_signature allows the registers to send data on the testbus one by one by enabling a 3 bit counter that controls the MUX. This signature is then compared with the precomputed signature. If the signature matches with the precomputed signature then the value of test-flag is set ‘high’, else the test flag is set ‘low’.

Figure 9: SAYEH simulation with enhanced IEEE 1500 standard, when SAYEH is fault free.

Figure 10: SAYEH simulation with enhanced IEEE 1500 standard, when SAYEH is faulty.

The test program (Figure 10) is executed twice on the SAYEH processor. In the first run, fault-free SAYEH processor executed the test program. Results (Figure 11) showed high value of ‘test_flag’ after 1200ns which means that the pre-computed signature matches with the actual signature. In the second run, an error is introduced in the addition operation of AU of SAYEH processor that executed the test program. Simulation results (Figure 12) showed that this causes the mismatch between actual and pre-computed signatures as test_flag after 1200ns stayed at low logic value. In this case study a very simple program is used to validate the idea of functional testing by using modified IEEE 1500 standard. A good test program can test the wrapped module for all the possible faults through this method.

[6]

[7]

[8]

[9]

5. Conclusion

In this paper, an enhanced IEEE 1500 standard for functional testing has been discussed and evaluated experimentally. All the modules of the enhanced IEEE 1500 standard are discussed in detail in section-2 of the paper. In order to demonstrate the proposed methodology as used in functional testing, SAYEH processor is used as a case study. Simulation results discussed in section-4 showed that this modified IEEE 1500 standard can be used for test application in the functional mode as well. This will allow the test engineers to test the CUT in functional (snooping mode) as well as in test modes by using the same IEEE 1500 standard which increases the reusability of design. This proposed architecture also increases the observability of the CUT during functional test by having the ability to capture and transport out the internal states.

6. Acknowledgement The project was supported in part by the Ministry of Science, Technology and Innovation (MOSTI) under the Science Fund (03-02-02-SF0141) and by Universiti Teknologi PETRONAS under the Graduate Assistantship scheme. The authors would like to acknowledge the Centre for Intelligent Signal & Imaging Research (CISIR) for providing the facilities to conduct this research.

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