Optimized Modeling and Control Strategy of the

electronics Article

Optimized Modeling and Control Strategy of the Single-Phase Photovoltaic Grid-Connected Cascaded H-bridge Multilevel Inverter Seongjun Lee 1 and Jonghoon Kim 2, * 1 2

*

School of Mechanical System & Automotive Engineering, Chosun University, Gwangju 61452, Korea; [email protected] Department of Electrical Engineering, Chungnam National University, Daejeon 34134, Korea Correspondence: [email protected]; Tel.: +82-42-821-5657

Received: 11 August 2018; Accepted: 14 September 2018; Published: 18 September 2018







Abstract: This paper presents the modeling and control-loop design method with an inverted decoupling scheme of a single-phase photovoltaic grid-connected five-level cascaded H-bridge multilevel inverter. For the unity power factor, the proportional and integral current controller with a duty ratio feed-forward compensation is used. In addition, in order to achieve the maximum power point tracking of each photovoltaic array, when the stacked modules are in the partial shading condition, each direct current (DC) voltage is stably controlled to their maximum power points (MPP) by dedicated voltage controllers of each H-bridge module. This paper also presents a control method that minimizes the effect of the loop-interaction in the design of an individual DC-link voltage control loop in a two-input two-output system. The proposed control methods of the cascaded H-bridge multilevel inverter are validated through the simulation and experimental results of the 2-kW prototype hardware. Keywords: Cascade H-bridge; multilevel inverter; two-input two-output; individual voltage control; maximum power point

1. Introduction The multilevel converter can improve efficiency by enabling the use of components with better characteristics due to the reduced voltage stress, and has the advantage of lowering electromagnetic emissions by providing a staircase output voltage [1–10]. Thus, the use of a multilevel converter has increased in industrial and renewable energy applications, which require high-voltage and high output quality [11–14]. In recent times, studies of photovoltaic applications with multilevel topologies have made progress in increasing the efficiency and lowering the electromagnetic interference (EMI) and core losses [10–17]. The multi-level converter has been used mainly in renewable energy systems using high-voltage above kV, but researches are expanding to low-voltage applications to take advantage of the aforementioned merits [16,17]. Among several studies, because isolated direct current (DC) sources are naturally obtained from the photovoltaic (PV) arrays, and can be easily modularized compared to other multilevel converters, a PV generation system with the cascaded H-bridge multilevel inverter topology has been studied [16–25]. Reference [16] presented a study on the reactive power compensation for the single phase grid-connected cascaded H-bridge multilevel inverter, but they did not fully suggest the method for designing the controller. The results of applying a cascaded H-bridge multilevel inverter to the rooftop photovoltaic micro-inverter as a low-voltage application were studied in [17]. In this paper, they present the results of a power balancing scheme using a multi-level inverter in a two-stage power conversion architecture. However, there is no analysis for control-loop design and only simulation results are presented. Electronics 2018, 7, 207; doi:10.3390/electronics7090207

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In grid-tied PV generation systems, the single stage structure requires many series-connected PV modules for making PV arrays with a high voltage. However, each of the stacked PV modules has its optimal maximum power points (MPPs) owing to the partial shading when the PV operates under a non-uniform irradiation. When the illumination level is decreased because of non-uniform irradiation, the whole PV system has multiple maximum power points. In this situation, the maximum power point tracking (MPPT) algorithm is apt to fall into the local MPPs and the output power is considerably decreased [26–33]. However, this problem can be mitigated by using the cascaded H-bridge multilevel inverter. When using the cascaded H-bridge multilevel inverter, PV modules are separately divided and grouped by the number of H-bridge modules, and the output voltage of PV arrays can be controlled to achieve their MPPs. Thus, the control loop design should be taken into account, in order to achieve the individual voltage control of each PV array and the unity power factor control in multi-input multi-output systems. In [34], the individual DC-link voltage control and PWM method are proposed in order to achieve the aforementioned objectives. However, the loop-interaction and solutions among H-bridge modules are not presented. Compared with a previous conference paper [35], we further present the inverted decoupling control method and the simulation results to show the effectiveness of the proposed method to minimize the loop gain interactions that occur when controlling each PV array voltage. Furthermore, we describe the detailed modeling process and simulation results for verification of the designed controller that was not presented in the previous paper to make it easier for other researchers to understand. In addition, the MPPT algorithm for tracking the MPPs of the photovoltaic system is further described. In this paper, the controller design method with an inverted decoupling scheme of the cascaded H-bridge multilevel inverter for achieving an individual MPPT of each PV array and the unity power factor of the grid current is presented. The proportional and integral (PI) current controller, with the duty ratio feed-forward compensation method for minimizing the steady-state error and the phase delay is applied. In addition, in order to avoid a local MPPT, the output voltage of each PV array is individually controlled through the decoupled loop gain design method of the two-input two-output (TITO) system. The proposed small signal modeling and control loop design methods are validated through the simulation and experimental results of the 2-kW five-level single-phase cascaded H-bridge multilevel inverter system. The remainder of this approach is organized as follows. This approach is divided into four parts including this introduction section. To begin with, the small signal transfer function of the cascaded H-bridge multilevel inverter based on the small signal modeling approaches are derived in Section 2. Also, the current and voltage controller design methods using the inverted decoupling method of two-input two output system are described. Section 3 shows the simulation and experimental setup and the results of the proposed approach. The experimental results show the validity of the proposed individual voltage control for obtaining the maximum power of each PV module. In the final section, some conclusions and final remarks are given. 2. Modeling and Control Loop Design Method 2.1. Small Signal Modeling of Five-Level Cascaded H-bridge Multilevel Inverter The single-phase five-level cascaded H-bridge multilevel PV system is shown in Figure 1. In order to design the control loops, a small signal model, based on the state space averaging method [36,37], is developed. More detailed small-signal modeling is given in [37]. The input currents and output voltages of each H-bridge power stage of Figure 1 are defined as (1)–(4), using the switching states shown in Figure 2.

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PV PV

PV PV

iin1

idc1

iin1

isdc1 11

s31

s+11

s31

+

C1 V + dc,1 s41 s21 C1 Vdc,1 s41 s21

+

+

Vsw1

L

iL

L

iL

+

Vsw1

-

Vsw

iin2

idc2

iin2

isdc2 12

s32

s+12

s32

Vg

Vsw +

dc,2 C2 V + s22 s 42 C2 V-dc,2 s42 s22

+ -

Vg

Vsw2 -

Vsw2 -

Figure 1. Single-phase photovoltaic cascaded H-bridge multilevel inverter. Figure Figure 1. 1. Single-phase Single-phase photovoltaic photovoltaic cascaded cascaded H-bridge H-bridge multilevel multilevel inverter. inverter. Ts 1

Ts

Vc*

1

Vc*

1  Vc*

0

11 Vc*

S011

d11

31 SS11

1-d d1111

SS31 12

1-d11 d12

S12 S32

1-d d1212 1-d12

S32 vsw1 sw2 vvsw1

vsw2 vsw vsw

0 11 00 11 00 11 00 1 V0dc 0 VVdc dc 00 Vdc 0 2Vdc Vdc 2Vdc 0 Vdc 0

Figure 2. Relationship of switching states and duty ratios of the cascaded multilevel inverter. Figure 2. Relationship of switching states and duty ratios of the cascaded multilevel inverter.

Figure 2. Relationship of switching states and duty ratios of the cascaded multilevel inverter.

vvsw1 =ss11 vv s31svdc,1 dc,1 −  v

sw1 11 dc,1 31 dc,1 vvsw2 = s vdc,2 s31 vdc,1 sw1  s1211vvdc,2 dc,1−s32 vsw  s v  s v i 2 = 12 s idc,2 − s i32 dc,2 dc1

11 L

31 L

vsw2  s12vdc,2  s32vdc,2 idc2 i Li −s32 iL idc1=s12 s11 L s31iL

(1) (1) (2) (1)

(2) (3) (2) (4) (3)

S11 and S31 are switching states of theidc upper switches iL  s31of iL each leg in the upper H-bridge module (3) 1  s11  compared s12iL  s32result iL (4) and can take the values 1 or 0, according ito between the modulating (vc *) and dc 2the carrier signal, as shown in Figure 2. idc1 and v are the input current and the output voltage of the  sswitches iLeach leg in the upper H-bridge module (4) 2 sw1 12iL  s32of S11 and S31 are switching states of theidc upper upper H-bridge module, respectively. Similarly, S12 , S32 , idc2 , and vsw2 are switching states of upper and S can take the values 1 or 0, according to the compared result between the modulating (vc*) and 11 and S31 are switching states of the upper switches of each leg in the upper H-bridge module switches of each leg, the input current, and output voltage in the lower H-bridge module, respectively. carrier signal, as values shown inorFigure 2. idc1 and vsw1 compared are the input current and the the modulating output voltage ofand the and 0,voltage according to upper the result between (vc*) Vdc,1can andtake Vdc,2the are the DC1 link of the and lower H-bridge modules, respectively, and iL upper H-bridge module, respectively. Similarly, S 12, S32, idc2, and vsw2 are switching states of upper carrier signal, as shown in Figure 2. i dc1 and vsw1 are the input current and the output voltage of the is the filter inductor current. upper H-bridge module, respectively. Similarly, S12, S32, idc2, and vsw2 are switching states of upper

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Assuming that the switching frequency fs is higher than the frequency of the modulating signal vc *, the averaged state equations are derived as (5)–(7). L

di L = (2d11 − 1)vdc,1 + (2d12 − 1)vdc,2 − v g dt

(5)

C1

dvdc,1 = iin1 − idc1 dt

(6)

C2

dvdc,2 = iin2 − idc2 dt

(7)

Here, the switching states are changed to duty ratios d11 and d12 . L, C1 , and C2 are the output inductor and DC link capacitors of power stages as shown in Figure 1. Vg , iin1 , and iin2 are the grid voltage and the current of each PV module. By applying the perturbation and linearization technique, the small signal state equation can be derived as (8), from which transfer functions, such as duty ratio to inductor current and duty ratio to each DC voltage, can be obtained.  d dt 

iˆL





0

dc,1

L  L + − 2I C1 0

dc,2

L

0 L − 2I C2

(2D12 −1) L



ˆ  i L  0 0  vˆ dc,1 vˆ dc,2 0 0   " # 0 0 − L1  dˆ11   0  +  C11 0  ˆ  d12 0 C12 0

 (2D11 −1) =  − C1 − (2DC122−1)  2V  2V

 vˆ dc,1  vˆ dc,2

(2D11 −1) L

    iˆin1  iˆin2  vˆ g

(8)

2.2. Current Controller Design Method Because the proportional-integral (PI) current control in an AC system has a steady state error and phase delay for the reference current, the duty ratio feed-forward method is used to improve the grid current control performance. From the small signal state equation in (8), transfer functions with respect to duty ratios and grid voltage of upper and lower H-bridge power stage can be derived as (9)–(11).  Gi L d11 =

2V  iˆL = dc,1  ˆ L  d11

 s2 +

1 L

 Gi L d12 =

2V  iˆL = dc,2  ˆ L  d12

Gi L v g =



(2D11 −1) C1

 s2 +

1 L



s−

(2D11 −1) IL C1 Vdc,1

s−

2

(2D12 −1) C2

(2D12 −1) IL C2 Vdc,2

(2D11 −1) C1

2

iˆL s  =−  vˆ g (2D11 −1)2 L s2 + L1 + C 1

+

+



 2

  





(2D12 −1) C2

(2D12 −1)2 C2

(9)

2

  



(10)

(11)

Since the generated power of the PV array is generally measured for the MPPT algorithm, the duty ratio relationship for feed-forward can be derived as (12) with respect to PV array powers under steady-state conditions of the averaged model. Thus, duty ratios to grid voltage of each H-bridge module is derived as (13).     Pin,i · v g Iin,i 1 1 D1i = 1+ = 1+ , i = 1, 2 (12) 2 IL 2 Pin,tot · vdc,i 1 Pin,i dˆ1i = vˆ g , i = 1, 2 2 Vdc,i · Po

(13)

1  Iin,i D1i  1  2 IL

  

Pin,i  vg 1 1  2  Pin,tot  vdc,i

  , i  1, 2  

(12)

1 Pin,i dˆ1i  vˆg , i  1, 2 2 Vdc,i  Po

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where, and Pin,2 are the output power of each PV array, Pin,tot is the sum of the powers of two PV where, P Pin,1 in,1 and Pin,2 are the output power of each PV array, Pin,tot is the sum of the powers of two PV arrays, and is the voltage of each PV array. arrays, and V Vdc,i dc,i is the voltage of each PV array. In forfor thethe grid current andand each DC-link (PV(PV array) voltage, the In order orderto todesign designthe thecontrol controlloops loops grid current each DC-link array) voltage, current control loop in Figure 3 is designed first. As shown in Figure 3, the inductor current injected the current control loop in Figure 3 is designed first. As shown in Figure 3, the inductor current injected into into the the utility utility grid grid is is the the sum sum of of the the current current control control result result of of the the upper upper H-bridge H-bridge module module and and the the current control result of the lower H-bridge module from the controller design point of view. In this current control result of the lower H-bridge module from the controller design point of view. In this ˆ to inductor current and case, to inductor current in the stage power Figure 3 are dˆ11inductor 11 to inductor current and dˆ11 to case, dˆd11 current in the power of stage Figureof3 are expressed expressed (9)At and (10) At H this Hi is a proportional integral (PI)controller, current controller, andgain the and DC by (9) andby (10) this time, a proportional integral (PI) current and the DC i istime, gain of PI can controller can besodesigned that each current control loop has afrequency high cut-off zero and of PIzero controller be designed that eachso current control loop has a high cut-off and frequency a sufficient margin. In general, the cutoff frequency should be designed have a sufficientand phase margin. phase In general, the cutoff frequency should be designed to have a phaseto margin agreater phase than margin degrees. The duty ratio feed-forward scheme is employed attenuate 45 greater degrees.than The45 duty ratio feed-forward scheme is employed to attenuate theto disturbance the disturbance of the grid and effectsare of shown this scheme are shown in section 3. of the grid voltage, and thevoltage, effects of thisthe scheme in section 3.

iˆL1* +

Hi

dˆ11_fb + +

dˆ11_ff Z -1

dˆ 11 dˆ 12

Power Stage

Ti1

vˆdc,1 vˆdc,2 iˆL

Ti2

iˆL2* +

Hi

dˆ12_fb +

Z -1

+ ˆ d12_ff Figure3. 3.Small Smallsignal signalcurrent-loop current-loopcontrol control block block diagram diagram for for grid grid current current control. control. Figure

2.3. Voltage Controller Design Method It is necessary to design a voltage controller that can control input voltages of the PV arrays to determine the current reference in the state where the current controller is implemented. When the current-loops are closed, the transfer functions of the input voltages (Vdc,1 , Vdc,2 ) to each H-bridge module current are firstly derived. Then, the voltage controller should be designed to stabilize the transfer function of the voltages to the current reference, and the detailed procedure is as follows. The previously mentioned current loop closed system can be considered as the TITO system as shown in dotted box of Figure 4. g11 is the transfer function of the upper PV array voltage of the upper H-bridge module, with respect to the reference current, denoted as vˆ c1 , and g12 is the transfer function of the upper PV array voltage of the lower H-bridge module, with respect to the reference current, denoted as vˆ c2 . The derived transfer functions are represented as (14)–(17). In Figure 4, Hv represents the controller for the voltage control of the current loop closed system. g11 =

Hi Gvdc,1 d1 (1 + Ti2 ) − Ti1 Hi Gvdc,1 d2 vˆ dc,1 = vˆ c1 1 + Ti1 + Ti2

Hi Gvdc,1 d2 (1 + Ti1 ) − Ti2 Hi Gvdc,1 d1 vˆ dc,1 = ˆvc2 1 + Ti1 + Ti2   (2D11 −1)Vdc,1 (2D12 −1)2 2 s + s+ LIL LC2 vˆ 2I   = dc,1 = − L  C1 dˆ11 (2D11 −1)2 (2D12 −1)2 s s2 + L1 + C C2

g12 =

Gvdc1d1

1

(14)

(15)

(16)

2.3. Voltage Controller Design Method It is necessary to design a voltage controller that can control input voltages of the PV arrays to determine the current reference in the state where the current controller is implemented. When the current-loops Electronics 2018, 7, 207 are closed, the transfer functions of the input voltages (Vdc,1, Vdc,2) to each H-bridge6 of 16 module current are firstly derived. Then, the voltage controller should be designed to stabilize the transfer function of the voltages to the current reference, and  the detailed procedure is as follows.  (2D12 −1) IL as the TITO system as The previously mentioned current loop closed system can be considered s − 2(2D11 − 1)Vdc,2 vˆ C V   upper 2PVdc,2array voltage  =− Gvdc1d2box = of dc,1 shown in dotted Figure 4. g11 is the transfer function of the of the upper (17) ˆ LC1 d12 2D11 −1)2 (2D12 −1)2 2 + 1 (as H-bridge module, with respect to the reference current, v ̂ , and g 12 is the transfer function + s sdenoted L Cc1 C2 1 of the upper PV array voltage of the lower H-bridge module, with respect to the reference current, as 𝑣̂PI The derived transferand functions are represented (14)–(17). In Figure 4, Hvare represents wheredenoted Hi is the controller Ti1 and Ti2 are the as current loop gains that denoted as 𝑐2 .current the controller for the voltage control of the current loop closed system. Hi GiLd1 and Hi GiLd2 , respectively.

T1 vˆ

* dc,1

Hv

+

vˆ c1

g 11

+ +

vˆdc,1

g 12

g 21 * vˆdc,2

Hv

+

vˆ c2

g 22

T2

+

+

vˆdc,2

Current-loop closed system

Figure 4. Voltage control loop block diagram of current-loop closed plant system. Figure 4. Voltage control loop block diagram of current-loop closed plant system.

Similarly, g21 is the transfer function of the lower PV array voltage of the upper H-bridge module, Hi Gvas 1  T   T 1Hisi Gthe vˆdcdenoted vdc,1transfer d2 with respect to the reference current, function of the lower ,1 dc,1vˆdc1 1 , andi 2the gi22 (14) g11   PV array voltage of the lower H-bridge the reference current, denoted as vˆ c2 . vˆc1 module, with1 respect  Ti1  Tito 2 The transfer functions are derived as (18)–(21). vˆdc,1 Hi Gvdc,1d2 1  Ti1   Ti 2 Hi Gvdc,1d1 (15) g12 vˆdc,2 Hi Gvdc,2 d1 (1 + Ti2 ) − Ti1 Hi Gvdc,2 d2 g21 = (18) vˆc 2= 1  Ti1  Ti 2 vˆ c1 1 + Ti1 + Ti2 2 −dcT Hi Gvdc,22d2 (12+ D11Ti11)V vˆ dc,2 2D v12 d11  ,1i2 HiG dc,2 s   s =  LC2 vˆvˆc2 1 + TLIi1L+ Ti2 2 I L  dc,1  Gvdc1d1     ˆ 2 2 2D − 1 I ( ) C  d 11  1 L   1  1   2 D11  1s −  2 D vˆ dc,2 2(112D12 − 1)sV C112 Vdc,1    dc,1 s 2      = =−    L C1 C2 LC2    12 −1)2 dˆ11 (2D11 −1)2 (2D s s2 + L1 + C C2

g22 =

Gvdc2d1

(19) (16)

(20)

1

  2 D12  1 I L   (2D11 −1)2 dc,2 2 + (2D12 −1)sV s s + C V vˆdc,1 2  2 D11  1Vdc,2 2 dc ,2LC1 LI  L 2IL Gvdc1d 2  vˆ dc,2     2   G = − LC 2 vdc2d2 =dˆ12ˆ  2  1 2D 2−D112  C2 1 2 1 2 (2D 1 11− d12 1)11 (2D12 )2  1   s s +s Ls  C +  C2   L  1 C1 C2   



(17) (21)

Thus, the outer voltage control-loops are designed to stabilize the current-loop closed system where Hi is the PI current controller and Ti1 and Ti2 are the current loop gains that are denoted as usingHthe following loop design approach. Voltage loop T1 is first designed without the voltage loop iGiLd1 and HiGiLd2, respectively. T2 . In this condition, the transfer function of the control voltage Vc2 to DC voltage Vdc2 with the closed T1 loop can be derived as (22). In this equation, several loop gains are defined as follows:Ti1 = Hi Gi L d1 , Ti2 = Hi Gi L d2 , Tv1 = Hi Hv Gvdc,1 d1 , and Tx = − Hi 2 Hv Gvdc,1 d2 Gi L d1 .   Hi Gvdc,2 d2 (1 + Ti1 + Tv1 ) − Hi Gvdc,2 d1 Ti2 + Hi Hv Gvdc,1 d2 ˆvdc,2 = vˆ c2 T1 ,closed 1 + Ti1 + Ti2 + Tv1 + Tx + Ti2 Tv1

(22)

In this case, Hv is a voltage controller defined by (23), and DC gain and zero of the PI controller are designed so that the control loop T2 has the desired cutoff bandwidth and the phase margin. This sequential design approach can be used to achieve the control objectives and stability.

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vˆ dc,2 T2 = Hv · vˆ c2 T1 , closed

(23)

Because the system is a TITO system, the individual DC voltage control scheme has loop interaction. Thus, in order to minimize loop interaction, the inverted decoupling control scheme in Figure 5 can be employed. The objective to obtain the diagonal matrix in the series combination, between the matrix Electronics 2018, 7, xisFOR PEER REVIEW 8 of 17of the decoupling network and the matrix of the current-loop closed system [38]. In the inverted decoupling method, the off-diagonal elements are derived as (24) vand (25). ˆ dc,1

vˆc 2 g d12   12  vˆdc,1 ˆdc,1vˆ v gg11 d12 = − 12 = vˆ c2 vˆc1

g11

(24)

(24)

dc,1

vˆ c1

vˆdc,2

vˆ dc,2 vˆc1 g 21 g21  vˆ −g 22 =vˆdc,2vˆ c1 dc,2 g22 vˆc 2

d 21  

d21 =

(25)

(25)

vˆ c2

vdc,1* +

Hv

+

g 11 d 12

g 12

d 21

g 21

+

vdc,2* +

+

+

Hv

g 22

+ Decoupling network

+

+

vdc,1

+

vdc,2

Current loop closed Plant

Figure 5. Inverted oftwo-input two-input and two-output system. Figure 5. Inverteddecoupling decoupling method method of and two-output system.

3. Results

3. Results

FromFrom the the design point ofof view converter,the thesingle-phase single-phase grid-connected inverter design point viewofofthe thepower power converter, grid-connected inverter should be able to operate at universal voltages up to 240 V . If the output voltage of each H-bridge rms should be able to operate at universal voltages up to 240 Vrms . If the output voltage of each H-bridge module is Vis and Figure1,1,the the current flowing insystem the system be controlled module Vsw1 andVV sw2 in Figure current flowing in the can becan controlled by usingby theusing sw1 sw2 vector sum sum of the two in in Figure 6. Therefore, sincesince the sum of theoftwo the vector two output outputvoltages voltagesasasshown shown Figure 6. Therefore, the sum the two output voltages must be greater than the grid voltage, the sum of the voltages of the two PV arrays output voltages must be greater than the grid voltage, the sum of the voltages of the two PV arrays beto set380 to 380 V or more. theupper upper H H bridge bridge module with a 300 class power mustmust be set V or more. If Ifthe moduleisismanufactured manufactured with aV 300 V class power devices, the PV array can be designed to have a voltage of 200 V class. (5 series-configured arrays devices, the PV array can be designed to have a voltage of 200 V class. (5 series-configured ifarrays the open-circuit voltage of the individual PV modules is 40 V). Since this paper focuses on the if the open-circuit voltage of the individual PV modules is 40 V). Since this paper focuses on the controller design of cascaded H-bridge inverter, we verify the performance based on the controller design of cascaded H-bridge inverter, we verify the performance based on the experimental experimental set presented in Figure 7 and Table 1. In the experimental set, two isolated power set presented in Figure 7 and Table 1. In the PV experimental set, two isolated power supplies with series supplies with series resistors for emulating arrays are used, as shown in Figure 7. Since the output resistors for emulating PV are be used, as shown Figure 7. Since output characteristics of characteristics of each PVarrays array can controlled, the in performance of the the controller can be verified each using PV array can be controlled, the performance of the controller can be verified using the unbalanced the unbalanced PV output case shown in Figure 8. Two DCshown powerin supplies, an operating voltage range of 0–250 V and two resistors (R1 and PV output case Figurehaving 8. R 2) ofDC 14 Ω, are selected. In this condition, the voltage loop gain of of the0–250 experimental system is shown Two power supplies, having an operating voltage range V and two resistors (R1 and Figure 9. The cutoff frequency of the voltage loop gain is 30–40 andexperimental the phase margin is around R2 ) ofin14 Ω, are selected. In this condition, the voltage loop gainHz, of the system is shown 45°for analysis results the feedforward controller designed in in Figure 9. both The input cutoffconditions. frequencyThe of the voltage loopofgain is 30–40 Hz,current and the phase margin is around Section 2 are shown in Figure 10. When feedforward is applied, it can be seen that the effect of the ◦ 45 for both input conditions. The analysis results of the feedforward current controller designed in grid voltage on the grid current is further attenuated by −30 dB at the grid voltage frequency of 60 Section 2 are shown in Figure 10. When feedforward is applied, it can be seen that the effect of the grid Hz. voltage on the grid current is further attenuated by −30 dB at the grid voltage frequency of 60 Hz.

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Electronics 2018, 7, 2077, x FOR PEER REVIEW Electronics 2018,

L

8 of 16 9 of 17

iL

L

Vsw Vsw1

iL

Vsw1

Vsw1

Vg Vsw1



Vg

Vsw2

Vsw

IL

Vsw2



Vsw2

Vsw2

IL

(a)

XLIL X VLgIL Vg

(b)

(a) (b)output voltages for the unity Figure 6. AC-side equivalent circuit and the phasor diagram of H-bridge power factor. In figure, XL iscircuit the impedance of thediagram output inductor, Xoutput L = ωL. (a) AC-side Figure 6. AC-side equivalent circuit and thephasor phasor diagram of voltages for the unity Figure 6. AC-side equivalent and the ofH-bridge H-bridge output voltages forequivalent the unity power factor. In figure, XL is the impedance of the output inductor, X L = ωL. (a) AC-side equivalent circuit, (b) phasor diagram of voltages and current for the unity power factor. power factor. In figure, XL is the impedance of the output inductor, X = ωL. (a) AC-side equivalent L

circuit, (b) phasor diagram of voltages and current for the unity power factor. circuit, (b) phasor diagram of voltages and current for the unity power factor. i dc1

i in1

i dc1

i in1

R

s11

R

s11

s31

s31 L

+

+

Vin1V

C1C1

in1

i in2i in2 R

++ VV sw1 sw1

VVdc,1

dc,1

--

--

i dc2 i dc2

R

s

s1212

C2

Vin2

C2

Vg

s

32 s32

Vg

+ Vsw2 +

+

Vin2

i iL L

L

+Vdc,2 Vdc,2 -

-Vsw2

-

-

s11 s31 s12 s32

s11 s31 s12 s32 LPF LPF

LPF LPF LPF LPF LPF LPF

Advanced InCond Algorithm Advanced

InCond Algorithm Voltage Controller

PWM

PWM Current Controller Current Controller + sin

PLL

+ sin Voltage PLL Figure 7. Experimental hardware setup and Controller control block diagram of the prototype cascaded HDSP

DSP

bridge multilevel inverter system.

Figure7.7.Experimental Experimentalhardware hardware setup control block diagram the prototype cascaded HFigure setup andand control block diagram of theofprototype cascaded H-bridge Table 1. System parameters of the prototype PV system. bridge multilevel multilevel inverterinverter system. system.

Parameters Table 1. System parameters of the prototype PV system. System parameters of the prototype DCTable power1.supply Vin1 = VPV in2 =system. 0 ~ 250 V Output filter inductor L = 1mH Parameters Parameters DC-link capacitor C1 = 2200 μF, C2 = 2200 μF DC power supply Vin1 = VV in2in1==0~250 DC power supply Vin2 =V0 ~ 250 V Resistor RmH 1 = R2 = 14 Ω Output filter inductor L = 1 OutputGrid filtervoltage inductor L = 1mH Vrms DC-link capacitor C1 = 2200 µF,VCg 2==110 2200 µF DC-link capacitor C 1 = 2200 C2 = 2200 μF Switching frequency 5 kHz Resistor R1 = R2 =fsw14=μF, Ω Resistor RVrms 1 = R2 = 14 Ω Digital signal TMS320F2812 Vg = 110 Gridprocessor voltage Switching fsw = 5 V kHz Grid voltagefrequency g = 110 Vrms Digital signal processor TMS320F2812 Switching frequency fsw = 5 kHz

Digital signal processor

TMS320F2812

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1200 1200

10 of 17 9 of 16

Each H-bridge module input power versus Each DC voltage Each H-bridge module input power versus Each DC voltage

1000 1000

(a) (a)

Power(W) (W) Power

800 800

600 600

(b) (b) 400 400

200 200

0 00 0

50 50

100 100

Vdc (V) Vdc (V)

150 150

200 200

250 250

 

Figure8.8.Each Eachinput inputpower powerversus versuseach eachDC DCvoltage voltagecharacteristics. characteristics.(a) (a)emulated emulatedPV PVsystem systemwith withthe the Figure maximum 11 kW kW at at 240 maximum 714 WW at at 200V maximum 240 V V DC DC voltage, voltage,(b) (b)emulated emulatedPV PVsystem systemwith withthe the maximum 714 200DC V voltage. DC voltage.

Figure Figure9.9.Voltage Voltageloop loopgain gainbode bodediagram diagramof ofcascaded cascadedmultilevel multilevelinverter invertersystem; system;Blue Bluesolid solidline lineisisaa voltage loop-gain bode diagram of the upper H-bridge module and a green dotted line is a voltage voltage loop-gain bode diagram of the upper H-bridge module and a green dotted line is a voltage loop-gain loop-gainbode bodediagram diagramof ofthe thelower lowerH-bridge H-bridgemodule. module.

Figure Figure 11 11 shows shows the the simulation simulation results results of of the the control control performance performance for for the the designed designed voltage voltage controller in Figure 9. In order to demonstrate the validity of the voltage controller designed controller in Figure 9. In order to demonstrate the validity of the voltage controller designedwith withaa cutoff frequency of 30 Hz, we simulated whether the DC voltages of the upper and lower H-bridge cutoff frequency of 30 Hz, we simulated whether the DC voltages of the upper and lower H-bridge modules 30t) V. V. modules were were tracking tracking the the voltage voltage reference reference of of120 120++ 5sin 5sin (2π (2π×× 3t) 3t) V V and and 120 120 ++ 5sin 5sin (2π (2π × × 30t) Figure 11a shows the voltage control result when 120 + 5sin (2π × 3t) V is input as the DC link voltage Figure 11a shows the voltage control result when 120 + 5sin (2π × 3t) V is input as the DC link voltage reference upper andand lower H-bridge modules. It canItbe seen average DC voltage referenceofofthe the upper lower H-bridge modules. can bethat seenthethat the average DC follows voltage the voltage reference except 120 Hz DC voltage ripple due to the pulsating power of double frequency follows the voltage reference except 120 Hz DC voltage ripple due to the pulsating power of double of the grid of voltage frequency present in the instantaneous power of the single phasephase system [39]. frequency the grid voltage frequency present in the instantaneous power of the single system Figure 11b shows DC voltage control results of the upper and lower H-bridge modules for 120 + 5 [39]. Figure 11b shows DC voltage control results of the upper and lower H-bridge modules for sin 120 (2π × 30t) V voltage references. As in the previous case, it can be seen that the DC voltage can follow + 5 sin (2π × 30t) V voltage references. As in the previous case, it can be seen that the DC voltage can the DC input voltage on average, althoughalthough there is a there 120 Hz ripple. Figure 11cFigure is the follow the DC input command voltage command on average, is voltage a 120 Hz voltage ripple. 1-period from the result (a).result As shown bottom result, it canresult, be confirmed 11c is theenlarged 1-periodwaveform enlarged waveform fromofthe of (a). in Asthe shown in the bottom it can be that the current is controlled to be in phase with the grid voltage. confirmed that the current is controlled to be in phase with the grid voltage.

1   

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1011 of 17  of 16 Grid voltage to Grid current Bode diagram

0

Magnitude (dB) Magnitude (dB)

-20

Grid voltage to Grid current Bode diagram 0

-40 -20 -60 -40 -80 -60

-100 -80

w/o FF w/ FF

-120 -100 360

w/o FF w/FF FF w/o w/ FF

Phase (deg) Phase (deg)

-120 270 360

w/o FF w/ FF

180 270 90 180 090

-90 0 0 10 -90 0 10

10

1

10

2

1

10 Frequency (Hz) 2 10 Frequency (Hz)

10

3

10

10 3

4

10

4

Figure 10. Grid-voltage disturbance effects with and without the duty-ratio feed forward on the   condition of the output voltage of the PV is 120 V and output power is 1 kW. Figure 10. Grid-voltage disturbance effects with and without the duty-ratio feed forward Figure  10.  Grid‐voltage  disturbance  effects  with  and  without  the  duty‐ratio  feed  forward on on the the  condition of the output voltage of the PV is 120 V and output power is 1 kW. condition of the output voltage of the PV is 120 V and output power is 1 kW. 

(a)

 

DC voltages (V)

(a) 

(b) (b) Cont. Figure 11.

 

12 of 17  11 of 16 12 of 17

Grid voltage (V) & Current (A)

DC voltages (V)

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  (c)  (c) Figure 11. Simulation results for DC voltage control of the upper and lower H‐bridge modules for the  Figure 11. Simulation results for DC voltage control of the upper and lower H-bridge modules for the Figure 11. Simulation results for DC avoltage control of the(a) upper andfor lower H-bridge modules for the DC  link  voltage  reference  including  a  sinusoidal  voltage.  (a)  results  for  +  5sin(2π  ×  3t)V  voltage  DC link voltage reference including sinusoidal voltage. results 120120  + 5sin(2π × 3t) V voltage DC link voltage reference including a sinusoidal voltage. (a) results for 120 + 5sin(2π × 3t)V voltage reference, (b) results for 120 + 5sin(2π × 30t)V voltage reference, (c) 1‐period enlarged waveform of (a).  reference, (b) results for 120 + 5sin(2π × 30t) V voltage reference, (c) 1-period enlarged waveform of (a). reference, (b) results for 120 + 5sin(2π × 30t)V voltage reference, (c) 1-period enlarged waveform of (a).

ToTo  verify thethe  independent DC link control control  of the cascaded a simulation verify  independent  DC voltage link  voltage  of  the  H-bridge cascaded inverter, H‐bridge  inverter,  a  considering the voltage reference step is conducted with in Figure 7 anda To verify the independent DC change link voltage control of the theconditions cascaded shown H-bridge inverter, simulation considering the voltage reference step change is conducted with the conditions shown in  Table 1. In Figure 12, the DC link voltages two H-bridge initially controlled atinitially  120 in V. simulation considering voltage reference step change is modules conducted with the conditions shown Figure  7  and  Table  1. the In  Figure  12,  the of DC  link  voltages  of  two are H‐bridge  modules  are  After 0.5 s, the upper H-bridge module voltage reference is changed to 130 V, and the lower module Figure 7 and Table 1. In Figure 12, the DC link voltages of two H-bridge modules are initially controlled at 120 V. After 0.5 s, the upper H‐bridge module voltage reference is changed to 130 V,  reference isatchanged to 1100.5 V. Without employing themodule decoupling scheme, we can see the oscillatory controlled 120 V. After s, the upper H-bridge voltage reference is changed to 130 V, and the lower module reference is changed to 110 V. Without employing the decoupling scheme, we  voltage waveforms in light blue and light green. This oscillatory response results in a reduction in the and the lower module reference is changed to 110 V. Without employing the decoupling scheme, we can  see  the  oscillatory  voltage  waveforms  in  light  blue  and  light  green.  This  oscillatory  response  conversion increase the system However, when applied to the decoupling can see theefficiency, oscillatoryand voltage waveforms in instability. light blue and light green. This oscillatory response results in a reduction in the conversion efficiency, and increase the system instability. However, when  method, input voltages of the twoefficiency, PV arraysand canincrease be stably to their reference results inthe a reduction in the conversion thecontrolled system instability. However,value, when applied to the decoupling method, the input voltages of the two PV arrays can be stably controlled  as shown in the blue and green waveforms. applied to the decoupling method, the input voltages of the two PV arrays can be stably controlled to their reference value, as shown in the blue and green waveforms.  to their reference value, as shown in the blue and green waveforms. 160 160

150 150

140

FF VVdc1,w/o dc1,re f FF VVdc2,w/o dc2,re f Vdc1,w/o FF Vdc1,re FF f VVdc1,w/ dc1 w/o decoupling Vdc2,w/o FF Vdc2,re FF f VVdc2,w/ dc1 w/ decoupling FF VVdc1,w/ w/o decoupling dc1 ref VVdc1, dc2 w/o decoupling FF VVdc2,w/ w/ decoupling dc1 ref VVdc2, dc2 w/ decoupling ref VVdc1, decoupling dc2 w/o VVdc2, decoupling dc2 w/ ref

DC voltages (V) DC voltages (V)

140

130

130

120

120

110

110

100 100

90 0.3 90 0.3

0.4 0.4

0.5 0.5

0.6 0.6

0.7 Time (s) 0.7 Time (s)

0.8 0.8

0.9 0.9

1 1

 

Figure 12. Simulation result of the individual voltage control with respect to the step changes of the Figure 12. Simulation result of the individual voltage control with respect to the step changes of the  DC-input with (w/)ofand (w/o) inverted decoupling control method. Figure 12.reference Simulation result thewithout individual voltage control with respect to the step changes of the DC‐input reference with (w/) and without (w/o) inverted decoupling control method. 

DC-input reference with (w/) and without (w/o) inverted decoupling control method.

Figures 13 and 14 show the experimental results of an individual DC-link voltage and grid current Figures  13  and  14  show  the  experimental  results  of  an  individual  DC‐link  voltage  and  grid  control performance. Even though the two input source characteristics are different, powers Figures 13 and 14 show theEven  experimental results an individual DC-link maximum voltage grid current  control  performance.  though  the  two ofinput  source  characteristics  are and different,  current control performance. Even though the two input source characteristics are different,

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maximum powers from each input source are extracted by controlling the individual DC voltage using the proposed method. Figure 13, since voltagebyofcontrolling two input DC sources 240 V, maximum powers from eachIninput source are the extracted the power individual DCisvoltage the DC-link voltages at which maximum power is generated are 120 V. In Figure 14, because the from input source are extracted the individual DC voltage using the proposed usingeach the proposed method. In Figureby13,controlling since the voltage of two input DC power sources is 240two V, input DC supplies are 240 V and 200 V, the voltages of the maximum power are 120 V and 100 V, method. In Figure 13, since the voltage of two input DC power sources is 240 V, the DC-link voltages the DC-link voltages at which maximum power is generated are 120 V. In Figure 14, because the two respectively. In the voltage control results shown in Figures 13–15, the single-phase power injected atinput which maximum arethe 120voltages V. In Figure 14,maximum because thepower two input DCVsupplies DC supplies power are 240isVgenerated and 200 V, of the are 120 and 100are V, intoVthe the pulsating power twice the120 frequency of grid voltagepower asthe mentioned 240 andgrid 200includes V, the voltages of the maximum power V13–15, and 100 V,single-phase respectively. In voltage respectively. In voltage control results with shown inare Figures thethe injected in reference However, it can13–15, be confirmed by the designed controller that the average voltage control shown in Figures thewith single-phase power injected the grid includes the into theresults grid [39]. includes the pulsating power twice the frequency of theinto grid voltage as mentioned follows the voltage reference. In addition, the inverter output voltage of the cascaded H-bridge pulsating power twice the frequency of the grid as mentioned in reference [39]. However, in reference [39].with However, it can be confirmed by voltage the designed controller that the average voltage modules exhibits a five-level stair-case waveform. The grid current of Figure 15, which is the enlarged itfollows can be confirmed by the designed controller that the average voltage follows the voltage reference. the voltage reference. In addition, the inverter output voltage of the cascaded H-bridge waveform of 13,output is controlled phase withThe the gridcurrent voltage, the 15, summed power is stably In addition, theFigure. inverter voltagein ofwaveform. the cascaded H-bridge modules exhibits a five-level modules exhibits a five-level stair-case grid ofand Figure which is thestair-case enlarged transferred to the utility grid. waveform. grid current of Figure 15, whichwith is thethe enlarged waveform 13, is controlled in waveform The of Figure. 13, is controlled in phase grid voltage, and of theFigure summed power is stably phase with the gridutility voltage, and the summed power is stably transferred to the utility grid. transferred to the grid.

Figure 13. Experimental results of DC link voltage and grid current control when the MPP voltage of upper 13. H-bridge moduleresults and lower H-bridge module 120 V respectively. Figure 13.Experimental Experimental results ofDC DC linkvoltage voltage andare grid current controlwhen whenthe theMPP MPPvoltage voltageof of Figure of link and grid current control upper upperH-bridge H-bridgemodule moduleand andlower lowerH-bridge H-bridgemodule moduleare are120 120VVrespectively. respectively.

Figure Figure14. 14.Experimental Experimentalresults resultsof ofDC DClink linkvoltage voltageand andgrid gridcurrent currentcontrol controlwhen whenthe theMPP MPPvoltage voltageofof upper module H-bridge module are 120 and VVrespectively. upperH-bridge H-bridge moduleand andlower lower H-bridge module 120current and100 100 respectively. Figure 14. Experimental results of DC link voltage andare grid control when the MPP voltage of upper H-bridge module and lower H-bridge module are 120 and 100 V respectively.

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Figure 15. Enlarged experimental results of Figure 13. Figure Figure15. 15.Enlarged Enlargedexperimental experimentalresults resultsofofFigure Figure13. 13.

In this work, the DC voltage references are independently obtained from an advanced incremental In In this this work, work, the the DC DC voltage voltage references references are are independently independently obtained obtained from from an an advanced advanced conductance MPPT algorithm [40]. The algorithm flow-chart of the MPPT is shown in Figure 16. incremental conductance MPPT algorithm [40]. The algorithm flow-chart of the MPPT is shown incremental conductance MPPT algorithm [40]. The algorithm flow-chart of the MPPT is showninin The variable DC step size is defined as (26) and is determined using the relationship of the incremental Figure Figure16. 16.The Thevariable variableDC DCstep stepsize sizeisisdefined definedas as(26) (26)and andisisdetermined determinedusing usingthe therelationship relationshipofofthe the and instantaneous resistance of the PV arrays. The update period of theperiod MPPTof algorithm is set to 2 s incremental and instantaneous resistance of the PV arrays. The update the incremental and instantaneous resistance of the PV arrays. The update period of theMPPT MPPTalgorithm algorithm and the maximum step size for step changingfor the voltage references is 5 V. isisset settoto22ssand andthe themaximum maximum stepsize size forchanging changingthe thevoltage voltagereferences referencesisis55V. V. V  dI V Vdc,·i dI dI RR ii dc,i i = 1  11 dc,i 1,1, Mi M = + + Ri ii , ,ii i= (26) (26) Mi 1i  1 1,222 (26) Iin,i · dV r,s,i Iin  dV r dc,i dc,i sr i Iin,i,i  dV dc,i s,i Sense Vsa(k), Isa(k) Sense Vsa(k), Isa(k) dV = Vsa(k) − Vsa(k-1) dV = Vsa(k) − Vsa(k-1) dI = Isa(k) − Isa(k-1) dI = Isa(k) − Isa(k-1)

Vsak  dI Vsak  dI M 1  M 1  Isa k  dV Isa k  dV

M Mmax M Mmax

Yes Yes |M| < Mmin |M| < Mmin

No No

|M| > Mmin |M| > Mmin

No No

Vsa(k+1)* = Vsa(k) + M Vsa(k+1)* = Vsa(k) + M Vsa(k-1) = Vsa(k) Vsa(k-1) = Vsa(k) Isa(k-1) = Isa(k) Isa(k-1) = Isa(k)

Yes Yes M Mmin M Mmin

Figure 16. Algorithm flow-chart ofof the advanced incremental conductance method. Figure 16. Algorithm flow-chart of the advanced incremental conductance method. Figure 16. Algorithm flow-chart the advanced incremental conductance method.

Figure 17 shows the MPPT performance. Initially, because the power conversion system (PCS) Figure shows MPPT performance. Figure17 17 showsthe the MPPT performance.Initially, Initially,because becausethe thepower powerconversion conversionsystem system(PCS) (PCS) does not work, the output DC voltages of the PV arrays are 240 V. After starting the operation, does not work, the output DC voltages of the PV arrays are 240 V. After starting the operation, does not work, the output DC voltages of the PV arrays are 240 V. After starting the operation,both both output DC ofofthe are controlled tototheir maximum power points. Further, the both output DC voltages of PV the PV arrays controlled to their maximum power points. Further, output DCvoltages voltages the PVarrays arrays areare controlled their maximum power points. Further, the generated power of the PV arrays is transferred to the utility grid as shown in the red waveform. the generated power of the PV arrays is transferred to the utility grid as shown in the red waveform. generated power of the PV arrays is transferred to the utility grid as shown in the red waveform.

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of 17 14 15 of 16

Vdc,2 (50V/div)

Vdc,1 (50V/div) IL (20A/div)

Vg (100V/div)

10s/div Figure Experimental results maximum power point tracking. Figure 17.17. Experimental results forfor maximum power point tracking.

4. 4.Conclusions Conclusions InIn this paper, thethe modeling andand controller design methods for individual MPPT MPPT of the single-phase this paper, modeling controller design methods for individual of the singlecascaded H-bridge multilevel PV inverter are proposed. The small signal transfer functions are derived phase cascaded H-bridge multilevel PV inverter are proposed. The small signal transfer functions are through the small-signal modeling approach. For the unity power factor, a PI current controller with a derived through the small-signal modeling approach. For the unity power factor, a PI current duty ratio feed-forward compensation method is employed. In order to achieve the individual MPPT controller with a duty ratio feed-forward compensation method is employed. In order to achieve the ofindividual the PV arrays, each link voltage is designed to stabilize currenttoloop closed MPPT of of thethe PVDC arrays, each of loops the DC link voltage loops is the designed stabilize the system. Especially, in order to avoid loop interaction in the current loop closed system, the voltage current loop closed system. Especially, in order to avoid loop interaction in the current loop closed controller design withcontroller the inverted decoupling proposed. The inverted decoupling system, the voltage design with themethod invertedisdecoupling method is proposed. Themethod inverted todecoupling minimize the loop interaction of the has been verified the simulation butbythe method to minimize theTITO loopsystem interaction of the TITO by system has been result, verified the experimental performance will be done through the future work. The proposed control methods of simulation result, but the experimental performance will be done through the future work. The the cascadedcontrol H-bridge multilevel inverterH-bridge are validated through simulation and experimental proposed methods of thePV cascaded multilevel PV the inverter are validated through the results on the 2-kW prototype system. simulation and experimental results on the 2-kW prototype system. Author Contributions: S.L. contributed to the main idea of this article, and wrote the paper. S.L. and J.K. Author Contributions: to thecritically. main idea of this article, and the paper. and J.K. performed the experiments.S.L. J.K.contributed revised the paper All authors approved thewrote final version to beS.L. published. performed the experiments. J.K. revised the paper critically. All authors approved the final version to be Acknowledgments: This research was supported by Program through the National Research Foundation of published. Korea (NRF) funded by the Ministry of Science and ICT (NO.NRF-2017M1A3A3A06016680, Cubesat Contest and Development) and funded the Hanwha Land Systems. Acknowledgments: Thisby research was supported by Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (NO.NRF-2017M1A3A3A06016680, Cubesat Contest Conflicts of Interest: The authors declare no conflict of interest. and Development) and funded by the Hanwha Land Systems.

References Conflicts of Interest: The authors declare no conflict of interest. 1.

Rodriguez, J.; Lai, J.-S.; Peng, F.Z. Multilevel inverters: A survey of topologies, controls, and applications. IEEE Trans. Ind. Electron. 2002, 49, 724–738. [CrossRef] Lai, J.-S.; Peng, newinverters: breed of A power converters. IEEE controls, Trans. Ind. App. 1996, 32, Rodriguez, J.;F.Z. Lai,Multilevel J.-S.; Peng,converters-A F.Z. Multilevel survey of topologies, and applications. 509–517. [CrossRef] IEEE Trans. Ind. Electron. 2002, 49, 724–738, doi:10.1109/TIE.2002.801052. Selvaraj, J.; Peng, Rahim, N.A. Multilevel inverter fornew grid-connected PVconverters. system employing digital controller. Lai, J.-S.; F.Z. Multilevel converters-A breed of power IEEE Trans. Ind.PIApp. 1996, 32, IEEE Trans. Ind. Electron. 2009, 56, 149–158. [CrossRef] 509–517, doi:10.1109/28.502161. Vilanueva, E.;Rahim, Correa,N.A. P.; Rodriguez, Pacas,for M. grid-connected Control of a single-phase H-bridge multilevel Selvaraj, J.; Multilevel J.; inverter PV systemcascaded employing digital PI controller. inverter for grid-connected photovoltaic systems. IEEE Trans. Ind. Electron. 2009, 56, 4399–4406. [CrossRef] IEEE Trans. Ind. Electron. 2009, 56, 149–158, doi:10.1109/TIE.2008.928116. Zabihinejad, Mass minimization sensitivity of highcascaded power modular multilevel Vilanueva, A.; E., Viarouge, Correa, P.;P.Rodriguez, J.; Pacas, and M. Control of aanalysis single-phase H-bridge multilevel converter. Int. J. Electr. Power Energy Syst. 2017, 93, 328–339. [CrossRef] inverter for grid-connected photovoltaic systems. IEEE Trans. Ind. Electron. 2009, 56, 4399–4406,

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