Phase-Locked Loops using State Variable Feedback for Single-Phase ...

Phase-Locked Loops using State Variable Feedback for Single-Phase Converter Systems Timothy Thacker, Ruxi Wang, Dong Dong, Rolando Burgos, Fred Wang, Dushan Boroyevich Center for Power Electronics Systems (CPES) The Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA Abstract— A crucial component of a grid-connected converter system is the Phase-Locked Loop (PLL) that synchronizes the control to the grid voltage. Accurate, fast responding PLLs are required to provide phase angle and frequency measurements of the grid voltage for control and protection purposes. This paper proposes novel feedback mechanisms using the estimated frequency and phase in single-phase PLLs (in the stationary and rotating reference frames) which enhances performance. The estimated frequency ripple is eliminated without using low-pass filters (LPFs), and feedback terms are shown to improve the synchronization speed, by as much as 80% in some cases. Mathematical analyses, simulation, and hardware results are presented to verify the methods. 1

Index Terms— Converter Control, Frequency Control, Phase Control, Phase-Locked Loops (PLL), Single Phase Control, Synchronous Frame (DQ) Control.

I. INTRODUCTION grid connected systems, a critical component of the INconverter’s control system is the phase-locked loop (PLL)

that generates the grid voltage’s frequency and phase angle for the control to synchronize the output to [1-6]. Estimated frequency, ωe, and phase angle, θe, of the grid voltage by the PLL can be used not only for control and signal generation, through synthesis or transformations, but also in protection to detect when the converter has entered an islanded mode. Distortions and transients upon the grid, such as harmonics, frequency variations and phase shifts often occur in the grid voltage. A control system’s PLL operating based on this grid voltage measurement must be designed to be able to phaselock quickly, accurately and produce low distortion outputs under all imaginable grid conditions [1, 5, 7-9]. As such, PLL systems that can synchronize to these grid parameters accurately and as quickly as possible are of vital importance; otherwise, inaccurate and potentially harmful control of power factor angle, harmonics, and the determination of system mode of operation can result [10-12]. Stationary frame PLLs are useful in single-phase (1Φ) applications due to the lack of multiple signals to synchronize with, and for their increased synchronization speeds over other methods. Typical systems employ a sinusoidal multiplier phase detector (PD) that generates an error voltage, Verr, for the loop filter (LF); which in turn generates ωe. An issue with this type of PD is that it inherently generates a 2ω ripple term in Verr that propagates through the LF [13-16]. “This work made use of ERC shared facilities supported by the National Science Foundation under Award number EEC-9731677.” This was work was made possible under fellowship grants made by VPT, Inc., Blacksburg, Va.

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Past methods to minimize this effect have focused on adding filters, namely low-pass filters (LPFs), to the loop that attenuate this 2ω term [3, 11, 14, 17, 18]. These solutions generally cause the LF’s bandwidth and/or phase-margin to decrease, resulting in slower transient response times to input disturbances and slower overall synchronization speeds. Synchronous frame (DQ) PLLs can be extremely useful in control systems. These PLLs not only generate frequency and angle estimations, but transform the grid voltage into DC signals as well; which is advantageous due to that DQ control can produce zero steady-state errors of the output with simple PI regulators, whereas in the stationary frame, PI regulators cannot. An issue with DQ PLLs in 1Φ systems is that there is only one signal to use; an orthogonal signal from the input must therefore be created to transform the system from the stationary to the DQ frame. Creating such a signal, however, is not a simple task. Methods to produce this signal include static time/phasedelay filters which can cause inaccuracies to occur due to the slow varying nature of the grid within tolerable ranges [1, 3, 11], while differentiation of the input signal amplifies noise [19, 20]. Other methods, such as the second-order generalized integrator (SOGI) [1] and Inverse Park’s transform [11, 21, 22], generate accurate orthogonal signals and attenuated higher order harmonic terms; which is desirable for ω and θ estimation. For DQ control though, the DQ terms should not be attenuated; control should regulate see them un-attenuated. This paper presents novel feedback methods for a 1Φ, stationary frame PLL, and shows how these additional state feedback terms improve synchronization speeds, increase robustness due to input noise and disturbances, and produce accurate and non-distorted values of ωe and θe for the control system over a wide-range of conditions. The method eliminates the 2ω ripple without using LPFs and dynamically changes the bandwidth, to produce faster synchronization times of the LF depending upon system conditions inherently. This paper also presents a novel method for generating the orthogonal component of a 1Φ, DQ PLL. The method dynamically generates the orthogonal component, similar to the SOGI method, to obtain accurate results, but does not attenuate or degrade any signal information of the DQ signals that the control should see and regulate. Mathematical analysis and simulations show the performance responses of the stationary and DQ PLLs; hardware implementation of the stationary method was implemented and verified as well.

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II. STATIONARY FRAME PLL The block diagram in Fig. 1 shows the components of a digitally implemented PLL: PD, LF and a digitally controlled oscillator (DCO). Implementing a standard sinusoidal multiplier as the PD, as seen, the error voltage is seen to contain a 2ω ripple. Verr = A sin (ωi t ) cos(ωet ) =

A [sin ((ωi + ωe )t ) + sin ((ωi − ωe )t )] 2

(1)

due to the fact that this PLL PD requires a sinusoid of unity gain; therefore the measured input is divided by the nominal peak value of the line voltage and converted to a per-unit system. Since the grid voltage consistently varies within a nominal range, the input to the PLL will have some error due to this mismatch. The effect of this mismatch is seen in (2), where ψ is the angle mismatch between the PLL estimation and the actual value; as such no matter the state of the PLL, there will always be a 2ω ripple present in the error voltage. Verr =

1 1 A sin (2θ + ψ ) + sin (ψ ) 2 2

(2)

In steady-state, from (1), as ωe tracks the input frequency, ωi, the 2ω ripple term appears, seen in waveform of Fig. 3. The amplitude mismatch term, A, in (1) appears in the system

As mentioned previous, a common way to reduce the 2ω term is to place LPFs before the LF to attenuate the ripple.

Fig. 1: PLL Components and Structure for a sinusoidal multiplier PD.

Fig. 2: Modified PD for PLL.

2ω e in Multiplier PD not seen in Modified PD

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Multiplier PD Modified PD 60.4

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Frequency, (Hz)

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Fig. 3: Simulated steady-state of PD Multiplier and Modified PDs.

Fig. 4: 90° step disturbance for multiplier w/ and w/o LPFs.

Fig. 5: Hardware results of O-PD & M-PD PLL for 90° step (6.5 Hz peak response, 2ω ripple in O-PD = 1.2 Hz peak).

Fig. 6: Hardware results of O-PD & M-PD PLL for 2 Hz step (from 60 to 62 Hz, 2ω ripple in O-PD = 1.2 Hz peak).

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The results of adding a 1st order or 2nd order LPF to the loop is seen in Fig. 4. Depending upon the type and order of the filter, this method is seen to reduce the ripple effect, but at the cost of resynchronization speed of the PLL. The proposed method utilizes a trigonometric function with θe, seen in Fig. 2 and described by (3); instead of a filter to attenuate the 2ω ripple in steady-state, this method essentially forces Verr to zero during phase-lock conditions. Expanded out, (4) is obtained; if A ≈ 1, then (5) shows that zero steadystate error occurs and the 2ω term is only present during synchronization transients (ψ ≠ 0). Verr = A sin (ω i t ) cos(ω e t ) − sin (ω e t ) cos(ω e t ) Verr =

A sin (ψ ) + sin (2θ + χ ) 2

⎛ A2 + 1 ⎞ ⎛ A ⎞ ⎜ ⎟− cos(ψ )⎟ ⎜ 4 ⎟ ⎜⎝ 2 ⎠ ⎝ ⎠

⎛ A sin (ψ ) ⎞ χ = tan −1 ⎜⎜ ⎟⎟ ⎝ ( A cos (ψ )−1) ⎠

(3)

(4)

Verr =

sin (ψ ) ⎛ψ ⎞ + sin (2θ + χ )sin⎜ ⎟ 2 ⎝2⎠

This method allows for complete elimination of the ripple term during phase-lock, instead of just attenuation; simulation results in Fig. 3 show this effect. The hardware results in Fig. 5 and Fig. 6 show the responses to 90° and 2 Hz steps, respectively, in the AC voltage. The results seen in Fig. 7 – Fig. 9 show the close up steady-state waveforms of the two methods of PD implementation. It is seen that under nominal conditions, the Original PD (O-PD) has a steady-state ripple of approximately 1.2 Hz, while the Modified PD (M-PD) has no ripple; under amplitude mismatch, A ≈ 1.1, the O-PD can be seen to have about the same ripple, while the M-PD now produces a small 2ω term according to (4). To test the PLL under input line distortions, the nominal amplitude and frequency are produced for a 70% clipped sinusoid (22.9% THDv), and the PLL with the M-PD is seen to track the nominal frequency with only slight distortions.

Fig. 7: O-PD & M-PD during phase-lock of A = 1 (2ω ripple in O-PD = 1.2 Hz peak).

Fig. 8: O-PD & M-PD during phase-lock of A = 1.1 (2ω ripple in O-PD = 1.2 Hz peak, in M-PD = 0.14 Hz peak).

Fig. 9: O-PD & M-PD during phase-lock of THDv = 22.9% (2ω ripple in M-PD = 0.62 Hz peak).

Fig. 10: M-PD w/ FFB term implemented.

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The M-PD PLL works well to eliminate/reduce ripple effects during phase-lock conditions, while keeping the same basic response time of the O-PD system. To improve upon this, and cause the system to have good noise rejection during phase-lock, but faster synchronization speeds for transients, a frequency feedback (FFB) term is added to the M-PD. The M-PD w/ FFB, shown implemented in Fig. 10, allows for this by using a scaled value of the frequency and multiplying it with the output of the M-PD to adjust the gain of the LF dynamically. This works through the fact that during phase-lock, the output of the M-PD is essentially zero; therefore any multiplier term is negated, but when the PLL is out of phase-lock, the output of the M-PD is non-zero, and is amplified by the FFB term. The effective LF gain is therefore increased, which increases the bandwidth of the PLL and increases the synchronization speed. Simulations in Fig. 11 show the effect on synchronization speed for the M-PD w/ FFB compared to the M-PD. It is seen that up to an 80% reduction in synchronization time can be achieved with FFB. The drawback to this additional feedback term is that now any amplitude error, A ≠ 1, will be increased by the feedback multiplication, seen in (6) and in Fig. 12.

Verr = K FFB ⋅ ω e ⋅

A sin (ψ ) 2

⎛ A2 + 1 ⎞ ⎛ A ⎟ − ⎜ cos(ψ )⎞⎟ + K FFB ⋅ ωe ⋅ sin (2θ + χ ) ⎜ ⎜ 4 ⎟ ⎝2 ⎠ ⎝ ⎠

To correct for this effect, an Amplitude Error Correction (AEC) circuit is implemented before the FFB multiplication, as seen in Fig. 13 and described by (7). The all-pass filter (APF) transfer function seen in (8), produces a 180° phase shift of the integrated M-PD output (for KAEC = 0.1), which is then summed with the non-shifted signal. This forces a cancellation term to propagate through the feedback system and cancel any effect that A has on the PLL. AEC =

Verr

1 = K FFB ⋅ ω e ⋅ ⋅ (1 + APF) Vo, M − PD s

(7)

s − K AEC ωe s + K AEC ωe

(8)

APF = −

Results seen in Fig. 14 show how this AEC circuit can eliminate the effects of A upon the PLL system without sacrificing synchronization speeds.

Fig. 11: M-PD vs M-PD w/ FFB.

Fig. 12: M-PD vs M-PD w/ FFB at A = 1.01.

Fig. 13: M-PD w/ AEC feedback circuit added.

Fig. 14: M-PD w/ FFB vs M-PD w/ AEC at A = 1.01.

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III. SYNCHRONOUS FRAME (DQ) PLL

APF =

Synchronous Frame PLL’s are also a common type of PLL found in 1Φ implementations. The DQ transform, (9), itself acts as the PD for the PLL, while the LF and DCO remain the same as in the stationary case. ⎡ X d ⎤ ⎡ cos(θ e ) sin (θ e )⎤ ⎡ X α ⎤ ⎢X ⎥ = ⎢ ⎥ ⎥⎢ ⎣ q ⎦ ⎣− sin (θ e ) cos(θ e )⎦ ⎣ X β ⎦

s − ωe β =− α s + ωe

ωe −1 β = s α 1 + ωe

(10)

(11)

s

⎛

β ⋅ ⎜1 +

(9)

⎝

X ∈[V , i ]

As mentioned previously, an issue with DQ PLLs is in the accurate generation of the orthogonal component, which affects not only the PLL frequency and phase angle estimation, but also the corresponding DQ voltages that the control system uses to regulate the converter’s output. Systems such as those in [11, 21, 22], use an Inverse Park’s transform to generate the voltage orthogonal component, as such, the DQ currents cannot be generated and a mixed reference frame control is needed. This method can be shown to be equivalent to the M-PD case in the stationary frame (see Appendix), but in practical implementation, needs LPFs to help generate the desired ωe and θe values, thus reducing synchronization speeds and degrading performance. The SOGI method uses a similar technique to the dynamic APF created in the proposed method, but generates and deals only with the fundamental components of the input signal; it attenuates higher order terms, thus filtering out information in the DQ voltages/currents that the control should regulate.

ωe ⎞

⎛ω ⎞ ⎟ = α ⋅ ⎜ e − 1⎟ s ⎠ ⎝ s ⎠

(12)

ω ⎛ ωe ⎞ − 1⎟ − β ⋅ e s ⎝ s ⎠

(13)

β = α ⋅⎜

The proposed method uses the previously presented APF to produce an orthogonal signal from the input voltage to use in the transformation. This APF is dynamically created with feedback from the PLL frequency to ensure that a 90° shift is maintained as closely as possible (from (8), KAEC = 1 for this case). This will in turn force the system to track the voltage faster and more accurately than in other implementations. The implementation for the APF can be derived in (10) – (13), and seen in the block diagram of Fig. 15. The DQ PLL implementation can be seen in Fig. 16. This implementation of the orthogonal component generation is advantageous over other methods because it can be used not only for the voltage, but also for the current as well; and without filtering any information out from the DQ signals for the control to regulate.

Fig. 15: APF/Orthogonal Generation Block Diagram.

Fig. 16: DQ PLL Implementation.

Fig. 17: Inverse Park’s Response for 90° step.

Fig. 18: Inverse Park’s Response for 90° step w/ 20% 3rd Harmonic.

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The results in Fig. 17 and Fig. 18 show the responses from a 90° step for the Inverse Park’s case for an ideal and a 20%, 3rd harmonic voltage, respectively. Seen is that the ideal voltage

produces clean DQ components, but the settling time is not as fast as other methods; for the 20% harmonic case, the signal is filtered from the LPFs added to make this transform work.

Fig. 19: SOGI Response for 90° step.

Fig. 20: SOGI Response for 90° step w/ 20% 3rd Harmonic

rd α,β Voltages for SOGI w/ 3 Harmonic

200

V V V

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Fig. 21: SOGI αβ Response for 90° step w/ 20% 3rd Harmonic.

Fig. 22: Proposed APF Response for 90° step. rd α,β Voltages for APF w/ 3 Harmonic

250

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Fig. 23: Proposed APF Response for 90° step w/ 20% 3 Harmonic.

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Fig. 24: Proposed APF αβ Response for 90° step w/ 20% 3 Harmonic

rd

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Seen in Fig. 19 and Fig. 20 are the responses to a 90° step in the voltage, ideal and harmonic cases respectively, for the SOGI method. The DQ components are generated and the frequency response has good synchronization speed; for the 20% harmonic case, the orthogonal signal is filtered, Fig. 21. In Fig. 22 and Fig. 23, the proposed method for both the ideal and harmonic cases are seen; generation of the DQ components and the frequency response are nearly identical to the SOGI case, but in Fig. 24, it is seen that none of the harmonics have been filtered, and the DQ components retain the original system information for the controller to regulate. In the SOGI and proposed methods, LPFs are needed to attenuate the ωe ripple for use in other control functions. IV. CONCLUSIONS

ACKNOWLEDGMENTS The authors would like to thank Bill Giewont and Vacon for their generous donation of hardware for the experimental results and their time and help with its modifications. APPENDIX A modification to the inverse of (9) is found in (14). The orthogonal component of the voltage is that of (15). Ideally, Vq = 0 and Vd = Vpk (peak AC voltage). Plugging (15) into (16), the variation from (3) is Vpk in the difference terms, (17).

Vq = V pk sin(ωi t )cos(ωet ) − Vβ sin(ωet )

Vq = V pk [sin (ωi t )cos(ωet ) − cos(ωe t )sin (ωet )] Verr = A ⋅ sin (ωi t )cos(ωe t ) − cos(ωe t )sin (ωe t )

[2]

[6]

[8]

[9]

[10] [11]

[12] [13]

[14] [15] [16] [17]

[18] [19] (15) (16)

[20] (17)

[21]

M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, "A New Single-Phase PLL Structure Based on Second Order Generalized Integrator," in Power Electronics Specialists Conference, 2006. PESC '06. 37th IEEE, 2006, pp. 1-6. A. Timbus, M. Liserre, R. Teodorescu, and F. Blaabjerg, "Synchronization Methods for Three Phase Distributed Power

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This paper presented novel methods of PD implementation for stationary and DQ based 1Φ PLLs. The stationary method was shown in simulation and hardware to eliminate the 2ω ripple effects in steady-state, and reduce the ripple due to amplitude mismatch at the input. Further improvements to increase synchronization speeds and correct for amplitude mismatches are shown in simulation, and is seen that synchronization speeds can be improved by as much as 80% with the proposed method. Amplitude mismatch errors are eliminated completely and all done without having to use LPFs which can greatly slow the response time of the PLL. In the DQ PLL, the orthogonal component generation through a dynamic APF was shown to have improved and/or equal performance to other methods, but with the added benefit of not filtering harmonics of the input; preserving signal quality during the transform and synchronization for control use.

⎡ X α ⎤ ⎡ sin (θ e ) cos(θ e ) ⎤ ⎡ X d ⎤ ⎥ ⎢X ⎥ = ⎢ ⎥⎢ ⎣ β ⎦ ⎣cos(θ e ) − sin (θ e )⎦ ⎣ X q ⎦ Vβ = Vd cos(θ e ) − Vq sin(θ e ) ≈ V pk cos(ωet )

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