Power and Timing Driven Physical Design

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Full Custom ... input parameters for the physical design tool set. The redesign of a circuit with a different set of design rules should be done by just changing the.
Power and Timing Driven Physical Design Automation Ricardo Reis

Universidade Federal do Rio Grande do Sul Instituto de Informática - Porto Alegre - RS - Brasil e-mail: [email protected] 1

OUTLINE 1. Introduction 2. History 3. Standard Cell 4. CMOS Complex Gates 5. Layout Synthesis 6. Layout Strategies 7. Design Flow 8. Conclusions

2

Introduction • VLSI

CAD

• Layout for

- Low Power - High Performance

• CAD System



- New Methodology - Low Power - High Performance - Library free 3

History Years 70 : microprocessors “hand made” computer used just as graphical input End Years 70: Random Logic Z8000 Years 90:



ROMs, PLAs

Next Step: Standard Cell





ROMs, PLAs M68000



Standard Cell 486, Pentium Random Logic Automatic Layout Cells-on-the-fly

4

MC6809

5

Full Custom

GND

VCC

GND

VCC

Zilog Z8000

detail of the control part using random logic

6

Full Custom

VCC

Strip Structure

GND

Detail of the control part of TMS7000 implemented with random logic

7

History Years 70 : microprocessors “hand made”

computer used just as graphical input

End Years 70: Random Logic Z8000 Years 90:

ROMs, PLAs

Next Step:

Standard Cell

























ROMs, PLAs



M68000

Standard Cell



486, Pentium

Random Logic Automatic Synthesis

8

Standard Cell Approach

Is it a layout automated approach ?

NO ! 9

Standard Cell Approach Cell characterization Cell performance predictability

10

Standard Cell Approach Logic Options Limited to Cells Available in the Library No optimal logic minimization Cells oversized Area 11

12

Standard Cell Approach

X

Cell On-the-fly Approach 13

Change of

Paradigm 14

Cell

Generation

on-the-fly

15

The goal is to have a set of layout synthesis tools addressing the following:

1

Each cell should be generated on-the-fly, considering the specific needs of the circuit environment where it is going to be placed.

2

Reduction of the amount of transistors by the use of complex gates (SCCG) combinations. The advantages of using SCCG gates are area, delay and power reduction (when comparing with standard-cell approach).

3

Each transistor should be sized to a good compromise between power and delay, considering the environment where it will be placed. 16

4

Routing minimization by the reduction of the connections average length and minimization of the connections lengths over the critical paths.

5 6 7

The performance of a circuit should be evaluated with a good accurance before its generation; The area and shape of a circuit must be evaluated before the generation of each functional block. Technology independence. All design rules are input parameters for the physical design tool set. The redesign of a circuit with a different set of design rules should be done by just changing the technology parameter description file and by running again the layout synthesis tool. 17

Nanotechnologies • CMOS technologies: - transistors with channel length with less then 0.1 micron. - more than 5 metal layers with stacked vias e contacts.

Interconnection delay

gate delay

• Increasing influence of routing in circuit performance • These evolutions requires new CAD tools

• Placement and routing tools increase their role and importance in the reduction of wirelenght. 18

challenge To develop a CAD system for the automatic physical design of integrated circuits tuned for the requirements of submicron technologies:

smaller area (wirelenght reduction) (wirelenght reduction) smaller delay less power consumption 19

To attain these requirements: it is necessary to reduce the average wirelength the amount of transistors It is also requested to generate logic gates that fit well in its layout environment, with the help of a specific transistor sizing tool.

Layout Automatic Generator It is needed tools target for layout generation on the fly, avoiding the limitations of the use of cell libraries that are restricted to some logic combinations and dimensioning. 20

But nowadays cell predictability is not anymore sufficient to have circuit predictability

Connections becomes the central problem ! 21

Connections becomes the central problem ! Predictability of connections: connections are random Challenges: how to predict connections ? how to reduce wirelength?

22

Challenges: how to predict connections ? -search for layout regularity -estimation tools -connections first, transistors later 23

Challenges: how to reduce wirelength? - area reduction - use of complex gates (SCCG) - improvement of routing and placement algorithms 24

Using Static CMOS Complex Gates (SCCG) with cell generation on-the-fly

It is possible do to an extreme logic minimization

Freedom to Logic Designers !!!!

25

Automatic Layout Synthesis Using Complex Gates (SCCG) NUMBER OF SERIAL PMOS TRANSISTORS

1 NUMBER OF SERIAL NMOS TRANSISTORS

2

3

4

5

1

1

2

3

4

5

2

2

7

18

42

90

3

3

18

87

396

1677

4

4

42

396

3503

28435

5

5

90

1677

28435

125803

26

Power Reduction Ileakage is become important in submicron circuits.

It is function of the number of transistors 27

Routing the solutions produced by academic and industrial tools are in average within 1.43 to 2.38 times the optimal solutions considering wirelength C-C. Chang, J. Cong, M. Xie. “Optimality and Scalability of Existing Placement Algorithms”. ASPDAC 2003

28

FOTC Routing FOTC approach (Full-Over-The-Cell Routing)

All conections are over the active zones 29

Layout

Strategies 30

Layout Strategies - transistor topologies - management of routing in all layers - VCC and Ground distribution - clock distribution - contacts and vias management - body ties management - transistor sizing and folding 31

Layout Strategies Transistor topologies - horizontal - vertical - doglegs (different directions) - folding 32

33

Layout Strategies Routing Management - priority tracks schema - routing layers priority - routing layers directions

34

Layout Strategies VCC and Ground Distribution - borders of the strip - middle of strips (between P and N diffusions)

- over the transistors Layer (metal 1, metal 2,...) 35

Power Lines over the transistors

TROPIC3 36

Power Lines between P and N plans Aligned pins with jog in polysilicon. Transistor not aligned Not aligned pin

Optimized Jog in polysilicon wire

P diffusion vcc (metal2) Connetion between N and P plan in metal1

gnd (metal2) N diffusion

Metal1 to connect supply line Over-the-cell routing

TROPIC3 37

Power Lines at the Strip Borders

Parrot1 38

Layout Strategies

- contacts and vias management - body ties management 39

Layout Strategies

contacts and vias management (towers of vias) 40

Physical Design Flow 41

Option 1 Logic Netlist

Partitioning and Placement Cell Generation Routing

Circuit Layout 42

Option 2 Logic Netlist

Partitioning and Placement Routing Cell Generation

Circuit Layout 43

Logic Netlist

Partitioning and Placement Routing Cell Generation

Automatic Characterization Timing Power

Circuit Layout

44

Challenge: Good Models Automatic Characterization Timing Power

45

PARROT PHYSICAL SYNTHESIS Partitioning

Apple Parrot

Placement

Mango Parrot

Cell Generation

Parrot Punch

Routing

Option 1

46

PARROT PHYSICAL SYNTHESIS Partitioning

Apple Parrot

Placement

Mango Parrot

Routing Cell Generation

Parrot Punch

Option 2

47

Mango Parrot

Placement Tool: First Step: Constructive Algorithm Plic-Plac Second Step: Interactive Algorithm Simulated Annealing with Multiple Perturbations Functions



(ISCAS2003) 48

Layout Generation Flow Circuit Placement

Specifications

Design Rules

Transistor Placement Layout Generation Routing

Layout

Wirelength Placement with wirelength reduction

50

Congestion Congestion is an important problem because it can forbid a complete routing

Routability 51

Plic-Plac

DFS (Depth First Search) BFS (Breadth First Search) 52

Compromise: Routability and Wirelength Reduction 53

Parrot Layout Style

Practical Experiments Comparison between Parrot Punch and TROPIC3 (VLSI’97)

TROPIC3

PARROT PUNCH

C432 TROPIC

PARROT

804 transistors Delay: -26.6 % Area: -41.3 %

C499 TROPIC

PARROT

1556 transistors Delay: - 26.0 % Area: - 37.3 %

C880 TROPIC

PARROT

1802 transistors Delay: -22.0 % Area: -37.5 %

C1355 TROPIC

PARROT

2308 transistors Delay: -21.1 % Area: -33.2 %

Parrot Punch vs TROPIC3

Conclusions Cell generated on-the-fly target to their environment Area reduction Reduction on the number of transistors Cell library free Wirelength minimization 61

Conclusions Predictability (estimation tools) Connections regularity Design driven by wires and not by logic cells

62

Power and Timing Driven Physical Design Automation Ricardo Reis

Universidade Federal do Rio Grande do Sul Instituto de Informática - Porto Alegre - RS - Brasil e-mail: [email protected] 63