Pulse-Width Modulated Rectifiers - ECEE

Chapter 18

Pulse-Width Modulated Rectifiers

18.1

Properties of the ideal rectifier

18.2

Realization of a near-ideal rectifier

18.3

Control of the current waveform

18.4

Single-phase converter systems employing ideal rectifiers

18.5

RMS values of rectifier waveforms

18.6

Modeling losses and efficiency in CCM high-quality rectifiers

18.7

Ideal three-phase rectifiers

Fundamentals of Power Electronics

1

Chapter 18: PWM Rectifiers

18.1 Properties of the ideal rectifier It is desired that the rectifier present a resistive load to the ac power system. This leads to • unity power factor • ac line current has same waveshape as voltage

vac(t) i ac(t) = Re

Re is called the emulated resistance

iac(t) + vac(t)

Re

– Fundamentals of Power Electronics

2


Control of power throughput

V 2ac,rms Pav = Re(vcontrol)

iac(t) + vac(t)

Power apparently “consumed” by Re is actually transferred to rectifier dc output port. To control the amount of output power, it must be possible to adjust the value of Re.


3

Re(vcontrol)

– vcontrol


Output port model

The ideal rectifier is lossless and contains no internal energy storage. Hence, the instantaneous input power equals the instantaneous output power. Since the instantaneous power is independent of the dc load characteristics, the output port obeys a power source characteristic.


Ideal rectifier (LFR)

iac(t) +

2

p(t) = vac /Re

vac(t)

Re(vcontrol)

i(t) + v(t) –

– ac input

dc output vcontrol

v 2ac(t) p(t) = Re(vcontrol(t))

4

v 2ac(t) v(t)i(t) = p(t) = Re Chapter 18: PWM Rectifiers

The dependent power source

i(t)

i(t)

p(t)

v(t)i(t) = p(t)

i(t) +

+

v(t)

v(t)

–

–

power source

p(t)

v(t)

power sink

i-v characteristic


5


Equations of the ideal rectifier / LFR When connected to a resistive load of value R, the input and output rms voltages and currents are related as follows:

Defining equations of the ideal rectifier:

i ac(t) =

vac(t) Re(vcontrol)

v(t)i(t) = p(t)

v 2ac(t) p(t) = Re(vcontrol(t))


6

Vrms = Vac,rms

R Re

I ac,rms = I rms

R Re


18.2 Realization of a near-ideal rectifier Control the duty cycle of a dc-dc converter, such that the input current is proportional to the input voltage:

dc–dc converter

ig(t)

1 : M(d(t)) +

iac(t) vac(t)

i(t) +

vg(t)

v(t)

–

–

C

R

d(t) ig Controller vg Fundamentals of Power Electronics

7


Waveforms vac(t)

ig(t)

VM t

v(t)

iac(t)

V

VM /Re M(t)

t

Mmin

vg(t)

VM


vac(t) = VM sin (ωt)

M(d(t)) =

vg(t) = VM sin (ωt)

M min = V VM

8

v(t) V = vg(t) VM sin (ωt)


Output-side current Averaged vg(t)i g(t) v 2g(t) i(t) = = over V VRe switching V 2M i(t) = sin 2 (ωt) period

VRe V 2M 1 – cos (2ωt) = 2VRe

Averaged over ac line I = i(t) period V 2M

P=

1 : M(d(t)) +

vac(t)

2Re

dc–dc converter ig(t)

iac(t)

V 2M = TL 2VRe

i(t) +

vg(t)

v(t)

–

–

C

R

d(t) ig Controller vg


9


Choice of converter

M(d(t)) =


M(t)

Mmin

• To avoid distortion near line voltage zero crossings, converter should be capable of producing M(d(t)) approaching infinity • Above expression neglects converter dynamics • Boost, buck-boost, Cuk, SEPIC, and other converters with similar conversion ratios are suitable • We will see that the boost converter exhibits lowest transistor stresses. For this reason, it is most often chosen Fundamentals of Power Electronics

10


18.2.1 CCM Boost converter with controller to cause input current to follow input voltage

Boost converter i(t)

ig(t) +

iac(t) vac(t)

+

L

D1

vg(t)

Q1

v(t)

R

–

– vg(t)

C

ig(t)

d(t)

Controller

• DC output voltage ≥ peak AC input voltage • Controller varies duty cycle as necessary to make ig(t) proportional to vg(t) Fundamentals of Power Electronics

11


Variation of duty cycle in boost rectifier M(d(t)) =


Since M ≥ 1 in the boost converter, it is required that V ≥ VM If the converter operates in CCM, then

M(d(t)) =

1 1 – d(t)

The duty ratio should therefore follow

vg(t) d(t) = 1 – V


12

in CCM


CCM/DCM boundary, boost rectifier Inductor current ripple is

vg(t)d(t)Ts ∆i g(t) = 2L Low-frequency (average) component of inductor current waveform is

i g(t)

Ts

=

vg(t) Re

The converter operates in CCM when

i g(t)

2L > ∆i (t) ⇒ d(t) < g Ts ReTs

Substitute CCM expression for d(t):

Re
vg(t) V VTs g


1–

vg(t) V

16


Boost input characteristics

d=0

d = 0.2

d = 0.4

d = 0.6

d=1

1

d = 0.8

with superimposed resistive characteristic

jg(t) = 2L i g(t) VT s

0.75

CCM: vg(t) = 1 – d(t) V

DCM: 0.5

) i g(t

=

t) v g(

2L i (t) 1 – vg(t) = d 2(t) vg(t) VTs g V V

/R e

CCM when CCM

0.25

2L i (t) > vg(t) VTs g V

DCM

1–

vg(t) V

0 0

0.25

0.5

m g(t) = Fundamentals of Power Electronics

0.75

1

vg(t) V 17


Open-loop DCM approach We found in Chapter 11 that the buck-boost, SEPIC, and Cuk converters, when operated open-loop in DCM, inherently behave as loss-free resistors. This suggests that they could also be used as near-ideal rectifiers, without need for a multiplying controller. Advantage: simple control Disadvantages: higher peak currents, larger input current EMI Like other DCM applications, this approach is usually restricted to low power (< 200W). The boost converter can also be operated in DCM as a low harmonic rectifier. Input characteristic is vg(t) v 2g(t) i g(t) T = + Re s R v(t) – v (t) e

g

Input current contains harmonics. If v is sufficiently greater than vg, then harmonics are small. Fundamentals of Power Electronics

18


Other similar approaches • Use of other converters (in CCM) that are capable of increasing the voltage: SEPIC, Cuk, buck-boost Flyback, isolated versions of boost, SEPIC, Cuk, etc. • Boundary or critical conduction mode: operation of boost or other converter at the boundary between CCM and DCM • Buck converter: distortion occurs but stresses are low • Resonant converter such as parallel resonant converter or some quasi-resonant converters • Converters that combine the functions of rectification, energy storage, and dc-dc conversion


19


18.2.2 DCM flyback converter Flyback converter

EMI filter ig(t) iac(t)

n:1

D1

+ L

vac(t)

i(t) + v(t)

C

R

vg(t) Q1

–

–

D

Operation in DCM: we found in Chapter 11 that the converter input port obeys Ohm’s law with effective resistance Re = 2n2L/D2Ts. Hence, simply connect input port to AC line.


20


Averaged large-signal model EMI filter

〈 ig(t) 〉T

Averaged model 〈 i(t) 〉T

+

iac(t) vac(t)

vg(t)

+ 2n 2L D 2T s

〈 p(t) 〉T

–

〈v(t)〉T

C

R

– D

• Under steady-state conditions, operate with constant D • Adjust D to control average power drawn from AC line


21


Converter design Select L small enough that DCM operation occurs throughout AC line cycle. DCM occurs provided that d3 > 0, or d 2(t) < 1 – D But vg(t) d 2(t) = D nV Substitute and solve for D:

D
+ L V V

Ts

vg(t) TsV vg(t) 1– V 2L V

R

or,

Ts

>

jg(t) = i g(t)

i g(t)

0.8

Rbase V

Mode boundary: CCM occurs when

ma = V 2L Rbase = 2L Ts

R = e R

ma +

ase

vg(t) V

base

i c(t) – 1 –

Re = 0.5R b

V – vg(t) vg(t) + m a L

ase

Ts

=

in DCM

Re = 0.33R b

i g(t)

Static input characteristics of CPM boost, with minimum slope compensation:

base

vg(t)

Li 2c (t) fs

Re =

0 0.0

ma = V 2L 38

0.2

0.4

0.6

0.8

vg(t) V


1.0

Input current waveforms with current mode control

i g(t) Peak i g

• Substantial distortion can occur

1.0

ma = V 2L Rbase = 2L Ts

0.2

ase

Re = 0.33 Rb

R = e 0.1R

bas

e

0.4

Re = 2R b

id uso Sin

0.6

• Can meet harmonic limits if the range of operating points is not too large

ase

0.8

0.0


ωt

39

• Difficult to meet harmonic limits in a universal input supply


18.3.3 Critical conduction mode and hysteretic control Variable switching frequency schemes

ig(t)

Hysteretic control

• Hysteretic control • Critical conduction mode (boundary between CCM and DCM)

ωt

ig(t)

Critical conduction mode

ton


40

ωt


An implementation of critical conduction control

Boost converter

EMI filter

ig(t)

i(t)

+

iac(t) vac(t)

L

+

D1

vg(t)

C

Q1

– vcontrol (t)

v(t) –

vg(t) Multiplier

X

Zero current ig detector

Rs va(t)

vr (t) = kx vg(t) vcontrol (t)

+ –

Comparator

S Q R Latch

Controller


41


R

Pros and cons of critical conduction control • Simple, low-cost controller ICs • Low-frequency harmonics are very small, with constant transistor on-time (for boost converter) • Small inductor • Increased peak current • Increased conduction loss, reduced switching loss • Requires larger input filter • Variable switching frequency smears out the current EMI spectrum • Cannot synchronize converter switching frequencies


42


Analysis ig(t)

Transistor is on for fixed time ton Transistor off-time ends when inductor current reaches zero Ratio of vg(t) to 〈ig(t)〉 is

Re = 2L t on

Inductor volt-second balance:

On time, as a function of load power and line voltage:

vg t on + vg – V t off = 0

t on = 4LP V 2M

Solve for toff:

t off = t on Fundamentals of Power Electronics

ωt

ton

43

vg V – vg Chapter 18: PWM Rectifiers

Switching frequency variations Solve for how the controller varies the switching frequency over the ac line period: 1 T s = t off + t on T s = 4LP V 2M vg(t) 1– V For sinusoidal line voltage variations, the switching frequency will therefore vary as follows:

V 2M V 1 fs = = 1 – M sin (ωt) V T s 4LP Minimum and maximum limits on switching frequency:

V 2M V min fs = 1– M V 4LP

V 2M max fs = 4LP

These equations can be used to select the value of the inductance L. Fundamentals of Power Electronics

44


18.3.4 Nonlinear carrier control • Can attain simple control of input current waveform without sensing the ac input voltage, and with operation in continuous conduction mode • The integral of the sensed switch current (charge) is compared to a nonlinear carrier waveform (i.e., a nonlinear ramp), on a cycle-bycycle basis • Carrier waveform depends on converter topology • Very low harmonics in CCM. Waveform distortion occurs in DCM. • Peak current mode control is also possible, with a different carrier


45


Controller block diagram Nonlinear carrier charge control of boost converter Boost converter D1

L

ig(t)

is(t)

+ is(t)

v(t)

C

:1

vg(t) + –

R

n

Q1 –

is /n

vi (t)

Comparator

Ci – vi (t) +

R Q

vc(t) Nonlinear carrier generator

vcontrol (t)

vc(t)

Latch

+ –

vi (t)

S Q 0

0

Ts

dTs

Ts

Clock

Nonlinear-carrier charge controller


46


Derivation of NLC approach The average switch current is t + Ts 1 i s(t) T = i s(τ)dτ Ts t s We could make the controller regulate the average switch current by • Integrating the monitored switch current • Resetting the integrator to zero at the beginning of each switching period • Turning off the transistor when the integrator reaches a reference value In the controller diagram, the integrator follows this equation:

vi(t) = 1 Ci i.e.,

vi(dT s) = Fundamentals of Power Electronics

dT s 0

is

i s(τ) n dτ

Ts

nC i fs

for 0 < t < dT s

for interval 0 < t < T s 47


How to control the average switch current Input resistor emulation: vg(t) i g(t)

=

Ts

Ts

Re(vcontrol)

Relate average switch current to input current (assuming CCM): i s(t)

Ts

= d(t) i g(t)

Ts

Relate input voltage to output voltage (assuming CCM): vg(t)

Ts

= d′(t) v(t)

Ts

Substitute above equations to find how average switch current should be controlled:

v(t) i s(t)

Ts

= d(t) 1 – d(t)


Ts

Re(vcontrol) 48


Implementation using nonlinear carrier v(t)

Desired control, from previous slide:

i s(t)

Ts

= d(t) 1 – d(t)

Ts

Re(vcontrol)

Generate carrier waveform as follows (replace d by t/Ts ): vc(t) = vcontrol t 1 – t for 0 ≤ t ≤ T s Ts Ts

vc(t + T s) = vc(t) The controller switches the transistor off when the integrator voltage equals the carrier waveform. This leads to: vi(dT s) = vc(dT s) = vcontrol(t) d(t) 1 – d(t)

i s(t)

Ts

nC i f s

= vcontrol(t) d(t) 1 – d(t)

v(t) Re(vcontrol) = d(t) 1 – d(t) Fundamentals of Power Electronics

49

i s(t)

Ts Ts

v(t) =

Ts

nC i fsvcontrol(t) Chapter 18: PWM Rectifiers

Generating the parabolic carrier Removal of dc component vcontrol (t)

vc(t)

+–

Integrator with reset

Integrator with reset Clock

(one approach, suitable for discrete circuitry) Note that no separate multiplier circuit is needed


50


18.4 Single-phase converter systems containing ideal rectifiers •

It is usually desired that the output voltage v(t) be regulated with high accuracy, using a wide-bandwidth feedback loop

•

For a given constant load characteristic, the instantaneous load current and power are then also constant: pload (t) = v(t)i(t) = VI

•

The instantaneous input power of a single-phase ideal rectifier is not constant: pac(t) = vg(t)i g(t) with

so

vg(t) = VM sin (ωt)

vg(t) i g(t) = Re

V 2M V 2M 2 pac(t) = sin ωt = 1 – cos 2ωt Re 2Re


51


Power flow in single-phase ideal rectifier system

•

Ideal rectifier is lossless, and contains no internal energy storage.

•

Hence instantaneous input and output powers must be equal

•

An energy storage element must be added

•

Capacitor energy storage: instantaneous power flowing into capacitor is equal to difference between input and output powers:

pC(t) =

d EC(t) = dt

d

1 2

Cv 2C(t) dt

= pac(t) – pload(t)

Energy storage capacitor voltage must be allowed to vary, in accordance with this equation


52


Capacitor energy storage in 1¿ system pac(t)

Pload

vc(t)

d =

1 2

Cv 2C(t) dt


t Fundamentals of Power Electronics

53


Single-phase system with internal energy storage

〈 pac(t)〉T

+

iac(t) vac(t)

pload(t) = VI = Pload

Ideal rectifier (LFR) i (t) 2

ig(t)

vg(t)

+

+ s

Re

C

–

vC(t)

Dc–dc converter

i(t) v(t)

load

–

– Energy storage capacitor

Energy storage capacitor voltage vC(t) must be independent of input and output voltage waveforms, so that it can vary according to

d =

1 2

Cv 2C(t) dt

This system is capable of



54

•

Wide-bandwidth control of output voltage

•

Wide-bandwidth control of input current waveform

•

Internal independent energy storage Chapter 18: PWM Rectifiers

Hold up time Internal energy storage allows the system to function in other situations where the instantaneous input and output powers differ.

A common example: continue to supply load power in spite of failure of ac line for short periods of time. Hold up time: the duration which the dc output voltage v(t) remains regulated after vac(t) has become zero A typical hold-up time requirement: supply load for one complete missing ac line cycle, or 20 msec in a 50 Hz system During the hold-up time, the load power is supplied entirely by the energy storage capacitor


55


Energy storage element Instead of a capacitor, and inductor or higher-order LC network could store the necessary energy.

But, inductors are not good energy-storage elements Example 100 V 100 µF capacitor 100 A 100 µH inductor each store 1 Joule of energy But the capacitor is considerably smaller, lighter, and less expensive So a single big capacitor is the best solution


56


Inrush current A problem caused by the large energy storage capacitor: the large inrush current observed during system startup, necessary to charge the capacitor to its equilibrium value. Boost converter is not capable of controlling this inrush current. Even with d = 0, a large current flows through the boost converter diode to the capacitor, as long as v(t) < vg(t). Additional circuitry is needed to limit the magnitude of this inrush current. Converters having buck-boost characteristics are capable of controlling the inrush current. Unfortunately, these converters exhibit higher transistor stresses.


57


Universal input The capability to operate from the ac line voltages and frequencies found everywhere in the world: 50Hz and 60Hz Nominal rms line voltages of 100V to 260V: 100V, 110V, 115V, 120V, 132V, 200V, 220V, 230V, 240V, 260V Regardless of the input voltage and frequency, the near-ideal rectifier produces a constant nominal dc output voltage. With a boost converter, this voltage is 380 or 400V.


58


Low-frequency model of dc-dc converter Dc-dc converter produces well-regulated dc load voltage V. Load therefore draws constant current I. Load power is therefore the constant value Pload = VI. To the extent that dc-dc converter losses can be neglected, then dc-dc converter input power is Pload , regardless of capacitor voltage vc(t). Dc-dc converter input port behaves as a power sink. A low frequency converter model is p (t) = VI = P i (t) load

2

+ C

vC(t)

+ Pload V + –

– Energy storage capacitor


59

load

i(t) v(t) load – Dc-dc converter


Low-frequency energy storage process, 1¿ system A complete low-frequency system model: iac(t) vac(t)


i2(t)

ig(t) 〈 pac(t)〉Ts

+ vg(t)

Re

+ C

vC(t)

+ Pload V + –

–

– Ideal rectifier (LFR)

Energy storage capacitor

i(t) v(t) load – Dc-dc converter

•

Difference between rectifier output power and dc-dc converter input power flows into capacitor

•

In equilibrium, average rectifier and load powers must be equal

•

But the system contains no mechanism to accomplish this

•

An additional feeback loop is necessary, to adjust Re such that the rectifier average power is equal to the load power


60


Obtaining average power balance

iac(t) vac(t)


i2(t)

ig(t) 〈 pac(t)〉Ts

+ vg(t)

Re

+ C

vC(t)

+ Pload V + –

v(t) load

–



i(t)

– Dc-dc converter

If the load power exceeds the average rectifier power, then there is a net discharge in capacitor energy and voltage over one ac line cycle. There is a net increase in capacitor charge when the reverse is true. This suggests that rectifier and load powers can be balanced by regulating the energy storage capacitor voltage.


61


A complete 1¿ system containing three feedback loops Boost converter i2(t) +

ig(t) +

iac(t) vac(t)

L

vg(t)

Q1

vC(t)

– vcontrol(t)

vg(t) Multiplier

X

i(t)

D1 DC–DC Converter

C

Load v(t)

–

–

ig(t) Rs

d(t)

PWM

v(t)

va(t)

vref1(t) = kxvg(t)vcontrol(t)

+

v (t) +– err Gc(s)

Compensator and modulator

–+ vref3

Compensator

Wide-bandwidth output voltage controller

Wide-bandwidth input current controller vC(t) Compensator

–+ vref2

Low-bandwidth energy-storage capacitor voltage controller


62


Bandwidth of capacitor voltage loop •

The energy-storage-capacitor voltage feedback loop causes the dc component of vc(t) to be equal to some reference value

•

Average rectifier power is controlled by variation of Re.

•

Re must not vary too quickly; otherwise, ac line current harmonics are generated

•

Extreme limit: loop has infinite bandwidth, and vc(t) is perfectly regulated to be equal to a constant reference value • Energy storage capacitor voltage then does not change, and this capacitor does not store or release energy • Instantaneous load and ac line powers are then equal • Input current becomes i ac(t) =


pac(t) p (t) Pload = load = vac(t) vac(t) VM sin ωt 63


Input current waveform, extreme limit i ac(t) =

pac(t) p (t) Pload = load = vac(t) vac(t) VM sin ωt

THD → ∞ Power factor → 0

vac(t)

iac(t)

t


64

So bandwidth of capacitor voltage loop must be limited, and THD increases rapidly with increasing bandwidth


18.4.2 Modeling the outer low-bandwidth control system This loop maintains power balance, stabilizing the rectifier output voltage against variations in load power, ac line voltage, and component values The loop must be slow, to avoid introducing variations in Re at the harmonics of the ac line frequency Objective of our modeling efforts: low-frequency small-signal model that predicts transfer functions at frequencies below the ac line frequency


65


Large signal model averaged over switching period Ts Ideal rectifier (LFR)

〈 ig(t)〉Ts

s

〈 p(t)〉T 〈 vg(t)〉T

s

+ –

〈 i2(t)〉T

+ s

〈 v(t)〉T

C

Re (vcontrol )

s

Load

– ac input

dc output vcontrol

Ideal rectifier model, assuming that inner wide-bandwidth loop operates ideally High-frequency switching harmonics are removed via averaging Ac line-frequency harmonics are included in model Nonlinear and time-varying Fundamentals of Power Electronics

66


Predictions of large-signal model Ideal rectifier (LFR)

〈 ig(t)〉Ts

If the input voltage is vg(t) = 2 vg,rms sin ωt

〈 p(t)〉T 〈 vg(t)〉T

s

+ –

Re (vcontrol )

〈 i2(t)〉T

s

+ s

C

〈 v(t)〉T

s

–

Then the instantaneous power is: vg(t)

ac input

dc output vcontrol

2

v 2g,rms p(t) T = = 1 – cos 2ωt s Re(vcontrol(t)) Re(vcontrol(t)) Ts

which contains a constant term plus a secondharmonic term


67


Load

Separation of power source into its constant and time-varying components 〈 i2(t)〉T

s

+ V 2g,rms – cos 2 2ωt Re

V 2g,rms Re

C

〈 v(t)〉Ts

Load

– Rectifier output port The second-harmonic variation in power leads to second-harmonic variations in the output voltage and current


68


Removal of even harmonics via averaging

v(t)

〈 v(t)〉Ts 〈 v(t)〉T

2L

t

T2L =


1 2

69

2π = π ω ω


Resulting averaged model

〈 i2(t)〉T2L + V 2g,rms Re

C

〈 v(t)〉T2L

Load

– Rectifier output port

Time invariant model Power source is nonlinear


70


Perturbation and linearization The averaged model predicts that the rectifier output current is

p(t) i 2(t)

T 2L

=

v(t)

T 2L T 2L

=

v 2g,rms(t) Re(vcontrol(t)) v(t)

= f vg,rms(t), v(t) Let

T 2L

, vcontrol(t))

T 2L

with

v(t) i 2(t)

T 2L T 2L

= V + v(t)

V >> v(t)

= I 2 + i 2(t)

I 2 >> i 2(t)

vg,rms = Vg,rms + vg,rms(t) vcontrol(t) = Vcontrol + vcontrol(t)


Vg,rms >> vg,rms(t) Vcontrol >> vcontrol(t) 71


Linearized result vcontrol(t) I 2 + i 2(t) = g 2vg,rms(t) + j2v(t) – r2 where df vg,rms, V, Vcontrol) g2 =

=

dvg,rms

– 1 = r2

v g,rms = V g,rms

df Vg,rms, v d v

, Vcontrol)

T 2L

=–

T 2L

dvcontrol


I2 V

v T =V 2L

df Vg,rms, V, vcontrol) j2 =

Vg,rms 2 Re(Vcontrol) V

v control = V control

72

V 2g,rms dRe(vcontrol) =– VR 2e (Vcontrol) dvcontrol

v control = V control


Small-signal equivalent circuit i2

+ r2

j2 vcontrol

g 2 vg,rms

C

v

R

– Rectifier output port

Predicted transfer functions

Control-to-output

v(s) 1 = j2 R||r 2 vcontrol(s) 1 + sC R||r 2

Line-to-output

v(s) 1 = g 2 R||r 2 vg,rms(s) 1 + sC R||r 2


73


Model parameters

Table 18.1 Small-signal model parameters for several types of rectifier control schemes Controller type

g2

j2

r2

Average current control with feedforward, Fig. 18.14

0

Pav VVcontrol

V2 Pav

Current-programmed control, Fig. 18.16

2Pav VVg,rms

Pav VVcontrol

V2 Pav

Nonlinear-carrier charge control of boost rectifier, Fig. 18.21

2Pav VVg,rms

Pav VVcontrol

V2 2Pav

Boost with critical conduction mode control, Fig. 18.20

2Pav VVg,rms

Pav VVcontrol

V2 Pav

DCM buck-boost, flyback, SEPIC, or Cuk converters

2Pav VVg,rms

2Pav VD

V2 Pav


74


Constant power load ig(t) 〈 pac(t)〉Ts

+

iac(t)

vg(t)

vac(t)


i2(t)

Re

C

–

+

+ vC(t)

Pload V + –

v(t) load –



i(t)

Dc-dc converter

Rectifier and dc-dc converter operate with same average power Incremental resistance R of constant power load is negative, and is 2 V R=– Pav

which is equal in magnitude and opposite in polarity to rectifier incremental output resistance r2 for all controllers except NLC


75


Transfer functions with constant power load When r2 = – R, the parallel combination r2 || R becomes equal to zero. The small-signal transfer functions then reduce to

j v(s) = 2 vcontrol(s) sC

g v(s) = 2 vg,rms(s) sC


76


18.5 RMS values of rectifier waveforms Doubly-modulated transistor current waveform, boost rectifier:

iQ(t)

t Computation of rms value of this waveform is complex and tedious Approximate here using double integral Generate tables of component rms and average currents for various rectifier converter topologies, and compare Fundamentals of Power Electronics

77


RMS transistor current RMS transistor current is I Qrms =

1 Tac

T ac

iQ(t)

i 2Q(t)dt

0

Express as sum of integrals over all switching periods contained in one ac line period: I Qrms =

1 T Tac s

T ac/T s

∑ n=1

1 Ts

t

nT s

i 2Q(t)dt

(n-1)T s

Quantity in parentheses is the value of iQ2, averaged over the nth switching period.


78


Approximation of RMS expression I Qrms =

T ac/T s

∑

1 T Tac s

1 Ts

n=1

nT s

i 2Q(t)dt

(n-1)T s

When Ts

Pulse-Width Modulated Rectifiers - ECEE

Pulse-Width Modulated Rectifiers - ECEE

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