Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for ...

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement Yajuan Du1,2 , Qiao Li3 , Liang Shi3 , Deqing Zou1,♯ , Hai Jin1 , Chun Jason Xue2 1

Service Computing Technology and System Lab, Cluster and Grid Computing Lab, Big Data Technology and System Lab, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, China 2 Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong 3 College of Computer Science, Chongqing University, Chongqing, China ♯ Prof. Deqing Zou is corresponding author [email protected],[email protected]

ABSTRACT

flash errors, is caused by decreased data retention capability of flash cells [5]. Longer retention time induces higher raw bit In order to relieve reliability problem caused by technology error rates (RBERs), which may exceed capability of error scaling, LDPC codes have been widely applied in flash memcorrection codes (ECC). The popular method to overcome ories to provide high error correction capability. However, increasing RBERs is to apply advanced ECC, low-density LDPC read performance slowdown along with data retention parity-check (LDPC) codes [12]. Although with much higher largely weakens the access speed advantage of flash memoerror correction capability than traditional ECC, such as ries. This paper considers to apply the concept of refresh, BCH codes, LDPC codes induce large read latency when that were used for flash lifetime improvement, to optimize data retention becomes long. This phenomenon has also been flash read performance. Exploiting data read characteristics, reported by Samsung [2] that it is much slower to read back this paper proposes LDR, a lightweight data refresh method, from old data than fresh data in flash memory. LDPC read that aggressively corrects errors in read-hot pages with long latency comes from current progressive read-retry sensing read latency and reprograms error-free data into new pages. and decoding steps [16]. For old data with high RBERs, more Experimental results show that LDR can achieve 29% read read-retry steps are required for successful LDPC read. This performance improvement with only 0.2% extra P/E cycles induces latency accumulation of each read-retry step and on average, which causes negligible overhead on flash lifetime. worsens flash read performance, especially for read-intensive applications for late-lifetime flash. CCS CONCEPTS In order to improve flash read performance, this paper con• Computer systems organization → Reliability; Firmware; siders to apply the concept of refresh on reducing long read latency from high RBERs. The prior works about the refresh KEYWORDS technique, such as flash correct and refresh (FCR) [6], WARLDPC Codes, Flash Read Performance, Data Refresh M [11] and process variation (PV) based refresh [7] all utilize ACM Reference format: the refresh mechanism to improve flash lifetime by keeping Yajuan Du1,2 , Qiao Li3 , Liang Shi3 , Deqing Zou1,♯ , Hai Jin1 , data integrity of long-retention flash blocks. Erroneous data Chun Jason Xue2 . 2017. Reducing LDPC Soft Sensing Latency by are periodically corrected in block level and reprogrammed Lightweight Data Refresh for Flash Read Performance Improveinto new blocks to avoid RBERs exceeding error correction ment. In Proceedings of Design Automation Conference, Austin, capability of BCH codes. When applied for LDPC read perTX, USA, June 2017 (DAC ’17), 6 pages. formance improvement, refresh can reset high-level sensing https://doi.org/10.1145/3061639.3062309 latency of erroneous pages back to the cheapest hard sensing. However, heavy block migration costs are involved in current 1 INTRODUCTION refresh method, which harms flash lifetime, a new refresh With technology scaling, flash-based solid state drives become method has to be designed. more prone to errors. Retention error, as the main type of This paper proposes LDR, a lightweight data refresh method by exploiting the access characteristics of read-hot data. The Permission to make digital or hard copies of all or part of this work lightweight nature of LDR can be reflected in two aspects. for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage First, LDR only refreshes read-hot data with soft sensing, and that copies bear this notice and the full citation on the first which induces long read latency. As read-hot data often takes page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy up a small portion but frequently accessed [9], potential read otherwise, or republish, to post on servers or to redistribute to lists, performance improvement will be high. This paper focuses requires prior specific permission and/or a fee. Request permissions on LDPC read performance optimization without considering from [email protected]. DAC ’17, June 2017, Austin, TX, USA data integrity problem. Second, the refresh granularity of © 2017 Association for Computing Machinery. LDR is in page level. As only one or several read-hot pages ISBN 978-1-4503-4927-7/17/06. . . $15.00 https://doi.org/10.1145/3061639.3062309

DAC ’17, June 2017, Austin, TX, USA are moved in one refresh operation, heavy block migration costs in current refresh methods [6, 7, 11] can be reduced. To evaluate and verify the effectiveness of LDR, seventeen real workloads are run in the trace-driven simulation platform, DiskSim [4] with SSD extension. Experimental results show that LDR can improve 29% of flash read performance with only 0.2% extra P/E cycles on average, which causes negligible flash lifetime reduction. As a comparison, current refresh method induces 107% extra P/E cycles although with 35% read performance improvement. The following contributions are made in this paper. • Studies potential benefits of applying data refresh for better LDPC read performance in real workloads with a preliminary experiment. • Proposes LDR, a lightweight data refresh method to reduce read latency with soft sensing. By exploiting characteristics of read-hot data, LDR refreshes a small portion of data and takes little P/E cycle. • Evaluates LDR with seventeen trace-driven workloads and verifies that LDR can largely improve LDPC read performance, especially for read-intensive workloads in flash late lifetime stage. The remainder of the paper is illustrated as follows. Background and motivation are introduced in Section 2. The proposed method, LDR, is presented in Section 3. Experiment setup and results are shown in Section 4. Conclusion of this paper is presented in Section 5.

2

BACKGROUND AND MOTIVATION

This section first introduces the problem of LDPC read performance slowdown along with data retention and existing works to solve this problem. Then, related works on refresh mechanisms and the opportunity to apply refresh for LDPC read performance improvement are presented.

2.1

LDPC Read Performance Slowdown

Flash memory cells store data by keeping amount of electrons. For multi-level cell (MLC) flash, flash cells may be in one of the four states: the erased state and three programmed states. When data are kept for long time, electrons in programmed states decrease. Once thresholds between adjacent states are crossed, one or two data bits are flipped and retention error happens. Weak cells that experienced a lot of P/E cycles are more prone to retention errors and have higher RBERs. LDPC codes apply multiple read-retry steps to sense and decode flash data. When results from the first step, the hard sensing step, fail to decode data, extra soft sensing steps are progressively tried until the decoding succeeds [16]. Overall read latency for the data is the accumulated latency of all tried steps. As soft sensing steps take longer latency than the hard sensing step, LDPC read performance is largely slowed down on old data with long retention, as shown in Figure 1(a). Read performance using LDPC codes is mainly affected by RBERs of data that need to be decoded. Comprehensive

Y. Du et al. solutions are proposed to reduce RBERs. EC-Cache [10] proposed to use an error correction cache to store information of errors detected in prior reads. The errors are corrected before data are decoded in subsequent reads. RBERs are lowered down by using extra RAM storage of error information. AGCR [9] exploited cost asymmetry between reads and writes and proposed to apply varied programming speeds according to workload characteristics. RBERs are reduced by applying slower programming speed for read-dominant workloads, which makes faster read speed. FlexLevel [8] proposed to store three instead of four states in multi-level per cell flash memory. RBERs are decreased by using wider noise margin between cell states.

2.2

Applying Data Refresh for Read Performance Improvement

According to above analysis, reducing RBERs of data is an effective method to reduce high LDPC latency. This paper borrows the idea of refresh to reduce RBERs and improve flash read performance. Refresh can reset long LDPC read latency with soft sensing back to the cheapest latency with hard sensing. As shown in Figure 1(b), when LDPC reaches to high read latency, refresh operation is activated to correct errors and reprogram error-free data into new blocks, which can benefit read performance of subsequent reads. Existing works exploited the refresh mechanism to ensure data integrity with BCH codes. Cai et.al [6] proposed to apply correct and refresh in flash memory to solve the lifetime problem caused by ECC expiration. When data are kept for long, all valid pages in the block are corrected and moved into another block. In order to avoid unnecessary refresh operations to write-hot blocks, WARM [11] proposed to only correct and refresh write-cold data. Di et. al [7] proposed to exploit process variation among blocks to refresh long-kept data into strong blocks.

LDPC Read Latency

LDPC Read Latency

L0

L0

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Data Retention

Refresh

Data Retention

(a) LDPC Read Performance S- (b) Refresh Lowers Down LD-

lowdown.

PC Read Latency.

Figure 1: The Concept of Refresh. In order to further study the potential benefit of applying refresh to improve read performance, a preliminary study has been performed with seventeen workloads on Disksim with SSD extensions [4]. Read performance and extra P/E cycles of basic LDPC reads [16] (Baseline) and the method with traditional refresh method [6] (Refresh) are shown in Figure 2. Besides, the results of a new method, Selective, are also presented, which selectively corrects errors only in read-hot pages. Selective is a ideal case just counting benefits

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for ... but not overheads of refresh operations. It can be found from the results that Refresh improves 35% of Baseline read performance while Selective improves 30%. However, heavy P/E overhead, 107% P/E cycles of Baseline, are involved in Refresh. In order to minimize the high refresh cost by directly applying traditional refresh method for LDPC read performance improvement, this paper proposes a lightweight data refresh method to approach performance of Selective by exploiting access characteristics of workloads.

with hot reads can accumulate more performance benefits taken by the refresh operation. Thus, it would be more valuable to refresh data pattern one. Details of the lightweight refresh technique is presented in the next section. Hot Reads

Hot Reads

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Figure 3: Patterns of Read Hot/Cold Data with Long/Short Retention.

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(b) Heavy P/E Overhead Caused by Traditional Refresh

Method.

Figure 2: Potential Read Performance Benefit and Overhead by Refresh Method.

LIGHTWEIGHT DATA REFRESH METHOD

LDR applies a decision tree to identify the read-hot data pattern, as shown in Figure 4. Three decision nodes are involved in the decision tree. When read data are successfully decoded in LDPC decoder, LDPC read latency can be determined by the current sensing level. In the first decision node, LDR identifies pages with soft sensing levels as refresh candidates. The second decision node of Figure 4 judges whether the read page exists in the LRU list, which keeps logical addresses and read counts of N recent read pages. If does, the corresponding read counts increments and the page is taken as refresh candidate of the next decision node. Otherwise, the page is inserted to the LRU list as the first item. In the third decision node, if read hotness of candidates from the last decision node is larger than T , they are considered as read-hot pages and put into refresh queues to wait for refresh operations. LDPC read

This section presents details of the proposed LDR method, which contains two parts: identifying read-hot data and lightweight page-level data refresh. Firstly, based on current work [15] that uses grouping-based least recently used (LRU) list to identify write-hot data, LDR applies a decision tree to identify read-hot data, data pattern one shown in Figure 3. Second, LDR refreshes data pattern one by refresh queues shown in Figure 5.

3.1

1

Retention

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LDPC sensing level is soft?

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Identifying Read-Hot Data

According to retention time and access density, LDR first classifies data into four types, as shown in Figure 3, in which arrows represent data reads and vertical lines represent data updates. The first two patterns probably induce high RBERs because of long retention, which require LDPC soft sensing for successful reads, called “soft reads”. The last two patterns probably require hard sensing in LDPC reads, called “hard reads”, because of short retention. As soft reads takes more costs than hard reads, potential read performance improvement can be achieved by refreshing them. Thus, the first two data patterns are candidates to perform refresh operations. Furthermore, when comparing read density, data pattern one

No

Hotness > T?

No

Hotness++

Yes Insert to package refresh queue

Figure 4: The Decision Tree for Read-Hot Data Identification.

3.2

Lightweight Data Refresh in Page Level

When hot pages are identified, refresh queue keeps their logical address. LDR allocates one refresh queue for each flash package to keep logical addresses of hot pages and stores

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the queue in RAM of flash controller, as shown in Figure 5. There are several cases to deal with the refresh queue. The first case is that when new reads come to the package with non-empty refresh queue, all elements in the queue are first refreshed by reading the data into controller and reprogramming error-free data into new pages. The service of these reads has to be postponed. The second case is that when new writes come to the package. As write performance is not affected by the refresh operations, no refreshes would be performed regardless that the queue is empty or not. The third case is that when reads/writes and refresh operations conflict with each other. they have to wait until the refreshes of all queue elements are finished. An example is presented in Figure 5, in which refresh queue of package 1 has elements denoted as LP N𝑖 while that of package 2 has no elements. When new reads reach package 1, refresh operations are first performed on pages in refresh queue. When page refreshes are all finished, read requests are served. As each package has one refresh queue, the parallelism among packages can be exploited to achieve better access performance. Refresh queue 1 has elements First refresh pages LPNi LPN1 LPN2 LPN3 . . . Flash Package 1 Hot pages all refreshed, read again

Refresh queue 2 is empty Host Reads

Flash Package 2 Directly read NAND flash

...

... Lightweight Data Refresh

NAND Flash

Figure 5: The Sub-system to Implement Lightweight Read-Hot Data Refresh.

3.3

Architecture

This section presents the whole flash system integrated with LDR, as shown in Figure 6. LDR is located in flash controller and closely communicates with other components. There are mainly three kinds of communications. The first and most frequent communication happens between LDPC component and LDR. On one hand, in hot data identification of LDR, requested pages have to be decoded with LDPC to obtain current sensing levels. Only with known sensing levels, LDR can identify data with long retention and perform further judgement. On the other hand, in lightweight data refresh of LDR, reads on pages to refresh are assisted by LDPC component. to obtain error-free data. As well, error-free data have be re-encoded to new data by LDPC component. The second communication happens between flash translation layer (FTL) and LDR. This communication is similar to that between FTL and access requests from host. FTL translates logical page addresses in both LRU list and refresh queues to physical page addresses to access flash data. The third communication happens between LDR and block cleaning operations, including garbage collection (GC) and wear leveling (WL). Three aspects of this communication are considered. First, for packages in which GC or WL is happening, refresh operations in LDR cannot be performed and have

to wait until block cleaning finishes. Second, as LDR only refresh pages with LDPC soft sensing level, GC and WL can reset LDPC latency and naturally reduce potential number of refreshes. Third, as extra page writes are involved in LDR, the number of block cleaning operations may increase. Host Requests

Requests Flash Translation Layer

Hot Data Identification

LDPC Encoder/Decoder

Lightweight Data Refresh LDR

Garbage Collection Wear Leveling

Flash Controller NAND Flash Array

Figure 6: The Whole Flash System Integrated with LDR.

3.4

Overhead Analysis

LDR Overheads come from extra P/E cycles and storage of LRU list and refresh queues. Extra P/E cycles are evaluated in Section 4.1. This section analyzes the storage overhead. Assume the size of physical addresses is 4 Bytes and LRU list contains 1000 items. Assume flash has eight packages and the refresh queue for each package has 100 items. The overall storage takes 4B ∗ (1000 + 100 ∗ 8) ≈ 7K For RAM with size of 256M, the 7K extra storage from LDR takes little proportion and can be ignored.

4

EVALUATION

In order to evaluate the proposed LDR, seventeen workloads from MSR and three workloads from UMASS [1, 3] have been run in the simulation platform DiskSim with SSD extensions [4]. The statistics of workloads are shown in Table 1, in which the read ratio column is computed as the ratio of read pages and written pages and the days column represents the duration of workloads. The workloads F 1 and F 2 represent workloads f inancial1 and f inancial2 in UMASS, respectively. Disksim configurations are shown in Table 2, in which the latencies are based on settings in [16]. The SSD system is simulated to use page-level mapping in FTL and the wear leveling method proposed in [13]. The read performance and overhead results are compared among current LDPC implementation [16] (Baseline), the proposed LDR and the case not counting refresh overheads (Ideal). To simulate flash error characteristics in late lifetime, initial retention is set to be one year and P/E cycles are set to be 10000, which is a extreme situation of flash late lifetime. Given P/E cycle and retention time, raw bit error rates can be computed according to the error model in [14]. The results of LDR in flash early lifetime stage are also studied by setting the same initial retention time and 5000 P/E cycles, as shown

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for ...

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Table 1: Workloads Statistics Write 13153463 605720 4604603 18265525 5691238 14127647 3095200 334365 130648 100684 26772 1932058 775983 5594270 65402 824502 1422974

Read Ratio 28% 64% 11% 28% 77% 22% 96% 3% 98% 97% 99.8% 37% 89% 12% 98% 61% 85%

Days 6 6.6 0.5 1.3 0.7 4.7 2.2 5.7 0.5 0.5 3.45 0.4 4.8 0.1 0.6 3.9 7

in Figure 10. The size of LRU list for read hotness identification is set to be 1000, which means that 1000 recently read pages are stored. 1000 is obtained by approximating the average accessed page size of several tens of successive requests. The results with other LRU sizes are studied to check the sensitivity to this parameter in Section 4.2. The hotness threshold to determine hot pages is set to be 2, which means that when one page in the LRU has been read more than two times, this page is considered to be read-hot. The sensitivity of LDR on this parameter is studied by setting two extra values, 1 and 3 in Section 4.2. Based on these datasets with different parameter settings, experimental results and analysis are shown as follows. Considering that read performance results of refresh have been shown in Section 2, Only comparisons among baseline, LDR and ideal are presented in the following results. Table 2: SSD Configurations. Flash Page Size Pages Per Block Blocks Per Plane Planes Per Package Packages

4.1

4KB 64 2048 8 8

Block Erase Page Write Hard Read Extra Soft Read Over-provisioning

3.5𝑚𝑠 900𝜇𝑠 85𝜇𝑠 24𝜇𝑠 15%

improvements from soft read ratio reduction are more significant. On the contrary, for workloads, such as proxy0, ts0, rsrch1 and proj1, with small read ratios, the benefits from LDR are greatly reduced, even for workloads with high soft read reductions, such as proxy0. In summary, the average read performance improvement on all workloads are 29% compared with the existing LDPC method. The other observation can be found in Figure 8, that the performance differences between LDR and the ideal case are varied for different workloads. For some workloads, such as rsrch2, stg1 and three workloads with high read ratios, F 1, F 2 and websearch, the differences are not obvious. This is because that extra writes take a small proportion of overall read/write requests. In summary, read performance of LDR is 4% slower than that of the ideal case. The results are very close and LDR has little effect on system performance, which also can be verified from P/E cycle results in Figure 9. 1 0.9 0.8

Soft Read Ratio

Read 5172477 1090912 545985 6966661 19136490 3976632 94361627 1110 6508016 4312858 16410267 1167249 6444861 773087 3471062 1301436 7992543

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Figure 7: Soft Read Ratios Normalized to Baseline. We analyze the overhead of LDR on P/E cycles, as shown in Figure 9. Some workloads are read-dominant, in which garbage collection does not happen and P/E cycles of them are zero. For the workloads with non-zero P/E cycles, LDR only increases 0.2% of P/E cycles in baseline on average. Because of over-provision space in SSD, it is not surprised that few extra P/E cycles are induced. This negligible overhead verifies that LDR is lightweight. 5

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Read Performance Benefit and P/E Overhead of LDR

The read response time results are shown in Figure 8. From the results, two observations can be found. Firstly, it can be found that performance benefits caused by LDR are greatly varied according to workloads. As soft reads cause LDPC read performance slowdown and LDR can reduce numbers of soft reads, the read performance improvement is closely related to two factors: read ratio of workloads shown in Table 1 and soft read ratio shown in Figure 7, which reflects the potential benefits from LDR. For workloads with large read ratios, such as f inancial1, f inancial2, websearch, stg1 and hm1, read performance improvements are high and in proportion to the ratio of reduced soft reads. This can be explained that when reads take a large portion, performance

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Workload wdev0 rsrch2 proxy0 prn1 prn0 ts0 stg1 rsrch1 F1 F2 websearch hm0 hm1 proj1 proj3 proj4 web1

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Figure 9: Overheads of LDR on P/E Cycles.

4.2

Sensitivity Study

This section studies the sensitivity of LDR on three factors: LRU size, read hotness threshold on read hotness identification and flash lifetime stage. The experimental results are shown in Figure 10. In the study on LRU size and read hotness threshold, with larger LRU size and smaller hotness threshold, more read-hot pages can be found and better read performance can be achieved. However, more storage overheads are required. It is a tradeoff between read performance improvement and storage overhead. In the study on

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Read Response Time

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Figure 8: Read Performance Results

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Figure 10: Sensitivity Study on Three Factors. Read Performance is Normalized to Baseline. flash lifetime stage, when flash is in early lifetime stage, read performance slowdown caused by soft sensing latency is not obvious. LDR does not achieve as many read performance improvements as that in flash late lifetime stage. Thus, LDR will be more effective for flash in late lifetime stage.

5

CONCLUSION

This paper proposes LDR, a lightweight data refresh method to reset long read latency with soft-decision sensing and decoding back to the cheapest latency with hard-decision sensing and decoding. By exploiting access characteristics of read-hot data, LDR performs page-level refresh and can largely improve LDPC read performance but takes little refresh overhead on P/E cycles. Experimental results show the effectiveness and the lightweight nature of LDR.

[7]

[8]

[9]

[10]

[11]

ACKNOWLEDGEMENT This work is supported by National Science Foundation of China (NSFC) 61672249 and National 973 Fundamental Basic Research Program 2014CB340600 and is partially supported by NSFC 61572411 and National 863 Program 2015AA015304.

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