Resist process control for 32-nm logic node and ...

Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool Seiji Nagahara*a, Kazuhiro Takahatab, Seiji Nakagawab, Takashi Murakamia, Kazuhiro Takedaa, Shinpei Nakamuraa, Makoto Uekic, Masaki Satakeb, Tatsuhiko Emab, Hiroharu Fujiseb, Hiroki Yonemitsub, Yuriko Seinob, Shinichiro Nakagawab, Masafumi Asanob, Yosuke Kitamurad, Takayuki Uchiyamaa, Shoji Mimotogib, Makoto Tominagaa a

Process Technology Division, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan b Process & Manufacturing Engineering Center, Semiconductor Company, TOSHIBA CORPORATION, 8, Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa, 235-8522, Japan c LSI Fundamental Research Laboratory, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan d System LSI Division 1, Semiconductor Company, TOSHIBA CORPORATION, 8, Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa, 235-8522, Japan ABSTRACT Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns, we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For 2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns, it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist. Keywords: 32-nm node logic, low-k1 lithography, ArF immersion lithography, LWR, 2D-pattern deformation, resist pattern collapse, hole shrink, acid diffusion control

1.

INTRODUCTION

As technology nodes shrink, the allowable process tolerance to fulfill the required logic device performance becomes increasingly smaller. In logic devices, patterning with low k1 factor in the Rayleigh’s equation is difficult because a wide variety of pattern shapes are exposed at once [1]-[5]. To realize the patterning of 32-nm node device and beyond, there are several challenges in the resist processing [1]-[4]. Line-width roughness (LWR) reduction and process-window enhancement for various layouts are important. The 2D-pattern shape fidelity is becoming more and more important as the technology shrinks. Resist pattern collapse prevention is indispensable for 32 nm node and beyond. In this paper, we mainly focus on 32-nm logic node results and discuss the technology aiming at 28-nm logic node. Table 1 is our tentative design rule for 32- and 28-nm node logic devices. For 32-nm node, we use 100-nm pitch for metal layer with 50-nm half pitch (HP). For contact hole, we use 126-nm pitch as the minimum pitch. The hole pitch is relaxed to be patterned by single exposure, not by double patterning. For the lithography design of 32-nm node, we employ a single exposure on 1.35-NA ArF immersion scanner without the use of double exposure to reduce the manufacturing cost. Attenuated-phase-shift masks (att. PSMs) are used for 32-nm node. The design rule for 28-nm logic node is 90 % size of 32-nm node. For 28-nm node, binary masks or att. PSMs are to be used based on the requirements for each layer.

：

*[email protected]; phone +81-42-771-0678; FAX +81-42-771-0896; www.necel.com Advances in Resist Materials and Processing Technology XXVI, edited by Clifford L. Henderson, Proc. of SPIE Vol. 7273, 72733A · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.813498

Proc. of SPIE Vol. 7273 72733A-1

Table 1: Tentative minimum pitch used in 32-nm and 28-nm node logic devices Pattern

32 nm node

28 nm node

Metal

100 nm (HP 50 nm)

90 nm (HP 45 nm)

Contact

126 nm

113 nm

SRAM cell size

0.150 µm2

0.120 µm2

In this work, we explore ways to realize robust resist processes for logic devices at the 32-nm node and beyond. We will point out the effects of strong resolution enhancement techniques (RET) on resist patterning performance for L/S (Section 2). We then examine process window enhancement techniques for hole patterning (Section 3). The impact of each component on the process instability is examined and ways to balance the different performance requirements for 32-nm node and beyond are then presented.

2.

LINE AND SPACE PATTERNING

2.1. Lithography condition requirements in line and space pattering for 32-nm node and beyond The impact of line width roughness (LWR) on logic device reliability under low-k1 conditions is significant. In particular, LWR at the densest pitch in Cu wiring is important for better yield. In Fig.1, 50-nm HP L/S patterns for 32nm technology node are shown. In this experiment, we intentionally change the exposure-focus offset for each wafer. The LWR worsens with defocus due to deteriorating image contrast as shown in Fig.1. Fig.2 shows the break down voltage for 50-nm HP Cu wiring for 10-meter-length pattern with meander. The break-down voltages are measured at 96 points within the wafer. At the center and +25 nm defocus settings, the yields are 100 %. However, as shown in Fig. 2, on the +50 nm defocus setting wafer, the yield worsens and some shots have low break down voltage. Better LWR is the key to the better logic device reliability. Therefore, sufficient image contrast at the densest pitch is essential.

Focus offset setting Center

+ 25 nm

LWR 4.5 nm Max-Min 6.7nm

LWR 5.0 nm Max-Min 7.2 nm

+ 50 nm

HhIIIIIO LWR 5.8 nm Max-Min 8.7 nm

Fig. 1: The LWR change with defocus for 50 nm HP L/S patterns.

Proc. of SPIE Vol. 7273 72733A-2

Effect of LWR on yield

1 cii) iw'w,s

cap Cu

Cu

low-k

SiO2

50nm space

MUflJO

Yield 93% Defocus + 50 nm

Yield 100%

Defocus 0nm

Defocus + 25 nm

S

S

r0

0

※Cu wiring parallel length 10 meter with meander, 96 points are measured on a wafer. Fig. 2: Cu wiring yield with defocus setting (different LWR).

On the other hand, a wide variety of patterns are used in logic design. Thus it is necessary to fulfill the requirements for all patterns (Fig.3). As shown in Fig.3, for dense pitches, improved LWR and larger exposure latitude (EL) are critical. For this purpose, higher NA and larger sigma illumination conditions are needed. For the middle pitch and isolated pitch patterns, inner sigma and/or sub-resolution assist features (SRAFs) are used to improve DOF performance. For the device 2D layout including dense SRAM, it is preferable to use mild illumination settings in order to prevent pattern deformation, line end (LE) shortening and pattern collapse.

Dense pitches - LWR, low EL

Middle and iso pitches - Small DOF

higher NA+larger sigma

Inner sigma / SRAF

A wide variety of patterns in logic design Device 2D layout including dense SRAM - Pattern deformation /LE shortening - Pattern collapse Milder illumination setting Fig. 3: Balance in RET optimization is the key to better full chip yield.

Proc. of SPIE Vol. 7273 72733A-3

Annular

CQUAD Pattern orientation dependent OAI

1st order light 0th order light

50 nm HP

σ

(32 nm node) NA 1.35 0.8/0.6

(Th

45 nm HP

I

I

σ

(28 nm node) NA 1.35 0.9/0.7

I

I

I

I

I I

Fig. 4: The diffracted light in the pupil plane in the scanner. Stronger RET is required with pitch shrink.

The need for high contrast at the densest pitch leads to the use of stronger RET as shown in Fig.4. Fig. 4 shows the diffracted light within the pupil plane of the scanner. For 50-nm HP with NA1.35, 0.8/0.6 condition, a large part of the 1st order diffracted light is already out of the lens. However, even at this pitch, there is still some amount of interference between the 1st order and the 0th order diffracted light. In the case of 45 nm HP, there is only a small amount of interference between the 0th order light and the 1st order light with annular setting. To increase the contrast at 45-nm HP, the non-interfering light that degrades contrast is generally removed by changing the illumination shape. CQUAD illumination is known to be one of the solutions for better contrast at the densest pitches. The next question is what is the effect of stronger RET. In the following sections, the effects of RET types on real device patterns are examined.

σ

2.2. 2D Pattern deformation of line and space patterns The effects of RET types on two dimensional (2D) device patterns are examined for 32-nm logic node. Before starting the discussion of 2D layout pattern, lithography margins for one-dimensional (1D) patterns are calculated (Fig.5). The tables in Fig.5 show DOF simulated with thin-mask approximation in the presence of OPC and SRAF. The space and line widths are changed and DOF for each pattern is estimated. The red color indicates patterns with less than the DOF criteria of 120 nm. Thus, these patterns require design manipulation such as retargeting or removal from the design rule. When the differences between annular and CQUAD illumination are compared in 1D layout, no large differences are seen in pattern coverage.

°

Cquad35 NA1.3

Cu Line (nm)

Annular NA1.35

Cu Line (nm)

Criteria: DOF > 120 nm

DOF (nm) with OPC, SRAF Space between Cu line (nm) LS

0

63

0012O15017002iO33O40O0OO1X0

IC

5O2S92L2II3S;;3

47

t i 60f.23002S18?22

4.

4

J4

:. Need DFM. : F:::

80 1 120

20 249 300 S5 '6 13 I2S 128 136 144 42 130 132 C2 1 i 1C 18 2t6 W0 22' 211 2W 206 231 W 28 2!,, i 1i4 157 47 165 1 168 53 284 830 300 240 100 13!

SI

!01

100

mI

7(1

I

001 1201 1501

0I 2001 2flI

)0I 4001 600iiX01

Need DFM.

Exposure latitude 2%, ellipse window, mask variation impact is included.

Fig. 5: Lithography margin by 1D pattern simulation.

Proc. of SPIE Vol. 7273 72733A-4

. However, 2D-pattern shape is greatly affected by changing the illumination shape. Metal layer patterns in a high density 0.15-µm SRAM cell used in 32-nm node device are shown in Fig. 6. The illumination shape is changed from narrow 35degree opening-angle CQUAD to annular illumination. The same mask is used for all illumination shapes. We found that as the opening angle of the illumination pole widens, the 2D pattern shape fidelity improves. The line end shortening is more significant in narrow CQUAD illumination. From the mask manufacturability point of view, annular illumination is a preferable illumination shape at 100-nm pitch due to the fact that there is a smaller amount of LE shortening correction required.

High density 0.15 µm2 SRAM cell (32 nm node)

°

CQUAD OA35 NA1.30, XY pol. = 0.75/0.56

σ

°

CQUAD OA70 NA1.30, XY pol. = 0.75/0.56

σ

Annular NA1.35, XY pol. = 0.80/0.60

σ

Fig. 6: Effect of illumination shapes on high-density SRAM pattern shapes (local metal level) at best focus condition.

For the patterning results with defocus, the effect of illumination-shape difference is more pronounced, as shown in Fig. 7. For the case of CQUAD illumination, even when the pattern fidelity is relatively good at best focus, the pattern fidelity at defocus position is greatly affected. A hot spot that induces a trench-resist short is seen with +50-nm defocus in narrow-angle CQUAD condition. This effect could also be simulated by lithography simulator as shown in Fig. 7. Conversely, annular illumination does not severely change the resist shape and trench-resist shorting is not seen with the same defocus. These results suggest that 2D pattern deformation becomes more severe with stronger RET, especially at defocus conditions. The orientation dependency of the illumination shape is thought to impact the 2D pattern shape deformation.

°

CQUAD OA35 NA1.30, XY pol. = 0.75/0.56

σ

+50nm defocus

Annular NA1.35, XY pol. = 0.80/0.60

σ

Best focus

Simulation

Best focus

Simulation

Tm

10

+50nm defocus

+50 nm defocus

Lkin LJ

ii p I

+50 nm defocus

Hot spot

Fig. 7: Effect of illumination shapes on high density SRAM cell pattern shapes (local metal level) with defocus.

Proc. of SPIE Vol. 7273 72733A-5

2.3. Pattern Collapse The illumination shape effect on pattern collapse margin is examined next. The pattern collapse margin for 1D dense pattern is observed by changing the illumination shape. In Fig.8, the pattern collapse margin is compared between narrow-angle CQUAD and annular illumination at best focus condition. One step in dose corresponds to 3% dose from the nominal dose. The pattern collapse margin for 1D-layout L/S patterns shown in Fig. 8 is almost the same between the two illumination shapes. The pattern collapse starts from around 40-nm pattern size in both cases. From the normalized image log slope (NILS) simulated in the upper graph in Fig.8, we see that CQUAD has higher image contrast than annular illumination. By carefully analyzing the results in Fig. 8, it appears that the CQUAD condition shows slightly better pattern collapse margin with superior optical contrast in 1D layout.

a

50 nm L/S

a

a

HT mask, Maxwell simulation Annular NILS 1.63 < CQUAD NILS 1.84 Wa

At best focus, dose step 3%

crs :.. It .at fl It J7t:Yct ..t.at!a

CQUAD OA35

NAI.30, XY pol. = O.75IA.SR

IillhiIllIlliluiH ms;'a 49.9

Tht Alt L

UUUuIl IHHIiIItIillhIHIRIII

w:

W!IWacoiapsCoiiapse T

p

Fig. 8: Pattern collapse margin at 1D dense pattern of 50-nm line with a pitch of 100 nm at active layer.

CQUAD35

SRAM cell Active layer (Min pitch 95 nm)

43.8 nm

Annular 42.1 nm 95 nm pitch

Fig. 9: Pattern collapse margin at active layer in a SRAM pattern with minimum pitch of 95 nm.

Proc. of SPIE Vol. 7273 72733A-6

For pattern collapse margin in SRAM patterns, the trend is reversed, as shown in Fig. 9. The annular setting gives much wider pattern collapse margin than CQUAD for 2D SRAM layout. In the case of CQUAD illumination, the pattern collapse starts quickly from the 3% over-dose pattern. On the other hand, annular setting does not induce pattern collapse even at 9% over-dose condition in 2D SRAM layout. It is interesting to find the opposite tendency in pattern collapse in different pattern layouts. Although the contrast of CQUAD is higher for dense patterns, the pattern collapse margin is very small for 2D shapes. To understand the reason why CQUAD induces more pattern collapse than annular illumination in SRAM patterns, we calculated the aerial image with a lithography simulator, as shown in Fig. 10.

Aerial image intensity 95 nm pitch

6% over dose

Annular

CQUAD

Fig. 10: Aerial image calculation to understand the layout-dependent pattern collapse.

The mask pattern and the aerial image intensity distribution are shown in upper left graphs in Fig. 10. The aerial image intensity at the cut line is shown in the upper right graph. The interesting finding here is that at the cut line, the aerial image slope for CQUAD illumination is slightly smaller than that for annular illumination in the SRAM cell. This tendency is the opposite compared to the 1D pattern simulation results. Also the background light at the pattern area is higher for CQUAD. Therefore, the pattern collapse observed in SRAM patterns is considered to be due to lower contrast of the image and higher back ground light in the resist pattern. From the above experiments, we conclude that if the minimum pitch process window and LWR permits, it is advantageous to use the mildest illumination, which exhibits less pattern type dependency and leads to an increased design freedom. Also from the experiment, it is concluded that for minimum pitch L/S pattern in 32-nm node logic, annular illumination is appropriate for use on NA1.35 scanner when the resist contrast is enough. For the further shrink, the effect of stronger-RETs on 2D-pattern shape deformation and pattern collapse needs to be addressed.

3.

HOLE PATTERNING

3.1. Requirements in contact/via hole lithography for 32-nm node and beyond The difficulty in hole patterning is the small depth of focus due to the poor image contrast which is worse than that of L/S patterns. In this paper, as examples of methods for better process window (PW), the following two approaches are examined. – Integration process approach – hole shrink. – Resist contrast enhancement by controlling acid diffusion in an ArF chemically amplified resist.

Proc. of SPIE Vol. 7273 72733A-7

3.2. Process window enhancement with hole-shrink process As an integration process approach for hole process-window enhancement, hole-shrink technology is shown in Fig. 11. One of the methods to pattern the holes is the tri-layer approach in Fig. 11 (left figure). In this approach, the hole is first patterned in the resist. Then the hole pattern is transferred to SOG layer. Using the SOG layer as the hard mask, the bottom layer is patterned. Then finally the pattern is transferred to the patterning layer. As an alternative, the quad-layer approach is introduced as shown in Fig. 11 (right figure). In the quad-layer approach, a hard mask harder than SOG is used and a bottom anti-reflective coating (BARC) is spin-coated on top of hard mask layer to control the reflectivity. From our experience in introducing hole shrink during BARC / HM / under-layer etching steps, the etching bias is generally larger than tri-layer approach. Therefore a larger resist CD target can be used to achieve wider process windows. For the tri-layer process, we used 75-80 nm hole size in resist before etching to obtain the target hole size of 45 nm in patterning layer. For the quad-layer approach, we can now use 85-nm hole size in resist to achieve the same postetch patterning layer size

Quad-layer

Tri-layer Resist

Resist

SOG

BARC Hard mask

Bottom layer

Bottom layer

Patterning layer

Patterning layer

Resist CD 85 nm After Etching 45 nm

Resist CD 78 nm After Etching 45 nm

Fig. 11: Tri-layer and quad-layer approaches for hole layer patterning.

Fig. 12 is the results of process window enhancement with hole-shrink process for dense pitch patterns (120-nm pitch). The Bulls Eye illumination [6] is used in this experiment as described in Fig. 12. The hole-pattern process window for dense contact hole is already wide enough with tri-layer process. Slight process window enhancement is seen by introducing the quad-layer process. With the larger target resist size with the quad-layer process, the process window is slightly enlarged.

Dense pitch (120 nm pitch) Focus (tim)

Tn-layer Original target CD mm)

-75

I

-50

-25

Cente

4 ....t.,..., 44

S:S 88.8

73.1

75.5

78.6

s! : 4* 'ctX: 75.8 75S .; a;;

;;. . .. 4.. . .. .. .t.... 78.2

I

76.4

t> tftftQ j:'

Original target 70.4

711

100

75

x'ct

c.:o4,.4:.....t.4.:#svt,,... :c*:':c.

.'od

Quad-layer CD nm)

50

:.C.

74.6

77.6

77.0

I

76.5

: sc.'

75.8

I

74.8

Illumination： Bulls Eye （Soft Annular） NA=1.30; Annular σout 0.85, σin 0.64 + Conv. σ 0.2 Fig. 12: Comparison of process margins between tri-layer process and quad-layer process for 120-nm pitch dense patterns.

Proc. of SPIE Vol. 7273 72733A-8

Isolated hole (500 nm pitch)

CD tim

57.10

68.10

11.20 4

81.70

70.20

77.9

74.4

82.2

81J6

-

Quad-layer Original target 7.5

65.5

I

Quad-layer + 5 nm target fl 59.0

58.1

Fig. 13: Comparison of process margins between tri-layer process and quad-layer process for 500-nm pitch isolated patterns.

The process-window enhancement effect is more significant for isolated holes. The results for 500-nm pitch pattern are shown in Fig. 13. In the case of tri-layer approach, we only have a small process margin. With the use of quad-layer, the process window is enhanced slightly even when we use the same target size, perhaps due to reduced reflection in quadlayer approach. For the quad-layer process with a larger target size, the process window is expanded greatly. This confirms that the via shrink process with quad-layer approach enhances the process window of isolated-hole patterns which often have a small process window. 3.3. Hole-pattern process-window control by acid diffusion control In addition to the RET effort to obtain better contrast through-pitch, contrast enhancement on the resist side is also very important. Therefore, we examined a method to improve the process window by introducing precise acid diffusion control.

Mid Pitch P = 170 nm

℃

PAB / Nominal [email protected]%=128 PEB -5

PAB / +10

nm

MAX EL=16.9%

-j

℃ Wider PW

[email protected]%=102nm PEB

[email protected]%=129

nm

MAX EL=16.6%

Wider PW [email protected]%=101nm

MAX EL=14.0%

MAX EL=13.5%

Nominal

Fig. 14: Process window improvement by acid diffusion control; lower diffusion condition with higher PAB and lower PEB enhances DOF by 20

～30 nm.

The post-exposure bake (PEB) temperature is lowered to obtain a shorter acid-diffusion length that provides better resist contrast, as shown in Fig. 14. Fig.14 shows that the process window is expanded with the lower PEB temperature. An additional approach is the post-apply-bake (PAB) temperature increase to reduce acid diffusion by increasing the density

Proc. of SPIE Vol. 7273 72733A-9

of the resist film during PAB. In Fig. 14, no significant change is seen with the PAB temperature change. These kinds of optimization techniques using PAB/PEB temperature manipulation are quite common during lithography process development. However the importance of the fine tuning to obtain wider process window is increasing with each successive technology node.

[email protected]% [um]

Fig. 15 shows the results of bake-temperature change through pitch. Process-window enhancement by PAB/PEB temperature control is effective especially at looser pitch patterns. At the middle and isolated pitches where the DOF is small, the window is expanded greatly with the change of PAB/PEB temperature. At the densest pitch, the change in not significant but process window is already wide enough.

0.20

℃ / -5℃

PAB/PEB=Ref. PAB/PEB= +10

0.15 0.10 0.05 0.00 120

170

2000

Pattern pitch [nm]

Fig. 15: Hole-pattern process-window improvement through pitch.

We introduced examples of two methods to expand the hole-pattern process window in 32-nm node logic technology. Hole shrink during the etching step using a quad-layer-film stack, and employing resist-contrast enhancement through acid diffusion control both prove to enhance the process window of hole patterns. Other approaches such as focus drilling [7] will also help to enhance the process window. For the optimal process window in hole lithography for 32-nm node and beyond, it is necessary to combine all applicable approaches.

4.

SUMMARY

We reviewed the resist processing challenges for 32-nm node logic devices and beyond. Line and space patterning We examined ways to balance the RET requirements in order to obtain robust resist processes. In 32-nm node logic patterning, 2D-layout pattern deformation becomes more severe with stronger RET (e.g., narrow angle CQUAD illumination). Also, pattern collapse occurs more frequently in 2D pattern layout when stronger RET is used. Conversely, milder RET (annular illumination) does not induce the sever pattern collapse in 2D pattern layout. For 2D pattern layout, stronger RET seems to worsen image contrast and results in high background-light in the resist pattern, which induces more pattern collapse. From these results, we conclude that if the minimum-pitch process window and LWR permits, it is preferable to use the mildest illumination which gives less pattern type dependency. For the minimum pitch L/S pattern in 32-nm logic node, annular illumination with NA1.35 scanner is acceptable when high contrast resist is used. For further device shrink, the stronger RET effect on 2D pattern shape deformation and pattern collapse needs to be addressed. Holes patterning To achieve better yield in contact/via lithography, expanding the overlapping process window is required. We explored ways to widen the process window in 32-nm node logic. Better process margin is realized through the combination of a hole-shrink technique and precise acid-diffusion control. It is necessary to combine all the approaches to enhance the process window of hole patterns for 32-nm node and beyond because of the narrow process margin in hole patterning.

Proc. of SPIE Vol. 7273 72733A-10

ACKNOWLEDGEMENT We would like to thank Mr. Kenji Konomi, Mr. Shigeki Nojima, Mr. Masanari Kajiwara, Mr. Masayuki Miyairi, Ms. Tomoko Ojima of Toshiba, Mr. Masayuki Fukushima of NEC Electronics, Jyunji Yoshioka of VSN and the other members of the joint development program between Toshiba and NEC Electronics, Mr. James Bonafede of Cymer Japan, materials and tool vendors for their support in this work. We are also grateful to Mr. Kiyoshi Fujii, Mr. Tomohisa Kitano, Mr. Shuichi Inoue of NEC Electronics and Mr. Soichi Inoue, Dr. Tatsuhiko Higashiki of Toshiba Corporation for their advice and encouragement in this work. This work is an outcome from the joint development program between Toshiba and NEC Electronics.

REFERENCES [1] Kazuhiro Takahata, Masanari Kajiwara, Yosuke Kitamura, Tomoko Ojima, Masaki Satake, Hiroharu Fujise, Yuriko Seino, Tatsuhiko Ema, Manabu Takakuwa, Shinichiro Nakagawa, Takuya Kono, Masafumi Asano, Suigen Kyo, Akiko Nomachi, Hideaki Harakawa, Tatsuya Ishida, Shunsuke Hasegawa, Katsura Miyashita, Takashi Murakami, Seiji Nagahara, Kazuhiro Takeda, Shoji Mimotogi, and Soichi Inoue, “Patterning performance of hyper NA immersion lithography for 32nm node logic process”, Proc. SPIE 7140, 714017 (2008). [2] Tatsuhiko Ema, Koutaro Sho, Hiroki Yonemitsu, Yuriko Seino, Hiroharu Fujise, Akiko Yamada, Shoji Mimotogi, Yosuke Kitamura, Satoshi Nagai, Kotaro Fujii, Takashi Fukushima, Toshiaki Komukai, Akiko Nomachi, Tsukasa Azuma, and Shinichi Ito, “Immersion resist process for 32-nm node logic devices”, Proc. SPIE 6923, 69230E (2008). [3] Shoji Mimotogi, Masaki Satake, Yosuke Kitamura, Kazuhiro Takahata, Katsuyoshi Kodera, Hiroharu Fujise, Tatsuhiko Ema, Koutaro Sho, Kazutaka Ishigo, Takuya Kono, Masafumi Asano, Kenji Yoshida, Hideki Kanai, Suigen Kyoh, Hideaki Harakawa, Akiko Nomachi, Tatsuya Ishida, Katsura Miyashita, and Soichi Inoue, “Patterning strategy and performance of 1.3NA tool for 32nm node lithography”, Proc. SPIE 6924, 69240M (2008). [4] S. Hasegawa, Y. Kitamura, K. Takahata, H. Okamoto, T. Hirai, K. Miyashita, T. Ishida, H. Aizawa, S. Aota, A. Azuma, T. Fukushima, H. Harakawa, E. Hasegawa, M. Inohara, S. Inumiya, T. Ishizuka, T. Iwamoto, N. Kariya, K. Kojima, T. Komukai, N. Matsunaga, S. Mimotogi, S. Muramatsu, K. Nagatomo, S. Nagahara. Nakahara, K. Nakajima, K. Nakatsuka, M. Nishigoori, A. Nomachi, R. Ogawa, N. Okada, S. Okamoto, K. Okano, T. Oki, H. Onoda, T. Sasaki, M. Satake, T. Suzuki, Y. Suzuki, M. Tagami, K. Takeda, M. Tanaka, K. Taniguchi, M. Tominaga, G. Tsutsui, K. Utsumi, S. Watanabe, T. Watanabe, Y. Yoshimizu,T. Kitano, H. Naruse, Y. Goto, T. Nakayama, N. Nakamura and F. Matsuoka, “A Cost-Conscious 32nm CMOS Platform Technology with Advanced Single Exposure Lithography and Gate-First Metal Gate/High-K Process”, Proc.IEDM2008, p.938 (2008). [5] Shoji Mimotogi, Fumikatsu Uesawa, Makoto Tominaga, Hiroharu Fujise, Koutaro Sho, Mikio Katsumata, Hiroki Hane, Atsushi Ikegami, Seiji Nagahara, Tatsuhiko Ema, Masafumi Asano, Hideki Kanai, Taiki Kimura, and Masaaki Iwai, “Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25 um2”, Proc. SPIE 6520, 652008 (2007). [6] Jo Finders, Andre Engelen, Geert Vandenberghe, Joost Bekaert, and Tim Chen, ” Experimental evaluation of BullsEye illumination for assist-free random contact printing at sub-65nm node”, Proc. SPIE 6154, 615412 (2006). [7] Alek Chen, Steve Hansen, Marco Moers, Jason Shieh, Andre Engelen, Koen van Ingen Schenau, and Shih-en Tseng, “The random contact hole solutions for future technology nodes”, Proc. SPIE 6520, 65201B (2007).

Proc. of SPIE Vol. 7273 72733A-11