JOURNAL OF ELECTRONIC TESTING: Theory and Applications 22, 11–22, 2006 c 2006 Springer Science + Business Media, Inc. Manufactured in The United States. DOI: 10.1007/s10836-006-4835-z
Scaling of iDDT Test Methods for Random Logic Circuits ALI CHEHAB American University of Beirut, Beirut, Lebanon
[email protected]
SAURABH PATEL University of North Carolina at Charlotte, Charlotte, NC 28223, USA RAFIC MAKKI College of Information Technology, UAE University, AL-Ain, UAE
[email protected]
Received December 21, 2003; Revised September 7, 2005 Editor: Z Li
Abstract. We present a scaling methodology to improve iDDT fault coverage in random logic circuits. The study targets two iDDT test methods: Double Threshold iDDT and Delayed iDDT . The effectiveness of the scaling methodology is assessed through physical test measurements, and studied relative to process variation and impact on circuit performance. The scaling is made possible using a clustering methodology that can significantly improve fault coverage. The results show that without clustering, the effectiveness of the iDDT testing methods considered is greatly reduced as the circuit size increases. Keywords: dynamic power supply current, design for current testability, resistive opens, resistive bridges, fault simulation, very deep sub-micron technologies, VDSM
1.
Introduction
Recent iDDT research has shown potential for iDDT testing to augment traditional test methods and increase fault coverage. Simulation results have shown that iDDT can successfully detect floating gate defects, source/drain open defects [13, 24], as well as cell transition and coupling faults in SRAM’s [11]. In a recent study, the transient response is analyzed in the time domain at distributed measurement points [6, 18, 19]. In [20], the transient response is transformed into the frequency domain where correlation and regression analysis are performed; the transient signal analysis method incurs increased measurement and computational complexity due to multiple test point measurements. Other researchers proposed to determine the average value of the transient current to successfully detect stuck-open defects [15]. Studies have also shown that the Energy Consumption Ratio, ECR, [2, 27] can be used to detect defects. This method performs average current measurements of a number of sequences and computes the corresponding ECRs. Each ECR has a corresponding pre-computed good circuit
average. The ECR is process tolerant; however, one aspect of this method is the increased test time due to large number of applied test vector pairs. Also increased leakage currents in today’s circuits affect the average current and limit the effectiveness of the test. Statistical formulation of thresholds for iDDT is proposed in [7]. In [21], a technique is proposed that is based on the golden signature of the DUT and whereby one sample of iDD is taken per test vector at a predetermined instance. In [8], a hardware solution of an iDDT monitor is presented that allows real-time testing for 0.25 micron CMOS devices. In [23] a method is presented that is based on measuring and computing the charge delivered during the transient operation. In this technique the area under two different waveforms, one for a good circuit and another for a defective circuit, may lead to very close results even though one circuit is defective. Also, similarly to ECR, its resolution reduces with very large values of leakage. In [28] a method is proposed based on the fact that some open defects cause delay faults and that such faults will cause iDDT to have a delayed peak, and a longer duration. By setting the observation window past the good circuit transition
12
Chehab, Patel and Makki
time, the delayed iDDT peak can be detected, and hence the defect inferred. In this paper we present a new iDDT test method based on measuring the peak magnitude of the iDDT pulse, aimed at providing a simple binary type of a test, wherein if the iDDT response is greater than a target high or less than a target low, a defect is inferred. A clustering method is introduced, that allows for the scaling of the test method. In addition, we apply the clustering method to the delayed- iDDT test method and show that it can significantly enhance test coverage. This paper is organized as follows: (1) The Doublethreshold iDDT test method is introduced and the Delayed iDDT (Section 2) test method is revisited, (2) An iDDT ATPG (Section 3) is developed and applied to ISCAS benchmark circuits for the purpose of studying the effectiveness of the above two test methods as circuit size increases; (3) Fault simulation results are presented in Section 4; (4) a method is presented for scaling the proposed iDDT methods to larger circuits (Sections 5 and 6); (5) Physical test results are presented (Section 7), and general observations are made (Section 8). 2.
Test Methods
The two methods that we consider are based on the peak magnitude of iDDT , and these are: Double Threshold iDDT method, and the Delayed iDDT method [4]. 2.1.
Double Threshold iDDT
This method is based on the observation that a good circuit will always have a lower bound and an upper bound of peak iDDT values in response to a select set of applied input vectors. If a circuit draws a peak iDDT value that is either lower than the lower bound or higher than the upper bound (allowing for variances and noise), a defect is inferred. Fig. 1 shows a circuit under test, which is equivalent to a 4-input NOR, Fig. 2 shows the transistor-level schematic of the CUT, and Fig. 3 shows the result of good circuit simulation. Fifteen vectors were applied to the CUT every time going back to vector “0000” before applying the new vector. Each pair of 2 adjacent columns represents the peak values of iDDT for each test vector pair. The two horizontal bars represent the maximum and minimum values of these peaks. Note that every pulse has duration of 5 ns and fall and rise times of 1 ns each. A complete cycle has a total duration of 1 ns (rise) + 5 ns (high) + 1 ns (fall) + 5 ns (low) = 12 ns. So the operating frequency is about 83 MHz. We can see that the peak values of the iDDT spikes range from 220 to 350 µA. A resistive open of 100 K at the gate of the PMOS transistor P7 in Fig. 2, will produce, in response to vectors “1000” and “0000” two iDDT spikes with values of 327 and 147 µA respectively. The second spike is 33% lower than the lower bound (220) and hence such a defect can be detected
Fig. 1.
Circuit under test.
using the double threshold iDDT method. The threshold setting will be described in Section 4.3.
2.2.
Delayed iDDT
A good circuit is normally expected to switch, and hence to draw an iDDT pulse within a specific time interval. Outside such an interval, no pulse should be observed. This time interval is dictated by the circuit’s speed and by the frequency of operation. If a particular defect causes a delay in the circuit’s response, this delay will be reflected in a delayed iDDT pulse. If the delay is unacceptable, it can shift the iDDT pulse outside the window of observation as shown in Fig. 4. If we shift the window of observation past the time where a good circuit is supposed to switch, then this pulse—if it has an appreciable magnitude—will be detected. As an example, a 1 M resistive open between the NAND gate and the first inverter of Fig. 1 will cause the output to be delayed by 3.7 ns and hence it causes an iDDT spike during this time. If we move the window of observation past 2 ns, this spike will be detected and the defect is considered as detected. Setting the time interval of the window of observation is discussed in Section 4.3
2.3.
Preliminary Testing Results
The correlation between resistive opens/bridges and each of the 2 methodologies were initially investigated by the manual insertion of resistors in the circuit shown in Fig. 2. The resistors were inserted at different locations in the circuit and with different resistor values, simulating the effects of opens and shorts as well as benign faults that do not affect the voltage or delay performance of the circuit. Table 1 summarizes the results and provides the detection percentage of the complete test set that detects all of the single stuck-at faults in the circuit of Fig. 1. The results of the simulations show that for the circuit under analysis, the Double Threshold iDDT method performs very well and is capable of detecting all the defects that were introduced at the transistor terminals and that are causing a delay of 0.5 ns or more. As for the Delayed iDDT method, it can detect resistive opens that cause a measurable delay value.
Scaling of iDDT Test Methods for Random Logic Circuits
3. 3.1.
Fig. 2.
Transistor-level schematic of CUT.
Fig. 3.
Double-threshold iDDT test method.
ATPG Algorithm for iDDT Testing Rationale
By referring to Fig. 1, for example, we see that there are 9 nets in the circuit. A resistive open can take place at any of these nets, and a resistive bridge can take place between
Table 1.
any two nets or between a net and a supply line. In order to have the maximum possible fault coverage when applying the above-mentioned iDDT -based methods, we need to have a set of test vector-pairs that can exercise all the appropriate nets in the circuit under test in a similar manner to transition fault testing [5, 9, 22, 26]. However, in transition fault testing, the voltage is being observed instead of the transient
Fault detection percentage of three different test methods. Number (percentage) of defects detected by: Number of Stuck-at test defects method
13
Double threshold iDDT
Delayed iDDT
Number of defects not detected by any method
Resistive opens
40
12 (30%)
38 (95%)
24 (60%)
1 (2.5%)
Resistive shorts
9
7 (78%)
8 (89%)
9 (100%)
0 (0%)
14
Chehab, Patel and Makki The ATPG program is implemented based on the following main steps:
Fig. 4.
Delayed- iDDT test method.
current, and the fault needs to be propagated to a primary output, which is not required for iDDT testing. Also we need to automate the process of test vector-pairs generation to make it practical to be applied to large-size circuits. Hence, we propose a new ATPG algorithm for the generation of test vector pairs for iDDT testing, and in the following subsection we describe the algorithm and its implementation in software. Note that manufacturing defects and early-life failures in DSM technologies can lead to opens and bridges [1]. We are targeting resistive opens and bridges since on one hand, resistive opens are said to comprise the bulk of defects that escape the test phase of the manufacturing flow [17], and on the other hand, the probability of resistive bridges increases with decreasing feature sizes. We consider that a resistive defect can occur at any interconnect between transistors as well as at every transistor terminal. In order to test for such defects, it is essential to switch every net in the circuit, and hence every gate input and output in the circuit.
3.2.
Algorithm Description
The selection of the vector set follows the following criteria: • Each test vector consists of two vectors, the application of which will activate at least one net in the circuit. One vector will set the target-net to a logic value of 1 while the second vector will set the same net to a logic value of 0. This leads to transition from 1 to 0. However, the technique will work equally if we make a 0 to 1 transition. • While targeting a specific net, a test vector-pair should be chosen in a way that minimizes the number of the switching gates and hazards elsewhere in the circuit. This condition is important to minimize the peak value of iDDT , which will allow for the distinction between the peak iDDT values of a defective circuit and a fault-free circuit. This is another difference with the vector pair generation for transition fault testing. • The vector set should activate every net in the circuit (for maximum fault coverage), yet it should contain a minimum possible number of input vectors (to reduce the test length).
• Parse the netlist file that is in benchmark format • Construct a reference model of the logic circuit using an appropriate set of data structures. • Select a minimum set of paths covering all the nets in the circuit. • For every selected path, generate a test vector-pair that tries to sensitize this path while minimizing switching elsewhere in the circuit. There is no need to sensitize the complete path as in transition fault testing because we are measuring iDDT and we don’t have an observability problem. However, we try to sensitize the whole path in order to minimize the total number of required test vectors. • Eliminate redundancy from the set of test vector-pairs. The netlist of the circuit under test is described in benchmark format (“∗ .bench”), and it is preprocessed to replace each multi-input gate with an equivalent set of 2-input gates. Note that benchmark circuits are available in a netlist format that includes, for example, gates such as a 9-input AND gate. The mapping to a CMOS technology requires changing the gates in the netlist to other gate types available in CMOS. We chose to use 2-input gates to increase the size of the circuit, and to have more locations as defect candidates. The testability results are not affected by this transformation; in fact, for a CMOS implementation that uses 3 and 4-input gates, the off-path switching may be reduced. The 2-input gate implementation is actually a worst-case condition to iDDT testability. In order to minimize the number of test vectors that need to be generated, it is important to select a minimum number of paths, among all the available paths of the CUT, that cover all the nets in the CUT. In other words, every net in the circuit has to belong to, at least, one path of this minimum set. The issue of minimum set of paths selection has been addressed in [10, 12, 14]. In our case, a new attribute is introduced and shall be designated as “access”. This attribute will be associated with every input as well as output of every gate. It represents the accessibility of a particular net from the set of primary inputs. It is somewhat similar to the “controllability” except that it is computed differently, and it shall be used in the calculation of the minimum set of paths to be exercised. In other words, the values of “access” will represent the number of times a particular net should be accessed in order to cover all the nets in the circuit with minimum redundancy, i.e. with the minimum possible number of paths. The rules for computing the “access” values of a gate are shown below: Rule 1: If a gate input is connected to a primary input, its “access” value is set to 1.
Scaling of iDDT Test Methods for Random Logic Circuits Rule 2: The “access” value of a gate output is set to the sum of the “access” values of all of the gate inputs. Rule 3: If the input, Ix, of a gate, Gx, is connected to the output of a gate, Gy, the access value of Ix is computed based on the fanout, Fy, and access, Ay, of the gate Gy according to the following:
If (Fy = 1) then access(Ix) = access(Gy) = Ay If (Fy >= Ay) then The first Ay fanout branches of Gy will have an access of 1 while the remaining (Fy−Ay) fanout branches will have an access of 0. If (Fy < Ay) then Each fanout branch will have a minimum access value of 1 such that the sum of access values of all fanout branches is equal to Ay.
The minimum number of paths that need to be exercised is first set to the sum of the fanout values of all primary inputs, Sf. Every primary input will be associated with a value, “num vectors” representing the number of vectors that need to originate from this primary input. Originally, the value of “num vectors” for a particular PI is set to the value of its fanout. Then, for every gate in the circuit, if its fanout value is greater than 1, and if the fanout is greater than the access value, we augment Sf by the difference between the fanout and access values of this gate. Then, we reflect this difference to the “num vectors” of the primary inputs as we back trace from the specific gate. After scanning all the gates in the circuit, the sum of final values of “num vectors” for all PI’s will be the number of paths that need to be exercised. After selecting a minimum set of paths to be exercised, we generate for every path a vector-pair that tries to exercise this path. The vector-pair is supposed to activate the selected path from the primary input to the primary output. In other words, the vector-pair will set to complimentary values the various nets along the target path. This algorithm was applied to the ISCAS’85 benchmark circuits and the results are shown in Table 2: The first row indicates the ISCAS circuit, and the second row shows the number of gates in the corresponding circuit. The third row indicates the number of selected paths that are needed to cover all nets. The fourth row shows the total number of nets that were activated in response to the applied vectors. The last two rows provide the original and reduced number of vector pairs generated by the ATPG, respectively.
Table 2.
15
ATPG results on ISCAS’85 benchmark circuits.
ISCAS’85
C17
C432
C880
C3540
No. of gates
6
160
383
1,669
2,307
3,512
Selected paths
6
113
262
1,008
2,157
3,146
Activated nets
12
393
770
3,241
4,870
6,464
Original # V–P
6
113
262
1,008
2,157
3,146
Reduced # V–P
6
79
93
409
1,006
521
4. 4.1.
C5315
C7552
Fault Simulation Using ATPG Vectors Fault Models
The targeted defects are resistive opens and resistive bridges at the transistor level. A 1 M resistor value was used to model some resistive opens, as they would insert delays in the circuit and not necessarily cause a catastrophic failure on the signal. Some opens were also modeled as capacitive opens employing parasitic capacitance values. Resistive bridges were modeled with a 10 resistor connecting two nodes. The values of resistors for the defects were chosen in a way not to introduce catastrophic effects on the circuit performance. 4.2.
Fault Simulation Setup
For fault modeling, the circuits were simulated using SPICE. The SPICE models employed parameters from the TSMC035 process. The Drain/Source perimeter parameters were added to the SPICE models to give better accuracy in simulations. The simulations also included the effect of wire bonding (via a 2 nH inductance) and a bypass capaciance of 1 pF. The iDDT was recorded by looking at the voltage drop across a resistor on the branch of the supply line connected to the circuit. 4.3.
Threshold Setting
In order to set the threshold values for both the double threshold method and the delayed iDDT method, we first considered the response of the good circuit to the complete set of test vector pairs. For the double threshold technique, we note the maximum and minimum peak values of iDDT , and for the delayed technique, we measure the maximum delay of the iDDT pulse. Next, we adjust these values in order to account for process variations. We collected 26 different transistor model libraries from the MOSIS website for different fabrication runs (actual measured values) of the TSMC fabrication process. We applied these different process parameters to an inverter circuit, and we simulated a 0-to-1 and 1-to-0 transitions and we measured the variations in the iDDT responses. The results show a maximum variation of peak iDDT from
16
Chehab, Patel and Makki
Table 3. Fault type
Fault simulation of C432.
Table 4.
# Faults
Delay detects
Threshold detects
Line
40
29 (72.5%)
23 (57.5%)
Line
50
18 (36%)
17 (34%)
Gate
29
21 (72.4%)
16 (55.1%)
Gate
58
20 (34.48%)
19 (32.7%)
the average value by 25%. As for the iDDT pulse delay, the results show a maximum delay of the good iDDT pulse of 0.274 ns and a maximum of 18% change, with pulse duration of 1.105 ns. Hence, for the double-threshold test method, the upper threshold was set to the maximum iDDT in addition to a 25% margin accounting for process variations (i.e. for a max of 100 uA, the upper threshold was set to 125 uA). Similarly, the lower threshold was set to the minimum iDDT value with 25% margin below it. A fault is detected if the iDDT response is beyond these thresholds (i.e. higher then the upper threshold or lower than the lower threshold). As for the delayed iDDT , the threshold was set in this experiment to 2 ns from the application of the test vector. If a fault causes an appreciable pulse to appear beyond this window (after 2 ns) it would be considered as detected. This time window value was selected based upon the capabilities of the target iDDT sensor [3] in capturing transients. This value should be adjusted depending on the sensing circuit/method characteristics that are employed.
4.4.
Simulations
Next, we performed fault simulations by introducing defects into various locations and along different paths of the C432 (priority decoder) and the C880 (ALU and Control) ISCAS’85 benchmark circuits. A separate SPICE simulation was performed to assess the detectability of each of these defects. The operating frequency of the experiments is about 83 MHz whereby each pulse has a duration of 5 ns, and the rise and fall times are each of 1 ns duration. The simulation results are shown in Tables 3 and 4 for the C432 and C880 ISCAS circuits respectively. The first column refers to the general location of the fault (a line defect implies a defect along an interconnect, and a gate defect implies a defect at a gate terminal). All defects were at the transistor level, and none of the open defects could be detected by stuck-at tests because the fault models used emulated cracks (see Section 4.1), and resulted in no change in the gate-level logic values. The third and fourth columns give the detection percentages for the delayed iDDT and threshold iDDT methods, respectively. The following observations are made: – The fault coverage of the double threshold method decreases as the circuit size increases; it went from 57% for the C432 circuit line defects to 36% for the C880 circuit.
Fault type
Fault simulation of C880. # Faults
Delay detects
Threshold detects
– The fault coverage of the Double Threshold method can be improved if the following conditions are satisfied: – Reduce the number of iDDT spikes per transition – Reduce the variations of the peak iDDT values among all test vectors. The next section describes a method that addresses the above conditions.
5.
Clustering Algorithm
In order to improve the defect detection of the double threshold iDDT method, we can organize the gates in the circuit into different clusters. This does not involve physical partitioning. It only involves distributing different branches of the supply line to different groups of gates. Hence, the iDDT response from each cluster can be monitored separately. The gates will be grouped in a way such that the maximum number of switching gates in one cluster, in response to the vectors generated by the ATPG, does not exceed a specific parameterized value. We can then monitor the individual iDDT response on a cluster by cluster basis (see Section 9 for a discussion on practical implementation of measuring iDDT from different clusters). First, we apply the test vectors generated by the ATPG to the defect-free circuit. For every vector-pair we note which nets in the circuit switched in response to this vector pair and we store the switching information in a 2-dimensional array. The reason why we note which net switched and not which gate is that because even if a gate does not switch, a switching input can cause a glitch and hence contribute to the iDDT pulse. For the C432 circuit, for example, with 79 vector-pairs and 217 gates, the dimensions of the array are 79 by 217. Every element, Eij in the array is set to “1” if vector-pair Vi switches any input in gate Gj , and set to “0” otherwise. The range of subscript “i” is [1–79], and the range of subscript “j” is [1–217]. After running all the vector-pairs on the C432 circuit and checking the switching gate-inputs, the array would be similar to the one shown in Table 5. Next, we try to group the gates into different clusters. Note that for every subset of gates belonging to one cluster, there corresponds a subset of vector-pairs that will be used to test the gates in this cluster. The criterion for clustering is that the number of switching gates in a cluster, in response to any vector-pair in the corresponding subset of vector-pairs, does not exceed a certain maximum value.
Scaling of iDDT Test Methods for Random Logic Circuits The clustering algorithm was implemented in software. The program was first tested on the C432 circuit and the results for different parameter values of maximum switching gates per cluster are shown in Table 6. The first column indicates the maximum number of allowed switching gates per cluster. The second column shows the total number of clusters, and the third column shows the number of gates in every cluster. Note that the number of gates in the various clusters is not balanced. If one is interested in a more balanced set of clusters where all the clusters will have more or less the same number of gates, we can do the following:
Table 7.
17
Examples of balanced clustering for C432.
MSG
MAC
#C
Number of gates per cluster
18
–
5
116 47 19 18 17
18
40
6
40 40 40 40 33 24
22
–
5
130 42 22 22 1
22
50
5
50 50 50 35 32
1. Run the algorithm with only 1 criterion: the maximum number of switching gates in a cluster should not exceed a predefined value. This will provide us with a minimum number of clusters, N 2. Re-run the algorithm with a second criterion: The total number of gates in a cluster should not exceed a number M, such that: M ≈ (Total Number of Gates in the Circuit)/N 3. Adjust M such that the number of clusters is close to N, yet the number of gates per cluster is more balanced than the solution in step 1.
Fig. 5. Table 8.
3-D balanced clustering plot for C880.
Fault detection comparison C432
When one applies this modified technique to the C432 circuit, one obtains more balanced number of gates per cluster, an example of which is shown in Table 7 where the second column indicates the maximum number of allowed gates per cluster. The balancing feature is also illustrated in the 3-D plot of Fig. 5, showing the number of gates per cluster for different values of switching gates per cluster for the C880 circuit. Table 5.
Vectors and switching-gates relationship. G1
G2
G3
...
G216
G217
V1
1
0
1
...
0
1
V2
0
1
0
...
1
0
...
...
...
...
...
...
...
V78
1
1
0
...
1
1
V79
0
1
1
...
0
1
Table 6.
C880
Delay
Threshold
Delay
Threshold
Pre-clustered
72.46%
57.90%
35.20%
30.23%
Post-clustered
78.00%
92.00%
80.23%
91.86%
6.
Fault Simulation and Cost of Clustering
The fault models of Section 4.1 were used for the clustering simulations. Also the simulations setup of Section 4.2 was employed. In order to verify the improvement in the Double Threshold iDDT method due to clustering, we apply the clustering technique to the C432 and the C880 circuits. Next, we perform fault simulation on the C432 and the C880 circuits with clustering. The C432 had 4 clusters and the C880 had 11 clusters after clustering. The results are summarized in Table 8. It can be seen that significant fault coverage improvement was attained after clustering.
Clustering results on C432.
MSG
#C
Number of gates per cluster
7
13
63 35 24 23 16 9 7 7 7 7 7 7 5
10
9
82 39 29 18 10 10 10 10 9
12
8
92 42 29 13 12 12 12 5
14
7
100 45 24 15 14 14 5
18
5
116 47 19 18 17
23
4
133 41 23 20
6.1.
Cost of Clustering
Clustering does not involve the addition of any partitioning circuitry. It does however affect the way in which power is distributed, which may increase the supply routing area. One problem in any power distribution method is that different power nodes within the circuit might be at slightly different power levels due to variances in power supply fanout branch resistances. There are several methods/tools that can be used
18
Chehab, Patel and Makki
to help alleviate this problem [16] and clustering will add another constraint to these tools. The fact that recent designs use global power grid makes the routing overhead minimal for gates that are to be included in the same cluster if they are physically placed close to each others. An additional routing overhead occurs when we need to group gates in a particular cluster if they are not physically close to each others. However, this overhead can be reduced in two ways: The first is pre-placement, whereby one of the objectives of the placement algorithm would be to place gates that are in the same cluster close to each other. The second is post-placement. In this case, the clustering algorithm would take into consideration the relative position of the gates when grouping them in a cluster, and giving a preference to gates that are in close proximity. Combining the two suggested methods would result in a reasonable constraint to be imposed on routing when detecting defects that cannot be otherwise detected by traditional testing techniques. However, in order to study the effect of clustering on circuit performance, we performed SPICE simulations of ISCAS benchmarks and observed the power network noise performance. The generally accepted constraint for optimum circuit performance states that: “At any node in the power network, the voltage drop should not exceed 0.9V DD ”. This constraint is set because the minimum high and maximum low digital levels are defined as 0.9VDD and 0.1 VDD respectively. For simulating the power network, an algorithm was developed to extract all parasitics of the network and generate a netlist in SPICE format. The algorithm extracts all power network parasitics based on the user specified width and the specified fabrication process. Routing resistance is calculated by the amount of squares in the total length of the network branches (corner rectangles are counted as less than a square of resistance as electrons near the inside corner travel a shorter distance than the electrons on the outer corner). Parasitics for metal1 were taken for this calculation. The total capacitance of each branch is the sum of the area and fringing capacitances. Metal1-to-substrate capacitance parameters were used for this calculation. The algorithm was not optimized for best-case power networks, as the idea of this study was to carry out worst-case analysis. Three benchmarks were studied and the simulation results for each circuit are shown in Table 9. From the table, it can be seen that simulations for the given circuits showed that the maximum voltage at any Table 9.
node did not fall below the specified 0.9VDD limit. Fig. 6 shows a sample simulation pool for C3540 with a 12λ wide power network. In the figure, the x-axis represents the xcoordinate of a node on the power network and the z-axis represents the voltage drop across the node. (Note: the yaxis, representing the y-coordinate of a node, is not shown to reduce complexity of the figure). From the figure, it can be seen that there are only a few nodes that act as outliers (having a voltage level under 4.9 V). The simulated circuits were relatively small in size compared to many industrial circuits but they give a general idea on how circuits would perform when clustered. It can also be stated that since these were not the best-case power networks, the results would be much improved for best-case power networks. Simulations on industrial sized circuits are the next step in checking the viability of the clustering approach.
7.
Physical Testing for iDDT
The clustering algorithm was applied to the ISCAS C432 circuit. We then selected the cluster with the largest number of switching gates for implementation using the MOSIS 0.5 µm CMOS (AMI05) process. Two chips were designed: one containing a defect-free cluster of the C432 and the other containing the same cluster but with built-in defects. The transistors within the cluster were sized to 20λ × 4λ. Fig. 7 shows a block diagram of the two chips. Two identical clusters having different defects were implemented as shown in Fig. 7(b). The cluster was formed using the clustering algorithm described earlier. Table 10 shows the profile of the cluster. A maximum of 23 gates switch in response to the test vectors generated by the ATPG. Table 11 shows the built-in defect profile. These defects were placed strategically to ensure that they do not mask each other during testing. Two of the defects were placed along the same transition path. Both defects Table 10.
Cluster profile.
Total number of gates
70
Max. switching gates
23
Number of primary inputs
36
Clustering effect on circuit performance. Minimum voltage level at any node
Benchmark name
6λ wide power network
12λ wide power network
Configuration
C880
4.68 V
4.82 V
6 clusters, max switching gates 35 per cluster
C1355
4.78 V
4.86 V
8 clusters, max switching gates 45 per cluster
C3540
4.57 V
4.75 V
15 clusters, max switching gates 85 per cluster
Scaling of iDDT Test Methods for Random Logic Circuits
Fig. 6.
19
Voltage levels of power nodes of the C3540.
Table 11. Defect 1 2 and 3 4 and 5 6
Summary of defect types Defect type and placement Pull-down drain open 2 Double floating gates 2 Pull-up drain opens Single floating gate in pull-down circuit
are excited by a common vector-pair test set. In total, the defect distribution allowed us to study the effect of isolated individual defects as well as defects that might fall along a common excitation path. 7.1.
Fig. 7. Fabricated chips with (a) good cluster and (b) defective clusters.
Test Set-up
A Tektronix TLA720 Tester was utilized for test generation and the output data was analyzed via a Tektronix TDS6604 Digital Storage Oscilloscope. This scope has the capability to measure signals at speeds of 6 GHz and can take 20 Gigasamples/s. The chips were fabricated through MOSIS. Three DIPs were fabricated and tested. To measure iDDT , an external resistor of 1 k was connected between the chip supply pad and the power supply. The voltage drop across the resistor was measured as indicative of iDDT using Ohm’s law. A 0.01 uF bypass capacitor was employed to reduce power supply noise. The value of this capacitance was chosen empirically in a way to properly capture the iDDT waveform. Note that the onchip capacitance was not accounted for explicitly; instead it was inherently included in the value of the bypass capacitor. The IC was mounted on a custom manufactured PCB
20
Chehab, Patel and Makki
to ensure short leads and a stable ground plane to reduce ground bounce and minimize noise.
niques that cancel the effects of process variation such as the one described in [29].
7.2.
7.3.
Test Results
Figs. 8 and 9 show a sample of the test results for the good circuit and defective circuit respectively. The figures show the voltage drop resulting from gate switching activity, resulting in iDDT currents of 392 uA for the defect-free circuit and 132 uA for the defective circuit. The horizontal axis is 40 nsec per square. The pulse width in Fig. 8 is roughly 7 nsec (this is an-off-chip measurement). Table 12 shows a summary of the test results. The results are shown for iDDT pulses resulting from both the leading edge transition of the input pulse and trailing edge transition of the input pulse. These input vectors are labeled 1 through 5 in Table 13, where the leading and trailing edges are labeled using up and down arrows respectively. The average percentage difference between good and defective iDDT levels among the defects is 35%. Note that it is possible to increase the margin of the threshold to better account for process variation; however, this will lead to an increase in the number of test escapes. It is also possible to use tech-
Chip Variances
Tables 13 and 14 show iDDT chip-to-chip variances across three different chips. Table 13 presents the results of the defect-free chips and Table 14 presents the results of the defective chips. It should be noted that the recorded deviation is the average deviation of the results obtained from the three chips. The maximum iDDT deviation among the good chips is 29.3%, and the average is 12.1%. The maximum iDDT deviation among the defective chips is 25%, and the average is 8.16%. While the number of chips is small, and is not statistically significant to cover with a high confidence level all the corners of the process, the deviation numbers are consistent with the results of the simulations that were performed on 26 different process model parameter sets that indicated a maximum deviation of 25%. Table 12.
Physical testing results summary. Good iDDT (uA)
Bad iDDT (uA)
↑ Set 1 (detects defect 2)
665
595
10.53
↓ Set 1 (detects defect 2)
620
536
13.55
↑ Set 2 (detects defect 1)
221
110
50.23
Vector set and pulse
Fig. 8.
Difference (%)
↓ Set 2 (detects defect 1)
154
80
48.05
↑ Set 3 (detects defects 3 and 4)
179
300
−67.60
↓ Set 3 (detects defects 3 and 4)
210
230
−9.52
↑ Set 4 (detects defect 5)
210
250
−19.05
↓ Set 4 (detects defect 5)
200
280
−40.00
↑ Set 5 (detects defect 6)
156
76
51.28
↓ Set 5 (detects defect 6)
160
41
74.37
Chip 3
Deviation
Good circuit response. Table 13.
Good circuit variations in iDDT (µA). Good chips (uAmps)
Vector set
Fig. 9.
Defective circuit response.
Chip 1
Chip 2
Rising edge of Set 1
665
663
663
0.20%
Falling edge of Set 1
620
628
624
0.64%
Rising edge of Set 4
221
229
167
18. 8%
Falling edge of Set 4
154
138
174
12.0%
Rising edge of Set 6
179
155
103
29.3%
Falling edge of Set 6
210
166
150
19.77%
Rising edge of Set 9
210
212
240
8.76%
Falling edge of Set 9
200
220
212
5.06%
Rising edge of Set 12
156
154
144
4.85%
Falling edge of Set 12
160
226
228
21.8%
Scaling of iDDT Test Methods for Random Logic Circuits Table 14.
Defective circuit variations in iDDT (µA). Defective chips
Vector set
CHIP 1
CHIP 2
CHIP 3
Deviation
Rising edge of Set 1
595
579
559
3.2%
Falling edge of Set 1
536
580
556
4.1%
Rising edge of Set 4
110
100
100
6.4%
Falling edge of Set 4
80
70
50
25%
Rising edge of Set 6
300
316
320
3.8%
Falling edge of Set 6
230
242
226
4.0%
Rising edge of Set 9
250
246
262
3.7%
Falling edge of Set 9
280
288
334
11.1%
Rising edge of Set 12
76
86
96
11.6%
Falling edge of Set 12
41
39
35
8.7%
Fortunately, sensors are available to remove the contribution of the leakage current from the iDDT measurement [3]. This is done through the use of filtering techniques. Fourth, an analysis of the test data reveals that the difference between good and defective iDDT levels increases as the number of switching gates decreases (as one would expect), implying that the most important criterion for cluster formation is reducing the number of switching gates, but that would increase the number of clusters and yield a larger overhead. This is an area that requires further study. Fifth, the chip variance data indicates that the good and faulty iDDT variances are about the same. Another important consideration is whether the presence of bypass capacitances would significantly affect the iDDT test method. In both simulation and physical measurements, the iDDT test worked in the presence of bypass capacitances. Finally, it is worthy to note that most of the open defects exhibited a delayed iDDT response. The delay was in the order of 6 ns.
9.
Fig. 10.
8.
Monitoring of multiple clusters.
Practical Implementation Observations
First, we make some observations on the data that was collected. The data was for the largest cluster of the C432 having the most switching activity, based on the clustering procedure described earlier. Thus, it is reasonable to assume that worst-case conclusions that are drawn from the above data should be applicable to all the other clusters. Second, all data was collected off-chip, and is thus necessarily subject to test probe parasitics and packaging noise. Ideally, iDDT is measured on-chip. Fig. 10 shows how different clusters can be monitored by an on-chip iDDT sensor. The iDDT sensor can be time-multiplexed among different clusters. There has been some work done on iDDT sensors and reference [3] includes a high speed sensor with offset voltage cancellation capability, and IDDQ filtering capability. Third, it is critical that a capability be provided to remove the effect of leakage current from the iDDT measurement. Otherwise, it is extremely difficult to isolate a relatively small iDDT pulse on top of a very large leakage current.
21
Conclusions
In this paper, we performed the following activities: (1) presented a new iDDT -based testing method, (2) Developed an ATPG for iDDT testing, (3) performed fault simulations using realistic fault models and under realistic conditions including the presence of a bypass capacitor, (4) developed a clustering algorithm to allow the proposed iDDT test methods to scale up to larger circuits, (5) studied the impact of clustering on power performance, (6) physically measured iDDT responses from fabricated chips. From the above study, one concludes that, unless DFT is performed, the iDDT test methods presented herein loose ground very quickly with circuit size, even with directed test vectors that aim to switch a minimum number of gates. Thus DFT is required for practical application to even moderate size circuits. Fortunately, the iDDT DFT is primarily concerned with forming clusters (not physical partitioning) to isolate the iDDT response to a more manageable number of switching gates. However, this clustering has implications on the supply line routing area and performance. This implication will require further study and analysis. The clustering also necessitates the test process be serialized, in that the clusters are tested one at a time. Parallel testing would be possible but at the cost of additional iDDT monitors which can get very expensive very quickly. In summary, the proposed iDDT test methods can work but not as a stand-alone test, and they should be used selectively on different, perhaps critical, portions of a chip. In this
22
Chehab, Patel and Makki
context, the proposed iDDT test methodologies may prove to be useful for random logic circuits. Acknowledgment This paper was supported in part by the National Science Foundation through CCR-9912412 and OISE 0242808. References 1. J. Abraham and R. Tupuri, “A Comprehensive Fault Model for Deep Submicron Digital Circuits,” International Workshop on Electronic Design, Test, and Applications, 2002, pp. 360–364. 2. Bapiraju Vinnakota, Wanli Jiang, and D. Sun, “Process-Tolerant Test with Energy Consumption Ratio,” International Test Conference, 1998,Vol. pp. 1027–1036. 3. D. Binkley, R. Makki, T. Weldon, and A. Chehab, “Method and Apparatus for Testing Electronic Circuits,” US Utility Patent Application, serial number 10/237, 670. 4. A. Chehab, R. Makki, M. Spica, and D. Wu, “Analysis of iDDT for Defect Detection and Classification in Very Deep Sub-micron CMOS Circuits,” Sixth World Multi-conference on Systemics, Cybernetics, and Informatics, 2002. 5. K.T. Cheng, “Transition Fault Testing for Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993. 6. A. Germida, Z. Yan, J. Plusquellic, and F. Muradali, “Defect Detection using Power Supply Transient Signal Analysis,” International Test Conference, 1999,Vol. pp. 67–76. 7. W. Jiang and B. Vinnakota, “Statistical Threshold Formulation for Dynamic Test,” International Test Conference, 1999,Vol. pp. 57– 66. 8. B. Kruseman, P. Janssen, and V. Zieren, “Transient Current Testing of 0.25 µm CMOS Devices,” International Test Conference, 1999,Vol. pp. 47–56. 9. Y. Levendel and P.R. Menon, “Transition Faults in Combinational Circuits: Input Transition test Generation and Fault Simulation,” International Fault Tolerant Computing Symposium, 1986,Vol. pp. 278–283. 10. W.N. Li, S.M. Reddy, and S.K. Sahni, “On Path Selection in Combinational Logic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989. 11. J. Liu, R. Makki, A. Kayssi, and S. Su, “An Economical Method for Detecting Disturb Faults in CMOS SRAMs,” IEEE Proceedings of the Economics of Design, Test and Manufacture, 1996. 12. A.K. Majhi, J. Jacob, L.M. Patnaik, and V.D. Agrawal, “On Test Coverage of Path Delay Faults,” 9th International Conference on VLSI Design, 1996,Vol. pp. 418–421. 13. R. Makki, S. Su, and T. Nagle, “Transient Power Supply Current Testing of Digital CMOS Circuits,” International Test Conference, 1995,Vol. pp. 892–901. 14. Y.K. Malaiya and R. Narayanaswamy, “Modeling and Testing for Timing Defects in Synchronous Sequential Circuits,” Design and Test of Computers, 1984. 15. Y. Min and Z. Li, “IDDT Testing versus IDDQ Testing,” Journal of Electronic Testing, Theory and Applications, Vol. 13,Vol. pp. 51–55, 1998.
16. A. Mukherjee, K. Wang, L.-H. Chen, and M. Marek-Sadowska, “Sizing Power/Ground Meshes for Clocking and Computing Circuit Components,” Design Automation and Test in Europe, 2002,Vol. pp.176– 183. 17. W. Needham, C. Prunty, and E. Yeoh, “High Volume Test Escapes, An Analysis of Defects our Tests are Missing,” International Test Conference, 1998,Vol. pp. 25–34. 18. J.F. Plusquellic, D.M. Chiarulli, and S.P. Levitan, “Digital Integrated Circuit Testing using Transient Signal Analysis,” International Test Conference, 1996,Vol. pp. 481–490. 19. J. Plusquellic, D. Chiarulli, and S. Levitan, “Characterization of CMOS Defects using Transient Signal Analysis,” DFT, 1998,Vol. pp. 93–101. 20. J.F. Plusquellic, D.M. Chiarulli, and S.P. Levitan, “Identification of Defective CMOS Devices using Correlation and Regression Analysis of Frequency Domain Transient Signal Data,” International Test Conference, 1997,Vol. pp. 40–49. 21. M. Sachdev, P. Janssen, and V. Zieren, “Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS ICs,” International Test Conference, 1998,Vol. pp.204–213. 22. M.H. Schulz and F. Brglez, “Accelerated Transition Fault Simulation”, 26th Design Automation Conference, 1987,Vol. pp. 237–243. 23. J. Seguera, I. de Paul, M. Roca, E. Isern, and C. Hawkins, “Experimental Analysis of Transient Current Testing Based on Charge Observation”, Electronic Letters, Vol. 35, No. 6, 1999,Vol. pp. 441–443. 24. S. Su, R. Makki, and T. Nagle, “Transient Power Supply Current Monitoring—A New Test Method for CMOS VLSI Circuits,” Journal of Electronic Testing: Theory and Applications,Vol. pp. 23–43, 1995. 25. B. Vinnakota, “Monitoring Power Dissipation for Fault Detection,” 14th VLSI Test Symposium, 1996,Vol. pp. 483–488. 26. J.A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, “Transition Fault Simulation,” IEEE Design and Test of Computers, 1987. 27. Wanli Jiang, and Bapiraju Vinnakota, “IC Test Using the Energy Consumption Ratio,” IEEE Design Automation Conference, 1999,Vol. pp. 976–981. 28. Masahiro Ishida, Dong Sam Ha, Takahiro Yamaguchi, Yoshihiro Hashimoto, and Tadahiro Ohmi, “IDDT Testing: An Efficient Method for Detecting Delay Faults and Open Defects,” IEEE International Workshop on Defect Based Testing, Los Angeles, 2001. 29. A. Chehab, A. Kayssi, A. Nazer, and R. Makki, “An Improved Method for iDDT Testing in the Presence of Leakage and Process Variation,” in Proc. IEEE International Workshop on Defect Based Testing, Napa, California, 2004,Vol. pp. 11–16. Ali Chehab received his Bachelor degree in EE from the American University of Beirut (AUB) in 1987, the Master’s degree in EE from Syracuse University, and the PhD degree in ECE from the University of North Carolina at Charlotte, in 2002. From 1989 to 1998, he was a lecturer in the ECE Department at AUB. He rejoined the ECE Department at AUB as an assistant professor in 2002. His research interests are VLSI design and test, mobile agents, and wireless security. Rafic Makki is currently serving as Dean of the College of Information Technology at UAE University. Rafic began his career with the University of North Carolina at Charlotte in 1984, serving the university for a period of 19 years. Rafic is the recipient of several awards including the 2005 IBM Faculty Research Award (first in the Middle-East), the 2002 First Citizen Research Scholar Medal, and the ALCOA Outstanding Graduate Faculty Award. Rafic received a PhD in Electrical Engineering in 1983 from Tennessee Tech University. His research interests include design for testability and defect-based testing.
