Simulation and FPGA Modeling of a Virtual BLDC Motor

International Review on Modelling and Simulations (I.RE.MO.S.), Vol. 5, N. 3 ISSN 1974-9821 June 2012

Simulation and FPGA Modeling of a Virtual BLDC Motor K. Giridharan1, A. Chitra2, J. Vanishree3, W. Razia Sultana3

Abstract – The Brushless Direct Current (BLDC) motors are widely used in consumer electronics, electric vehicles and medical applications. BLDC motors have many advantages over brushed DC motors and induction motors, such as better speed versus torque characteristics, good dynamic response, higher efficiency and large speed ranges. These applications have made it important to develop BLDC motor controllers. This paper presents the development of a virtual motor, a set of programs that represent the BLDC motor, which is modeled and simulated in LabVIEW. The BLDC motor characteristics are implemented on the Field Programmable Gate Array (FPGA). This is used as a virtual motor for the testing and validation of digital controllers; in addition, this can also be used for educational purposes. Such a virtual motor will allow for realizing motors of various ratings by changing the parameters. This will allow the testing and validation of different controllers, without the risk of damage in extreme conditions of operations. Copyright © 2012 Praise Worthy Prize S.r.l. - All rights reserved.

Keywords: BLDC Simulation, LabVIEW Model, Virtual Motor, FPGA

Nomenclature Va ,Vb ,Vc ia ,ib ,ic

Three phase terminal voltages, V Three phase currents, A

ea ,eb ,ec R L1 Ep

Trapezoidal back emf voltages, V Per phase winding resistance, Per phase leakage inductance, H Peak of back emf voltage, V

B l

Magnetic flux density, Tesla Length of the conductor, m The angular velocity, rad/s Back emf constant, V/rad/s

m p

N f Te TL J F r

P

r

Number of conductors in series per phase Trapezoidal shape back emf function Electromagnetic torque, Nm Load torque, Nm Inertia, kg/m2 Friction coefficient, Nm/rad/s Rotor position, radians Number of magnetic poles

I.

Introduction

Electric drives are preferred in various applications, due to their accuracy, smooth control and good dynamic response [1]-[27]. Conventional dc motors are efficient and their characteristics make them suitable for use as servomotors. However, they need commutator and brushes, which are subject to wear and require periodic maintenance. Manuscript received and revised May 2012, accepted June 2012

They cannot be employed in hazardous environments due to sparking in the brushes. Their high inertia contributes to their poor dynamic behavior. When the functions of the commutator and brushes were implemented by solid-state switches, maintenance-free motors were realized. These motors are now known Brushless Direct Current (BLDC) motors [1]. They are safe, superior to the synchronous and induction motors in many ways, specifically their speed torque characteristics and dynamic response. Squirrel cage induction motors have a poor power factor and efficiency. Synchronous motors and dc commutator motors have limitations, such as sparking, noise, wear and EMI, due to the use of the commutator and brushes. These problems have led to the development of Permanent Magnet (PM) brushless motors which have PM excitation on the rotor. The use of permanent magnets like Neodymium Iron Boron and Samarium Cobalt in the rotor of the machine, in place of electromagnetic excitation results in many advantages, such as no excitation losses, high torque or power per unit volume, fast dynamic performance and improved efficiency. The major disadvantage with PM motors is their higher cost and complexity due to the power electronic converter used to drive them. The wide deployment of these BLDC motors in many industrial and home appliances evokes interest in the design and development of various digital controllers. While these controllers are to be tested and validated, motors of various ratings are required, which is not only prohibitive in cost but also carries the risk of damage. With the characteristics of the BLDC motor implemented in the Field Programmable Gate Array (FPGA) as a

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virtual motor, border-line conditions can be exercised without causing damage to the motor or controller under test. Moreover, the virtual motor allows the realization of motors of different ratings for testing with controllers, by just changing the parameters. These virtual motors could also be used for educational purposes at low cost. This paper attempts to implement the characteristics of a BLDC motor in a FPGA, which can be used as a virtual motor to test and validate the controllers.

II.

Related Work

The construction of modern brushless motors is similar to that of the ac motor, known as the Permanent Magnet Brushless DC motor (PMBLDC). The stator windings are concentrated in slots and thus differ from a poly phase ac motor, and the rotor is composed of permanent magnets. A brushless dc motor is different from ac synchronous motor in that, the former has a rotor as a permanent magnet and incorporates some means to detect the rotor position, to produce signals to control the electronic switches. The most common position sensor is the Hall element, but some motors use optical sensors. In a conventional dc motor, commutation is undertaken by the brushes and commutator; in contrast, in a brushless dc motor it is done by using semiconductor devices, such as transistors [2]. Modeling and simulation of BLDC motors are reported in literature which will help the designer to choose the appropriate control strategy [3], [4], [5]. The PMBLDC motor requires a knowledge of the rotor position, based on which the commutation of the phase currents on the stator windings occur. This requires a controller which generates the gate pulses, based on the rotor position signal like the Hall Effect or optical sensors. The gate pulses are pulse width modulated for varying the inverter output average voltage, depending on the speed of the motor with reference to a desired speed. The proportional and integral control algorithm is rendered by the controller for speed control and current control. Some implementations use fuzzy, neuro and neuro-fuzzy logic in these controllers. Different varieties of controllers have been used with BLDC motors including microcontrollers, digital signal processors, and dedicated motor controllers. [6], [7]. Recent advancements allow the controller to be designed using the programmable logical devices and the FPGA [8], [9], [10]. Some implementations eliminate sensors for rotor position, using alternative techniques for rotor position estimation and deriving the gate pulses from the back emf, current, flux, etc. While there are many publications in literature on the virtual modeling of controllers, very few have been reported on virtual motors. Real time simulation and hardware in the loop model are designed for the control of BLDC motor [11], [12]. An induction motor and virtual permanent magnet synchronous motor (PMSM) have been modeled in the FPGA using sophisticated software and hardware. A

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closed loop control using the PMSM drive is implemented on a FPGA card connected to an external controller. It is implemented on a separate RT-LAB system, using the Opal-RT FPGA-based I/O cards for analog input capture and PWM generation [13], [14], [15]. Jastrzebski et al designed induction motor model in the FPGA. [16]. A custom processor for the solution of ordinary differential equations on FPGAs is introduced with its accompanying compilation tools [17]. A prototype client-server system is developed for performing experiments on BLDC motors remotely [18]. The client user can operate from remote location through web based connection. A FPGA based controller for BLDC machines is discussed with digital control strategy to solve the stability issues [19]. A digital hardware realization of a complete induction machine model based ac drive system on a FPGA is implemented with realtime simulator including a direct field-oriented control system, a space-vector PWM scheme, and a measurement system [20]. These models use more complex hardware and proprietary software, which are costly. Hence, a simple solution for realizing a virtual BLDC motor using the FPGA is attempted in this paper.

III. Mathematical Model of the BLDC In order to perform the simulation and realization of a virtual BLDC motor, a mathematical model is required. A dynamic model of the BLDC motor is arrived at, from the set of equations (1) to (10): Va

Ria

L1

dia dt

ea

(1)

Vb

Rib

L1

dib dt

eb

(2)

Vc

Ric

L1

dic dt

ec

(3)

m

(4)

Ep

Te

p

Bl

N

p

ea

f as

r

p

m

(5)

eb

f bs

r

p

m

(6)

ec

f cs

r

p

m

(7)

ia f as J

m

d

ib f bs

r

m

dt

F

m

r

ic f cs

Te TL

r

(8)

(9)

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d r dt

P 2

m

(10)

The self and mutual inductances are assumed to be equal for all three phases. The phase voltage equations are given in (1) to (3). The three phase emfs are trapezoidal their peak Ep is given in (4). Since the stator phase currents are balanced, the sum of the three phase currents is zero. The instantaneous induced emfs are given in (5) to (7). They have the same shape as the emfs with the maximum magnitude of 1. The electromagnetic torque is given by (8). The dynamics of motion is described by (9). The electrical rotor speed and position are related by (10).

IV.

can be selected, and the time step can be adjusted outside the simulator loop. The Integrator and other functional blocks are available in LabVIEW, so that the phase currents, speed and the angular position of the motor can be calculated. The speed is compared with a reference speed profile, and the speed control is performed using a PI controller. The proportional controller is used for current control. The motor current is compared with a reference current and controlling is done accordingly.

Proposed Scheme of the BLDC drive

The block diagram of a BLDC motor is as shown in Fig. 1. Fig. 2. Virtual motor with inverter modules

Fig. 3. LabVIEW model of the BLDC

Fig. 1. Block diagram of a BLDC motor

The proposed scheme has a virtual motor in the place of the physical motor. The virtual motor is supposed to give the same output as would a physical motor. The hall sensor output from the virtual motor is fed back to the motor controller, which gives appropriate gating signals to the inverter switches. Since the controllers under test are digital, it is appropriate that the signals from the virtual motor are digital, avoiding the power part, which anyway is away from the scope and domain of the controller manufacturers. Hence, the whole work can further be simplified as shown in Fig. 2. The virtual motor has various modules in it, one to solve the differential equations to give the motor characteristics, another representing the inverter module, and a module to generate the three phase emfs and three hall sensor signals. Fig. 4. Inverter module

V.

LabVIEW Model of the BLDC

The BLDC motor model shown in Fig. 3 is simulated in LabVIEW, using the dynamic equations (1) to (10). In order to implement the motor, a simulator loop is used in LabVIEW. Inside the simulator loop, the differential equations that represent the motor are solved. The numerical method used to solve the differential equations Copyright © 2012 Praise Worthy Prize S.r.l. - All rights reserved

The inverter block uses a 120 degrees mode of conduction, and produces the three phase supply voltages to the motor by accepting the six gate pulses from the decoder. The block diagram of the inverter module is as shown in Fig. 4. The simulation results for the LabVIEW model of the BLDC is as shown in Figs. 5 to 7. The three

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K. Giridharan, A. Chitra, J. Vanishree, W. Razia Sultana

phase currents are as shown in Fig. 5. The three phase back-emfs are as shown in Fig. 6. The speed profile is as shown in Fig. 7, which indicates a small dip when the load torque is applied, and its recovery to reference speed by the PI controller action.

Fig. 7. Speed waveform

VI.

FPGA Based Model of the BLDC

The entire functionality of the BLDC motor is realised using Verilog HDL programming. This is done mainly by solving the differential equations that govern the working of the motor, using Euler’s numerical method. The entire code is divided into two sections: the controller module and the motor module. The controller module consists of the decoder circuit. It accepts the hall sensor signals as the input, and produces six gate pulses as the output. The motor module consists of the inverter and the motor. This module accepts the gate pulses as inputs, internally produces the phase voltages required for the motor and gives the hall sensor signals as outputs. The other variables of the motor such as current, speed, back-emf, etc. are also produced as outputs. The various parts of the motor module are as follows: 1. The load selecting logic. Here, a two-bit register is used and the load torque can be set as 1, 3, 5 or 7 Nm. 2. The inverter that produces the three phase supply voltages, using gate pulses. 3. The sub-modules that generate the back-emf and hall sensor signals based on the speed and angle. 4. The ordinary differential equation solving logic that accepts the voltages, back-emfs, updates the currents, speed and angle. 5. The angle corrector logic that converts the angle from the radians to degrees, and normalises it to the 0-360 range. For example, 400 degrees becomes 40 degrees. 6. The waveform selecting logic that selects the waveforms those are to be displayed. Here, the 11 waveforms that are to be displayed are divided into four sets of three waveforms each (the last set has two waveforms), and a two bit register is used, which selects which set is to be displayed. Set 1 includes three phase voltages, set 2 includes three phase backemfs, set 3 includes three phase currents and set 4 includes the motor torque and speed. 7. The logic that prepares the 32 bit register that is to be sent to the DAC. Three registers are prepared based on the value of the two bit waveform selecting register. This combined logic is embedded in an infinite loop using an ‘always’ statement, and is supplied with a clock so that it executes whenever the positive edge of the clock appears. The values of the currents, speed, torque,

Fig. 5. Three Phase Current Waveforms

Fig. 6. Three phase trapezoidal back emf waveform

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K. Giridharan, A. Chitra, J. Vanishree, W. Razia Sultana

back-emfs, etc. are initialised to zero, using an initial statement. The various variables, such as the currents, and motor parameters have decimal values. Since the floating point is not supported in the Xilinx FPGA, a fixed point representation is used. Here, all the variables and the parameters are represented using 24 bits, in which the 13 least significant bits are used to represent the decimal value, and the most significant bit is used to represent the sign. Variables such as currents, speed, motor torque, back-emfs, etc. that are produced from the motor module are in digital form. It is desirable that they should be converted to analog form, so that they can be viewed and analyzed. This is possible by using a Digital to Analog converter (DAC). The Spartan 3E starter kit has a built-in LTC2624 Digital to Analog converter, which can be accessed by using an SPI interface. This DAC has four channels to display a maximum of four analog outputs at a time. It accepts a 12 bit unsigned digital input. In order to perform the digital-to-analog conversion, first the DAC chip select line must be set to zero. Then, each bit of the 32 bit register, from the MSB to the LSB, must be transferred through the SDI pin at each positive edge of the system clock, SCK. Once all the 32 bits are transferred, the chip select line must be held high long enough for the conversion to take place. In this work, the motor and controller modules are designed separately, and are implemented in separate FPGAs. This is done mainly because it must be possible to use either the virtual motor or the virtual controller separately with physical counterparts. A proper interface is essential between the motor and the controller FPGAs. In this work, the parallel ports available on the FPGA board are used. Two parallel ports that can transfer eight bits of data when put together are used. A six bit register is used through which the hall sensor outputs from the motor are sent to the controller. In the controller, the hall sensor signals are used to produce the gate pulses. The gate pulses are then pulse width modulated, based on the motor speed and reference speed for speed control, and the pulse width modulated gate pulses are sent to the motor module through the six bit register. One bit in the parallel port is used to transfer the motor module clock, which controls the controller module. This is done to ensure synchronization with both the modules. The motor module sends the hall sensor outputs at the negative edge of the motor clock, while the controller transfers the six gate pulses at the positive edge of the motor clock.

VII.

pulses using the hall sensor signals are shown in Fig. 8. The inverter module is designed such that the voltages are represented using only two bits. The MSB shows the sign and the LSB shows the magnitude. The output of this module is shown in Fig. 9. The entire motor module is simulated, and the results showing the back-emfs and currents of phase A, along with the motor speed and hall sensor signals are shown in Fig. 10. The variables are in 24 bit fixed point representation, where the 13 least significant bits are used to represent the decimal places. The Verilog code that imitates the functionality of the motor is downloaded into a Xilinx Spartan 3E FPGA. The Spartan3E starter kit is used. The digital variables were converted to the analog form, using the built-in Digital to Analog converter, and the waveforms were observed in an oscilloscope. The experimental setup is shown in Fig. 11. The waveform showing the back-emf of phase A is shown in Fig. 12. It can be seen that the back-emf is trapezoidal in nature. The three phase currents are shown in Fig. 13.

Fig. 8. Decoder output

Fig. 9. Inverter output

Fig. 10. Motor module output

Implementation and Results

The functionality of the various modules of the BLDC motor is implemented using Verilog HDL programming. These programs were simulated before the FPGA implementation to verify the performance of the program. The results of the program modules simulated in Verilog HDL software are shown in Figs. 8 to 10. The results of the decoder module that generates the gate

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Fig. 11. Experimental setup

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K. Giridharan, A. Chitra, J. Vanishree, W. Razia Sultana

[2] [3]

[4]

[5]

[6]

[7] Fig. 12. Back-emf waveform [8]

[9]

[10]

[11]

[12]

[13]

Fig. 13. Phase current waveform

VIII. Conclusion Many motor controllers using the microcontroller, digital signal processor and dedicated motor controller chips need motors to test and validate their products. The virtual motor model of PMBLDC implemented in a FPGA is presented. In this work the FPGA has been programmed using Verilog HDL coding to perform the functions of the BLDC motor as a virtual motor. Xilinx simulation tool and Spartan 3E FPGA board have been used for realizing the virtual motor which is used for testing the various controllers in the digital domain. The simple Euler method for solving the differential equations of the BLDC motor is used in Verilog HDL coding. The performance metrics like back emf, phase current and speed measured in the virtual PMBLDC motor are compared with those obtained by using LabVIEW simulation software. The results of wave forms agree thus validating the concept of virtual motor model. This virtual motor can be used to test the controller under extreme conditions with different motor parameters. This virtual motor is a good choice as a tool for education purpose.

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T J E Miller, Brushless Permanent Magnet and Reluctance Motor Drives (Clarendon Press, Oxford, 1989).

Copyright © 2012 Praise Worthy Prize S.r.l. - All rights reserved

B. K Bose, Power Electronics and Variable Frequency Drives, Technology and Applications (IEEE Press, 1997). P. Pillay and R. Krishnan, Modeling, simulation and analysis of permanent-magnet motor drives. II. The brushless DC motor drive, IEEE Trans. Ind. Appl., vol. 25, no. 2, pp. 274–279, Mar. /Apr. 1989. Gencer and M. Gedikpinar, Modelling and Simulation of BLDCM using MATLAB / SIMULINK, Journal of Applied Sciences, Vol 6. No. 3, pp. 688 -699, 2006. Kumar P and Bauer P, Improved Analytical Model of a Permanent-Magnet Brushless DC Motor, IEEE Transactions on Magnetics, Volume 44, Issue 10, pp. 2299 – 2309, Oct. 2008. Bhim Singh, B P Singh and K Jain, Implementation of DSP Based Digital Speed Controller for Permanent Magnet Brushless dc Motor, IE(I) Journal-EL, Vol 84, pp. 16-21, June 2003. Bhim Singh and S S Murthy, A H N Reddy, A Microcontroller Based Speed Controller for Permanent Magnet Brushless DC Motor, IETE Technical Review, Vol. 17, No. 5, pp. 299-310, Sep.Oct., 2000. R. Dubey and P. Agarwal, Programmable logic devices for motion control—A review, IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 559–566, Feb. 2007. E. Monmasson and M. N. Cirstea, FPGA design methodology for industrial control systems—A review, IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 1824–1842, Aug. 2007. Anand Sathyan et al, An FPGA-Based Novel Digital PWM Control Scheme for BLDC Motor Drives, IEEE Transactions on Industrial Electronics, Vol. 56, No. 8, pp. 3040 – 3049, Aug 2009. Ch. Dufour, J. Belanger and S. Abourida, Using Real-Time Simulation in Hybrid Electric Drive and Power Electronics Development: Process, Problems and Solutions, Proc. of SAE’05, SAE , Detroit, Feb. 2006. S. Abourida et al., Hardware-In-the-Loop Simulation of FiniteElement Based Motor Drives with RT-LAB and JMAG, EVS-22 Symposium, Yokohama, Japan, October 23-28, 2006. Christian Dufour, Vincent Lapointe, Jean Bélanger and Simon Abourida, Closed-Loop Control of Virtual FPGA-Coded Permanent Magnet Synchronous Motor Drives using a Rapidly Prototyped Controller, 13th International Power Electronics and Motion Control Conference (EPE-PEMC 2008), pp. 1077-1083. M. Harakawa et al., Real-Time Simulation of a Complete PMSM Drive at 10 us Time Step, Proceedings of the 2005 International Power Electronics Conference (IPEC 2005), April 4-8, 2005, Niigata, Japan. L. Charabi, E. Monmasson, I. Slama-Belkohodja and J-P. Louis, FPGA Realization of Reconfigurable IP-Core Function th for RealTime Induction Motor Model, Proceedings of the 10 European Conference on Power Electronic and Applications, Sept. 2-4, 2003, Toulouse, France. R. Jastrzebski, O. Pyhonen and A. Napieralski, FPGA Based Platform for Real-Time Testingth of Fast Induction Motor Controllers, Proceedings of the 11 International Conference on Mixed Design (MIXDES 2004), pp. 491-496, Szczecin, Poland, June 24-26, 2004. Chen Huang, Frank Vahid, and Tony Givargis, A Custom FPGA Processor for Physical Model Ordinary Differential Equation Solving, IEEE Embedded Systems Letters, VOL. 3, NO. 4, pp. 113-116, Dec. 2011. Tatsuya Kikuchi, Takashi Kenjo, and Shuichi Fukuda, Remote Laboratory for a Brushless DC Motor, IEEE Trans. On Edu., Vol. 44, NO. 2, pp. 207-211, May 2001. Nikola Milivojevic, et al, Stability Analysis of FPGA-Based Control of Brushless DC Motors and Generators Using Digital PWM Technique, IEEE Trans. on Indl. Elec., Vol. 59, No. 1, pp. 343-351, Jan 2012. Gustavo G. Parma, Member, IEEE, and Venkata Dinavahi, “RealTime Digital Hardware Simulation of Power Electronics and Drives”, IEEE Transactions on Power Delivery, VOL. 22, NO. 2, APRIL 2007, pp. 1235-1246. Bertoluzzo, M., Bolognesi, P., Bruno, O., Buja, G., Castellan, S., Isastia, V., Menis, R., Meo, S., A distributed Driving and Steering system for Electric Vehicles using rotary-linear motors, (2010) SPEEDAM 2010 - International Symposium on Power

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J. Vanishree received B.E degree in EEE from Ranippettai Engg. College, Walaja in 2003. She received her Master of Engineering in Applied Electronics from Hindustan College of Engg., Padur, India. Her research is in the power Quality and improvement.

E-mail: [email protected] Mobile: 917708464426 W. Razia Sultana received B.E degree in EEE from Crescent Engineering College, Chennai in 2004. She received her Master of Engineering in Power Electronics from SRM University. Her research is in the area of multilevel inverters and Power Electronics and Drives.

E-mail: [email protected] Mobile: 919943295041

Authors’ information 1

Assistant Professor (Sr), School of Electrical Engineering, VIT University, Vellore, India. 2

Assistant Professor (Sr), School of Electrical Engineering, VIT University, Vellore, India. 3

Assistant Professor, School of Electrical Engineering, VIT University, Vellore, India. K. Giridharan received B.E. (Honours) degree in ECE in 1982 from University of Madras, India. He completed his Master’s degree in Power Electronics and Drives and currently doing his Ph.D from Anna University Chennai, India. His research is in the area of Brushless DC motors, Power Electronics and Drives. E-mail: [email protected] Mobile: 919445618578 A. Chitra received Bachelor of Engineering in EEE from Government College of Engineering, Tirunelveli in the year 2001. She completed her Master of Technology (Electric Drives and Control) in Pondicherry Engg. College, Puducherry, India. Her research areas include vector controlled drives and neural networks. E-mail: [email protected] Mobile: 919894760447

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