Simulation of Vedic Multiplier Using VHDL Code

Simulation of Vedic Multiplier Using VHDL Code Minor Project Report (Phase 1)

Submitted by Bhupendra Pratap Singh (2012EEC27) Avinash Pandey (2012EEC26) Saurabh Singh (2012EEC15) Saurabh Pandey (2012EEC11)

School of Electronics and Communication Engineering Shri Mata Vaishno Devi University Katra December 2014

SHRI MATA VAISHNO DEVI UNIVERSITY School of Electronics and Communication Engineering

CERTIFICATE

This to be certify that the minor project entitled “ Simulation Of Vedic Multiplier Using VHDL Code ” being submitted by Bhupendra Pratap Singh 2012eec27, Avinash Pandey 2012eec26, Saurabh Singh 2011eec15 and Saurabh Pandey 2012eec11 to the School of Electronics and Communication Engineering is completed under the supervision and guidance of the undersigned. The report has reached the standard of fulfilling of requirement of the regulation related to degree.

We wish best for his endeavor.

GUIDE Dr. Rakesh Kumar Jha Dr. Neeraj Tripathi

DIRECTOR Mr. Sumeet Gupta

Abstract -In a typical processor, Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multipliers. In computers, a typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations, particularly multiplication operations .In this project, the comparative study of different multipliers is done for low power requirement and high speed, also gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers.

Acknowledgement A mini project is a golden opportunity for learning and self-development. We consider ourselves very lucky and honoured to have our teachers to guide us. I would like to thank Dr. Rakesh Kumar Jha for his constant motivation and guidance, and for helping us to attain highest possible standard of our project on “Simulation of Vedic Multipler Using VHDL code”. I am also very grateful to Dr. Neeraj Tripathi for providing valuable information and guidance for making this project successful. We would also like to express our gratitude to Department of Electronics and Communication Engineering, SMVDU.

Bhupendra Pratap Singh (2012eec27)

Avinash Pandey (2012eec26)

Saurabh Singh (2012eec15)

Saurabh Pandey (2012eec11)

Contents

S.no.

Chapter

Page

1

INTRODUCTION

1.1

A brief General Introduction …………………………………………………..6

1.2

Vedic Mathematics …………………………………………………………….7

2

ALGORITHAMS OF VEDIC MATHMATICS

2.1

Vedic Multiplication……………………………………………………………8

2.2

Urdhva Triyakbhyam Sutra…………………………………………………….8

2.3

Multiplication of Two Decimal Numbers……………………………………...8

2.4

Algorithm for 4×4 bit multiplication Using Urdhva Triyakbhyam…………….9

3

ARCHITECTURE

3.1

Logic implementation………………………………………………………….10

3.2

RTL Schematic………………………………………………………………....11

4

SIMULATION RESULT

4.1

I/O Vedic multiplication Algorithm……………………………………………12

4.2

Speed…………………………………………………………………………....12

4.3

Result…………………………………………………………………………....13

5

CONCLUSION……………………………………………………..14

6

REFERENCES …………………………………………...............................15

CHAPTER 1 INTRODUCTION 1.1 A Brief General Introduction Multiplication is an important fundamental function in Arithmetic Operations. Multiplication based operations such as multiply and Accumulate (MAC) and Inner Product are among some of the frequently used Computations Intensive Arithmetic functions (CIAF) currently implemented in many digital signal processing (DSP) Applications such as Convolution,. Fast Fourier Transform (FFT), Filtering and in Microprocessors in its Arithmetic and logic Unit (ALU). Since Multiplication dominates the execution time of most DSP algorithms. So there is a need of high speed Multiplier. Currently multiplication time is still the dominant factor in determining the instruction cycle Time of a DSP chip. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications. This work presents different multiplier architectures. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Minimizing power consumption for digital systems involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. Digital multipliers are the most commonly used components in any digital circuit design. They are fast, reliable and efficient components that are utilized to implement any operation. Depending upon the arrangement of the components, there are different types of multipliers available. Particular multiplier architecture is chosen based on the application. In many DSP algorithms, the multiplier lies in the critical delay path and ultimately determines the performance of algorithm. The speed of multiplication operation is of great importance in DSP as well as in general processor. In the past multiplication was implemented generally with a sequence of addition, subtraction and shift operations. There have been many algorithms proposals in literature to perform multiplication, each offering different advantages and having trade-off in terms of speed, circuit complexity, and area and power consumption.

1.2 VEDIC MATHMETICS Vedic mathematics is part of four Vedas (books of wisdom). It is part of Sthapatya- Veda (book on civil engineering and architecture), which is an upa-veda (supplement) of Atharva Veda. It gives explanation of several mathematical terms including arithmetic, geometry (plane, coordinate), trigonometry, quadratic equations, factorization and even calculus. His Holiness Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884- 1960) comprised all this work together and gave its mathematical explanation while discussing it for various applications. Swamiji constructed 16 sutras (formulae) and 16 Upa sutras (sub formulae) after extensive research in Atharva Veda. Obviously these formulae are not to be found in present text of Atharva Veda because these formulae were constructed by Swamiji himself. Vedic mathematics is not only a mathematical wonder but also it is logical. That’s why it has such a degree of eminence which cannot be disapproved. Due these phenomenal characteristics, Vedic maths has already crossed the boundaries of India and has become an interesting topic of research abroad. Vedic maths deals with several basic as well as complex mathematical operations. Especially, methods of basic arithmetic are extremely simple and powerful. The word “Vedic” is derived from the word “Veda” which means the store-house of all knowledge. Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with various branches of mathematics like arithmetic, algebra, geometry etc. These Sutras along with their brief meanings are enlisted below alphabetically. (Anurupye) Shunyamanyat – If one is in ratio, the other is zero. 1. Chalana-Kalanabyham – Differences and Similarities. 2. Ekadhikina Purvena – By one more than the previous One. 3. Ekanyunena Purvena – By one less than the previous one. 4. Gunakasamuchyah – The factors of the sum is equal to the sum of the factors. 5. Gunitasamuchyah – The product of the sum is equal to the sum of the product. 6. Nikhilam Navatashcaramam Dashatah – All from 9 and last from 10. 7. Paraavartya Yojayet – Transpose and adjust. 8. Puranapuranabyham – By the completion or noncompletion. 9. Sankalana- vyavakalanabhyam – By addition and by subtraction. 10. Shesanyankena Charamena – The remainders by the last digit. 11. Shunyam Saamyasamuccaye – When the sum is the same that sum is zero. 12. Sopaantyadvayamantyam – The ultimate and twice the penultimate. 13. Urdhva-tiryagbhyam – Vertically and crosswise. 14. Vyashtisamanstih – Part and Whole. 15. Yaavadunam – Whatever the extent of its Deficiency.

CHAPTER 2 ALGORITHAMS OF VEDIC MATHMATICS 2.1 Vedic Multiplication The proposed Vedic multiplier is based on the Vedic multiplication formulae (Sutras). These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. In this work, the same ideas to the binary number system to make the proposed algorithm compatible with the digital hardware. Vedic multiplication based on some algorithms, some are discussed below.

2.2 Urdhva Triyakbhyam Sutra The multiplier is based on an algorithm Urdhva Tiryakbhyam (Vertical & Crosswise) of ancient Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. It literally means “Vertically and crosswise”. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products. Power dissipation which results in higher device operating temperatures. Therefore it is time, space and power efficient. It is demonstrated that this architecture is quite efficient in terms of silicon area/speed.

2.3 Multiplication of Two Decimal Numbers Multiplication of two decimal numbers (Figure1)

To illustrate this multiplication scheme, for example, the multiplication of two decimal numbers (325 * 738). Line diagram for the multiplication is shown in Fig.2. The digits on the both sides of the line are multiplied and added with the carry from the previous step. This generates one of the bits of the result and a carry. This carry is added in the next step and hence the process goes on. To make the methodology more clear, an alternate illustration is given with the help of line diagrams in figure.4 where the dots represent bit „0‟ or „1‟.

2.4 Algorithm for 4×4 bit multiplication Using Urdhva Triyakbhyam To illustrate the multiplication algorithm, let us consider the multiplication of two binary numbers A3A2A1A0 and B3B2B1B0. As the result of this multiplication would be more than 4 bits, we express it as... R3R2R1R0. Line diagram for multiplication of two 4-bit numbers is shown in Fig. 2 which is nothing but the mapping in binary system. For the simplicity, each bit is represented by a circle. Least significant bit R0 is obtained by multiplying the least significant bits of the multiplicand and the multiplier. The process is followed according to the steps shown in Figure 2.

Figure 2: Line diagram for multiplication of two 4- bit numbers

Firstly, least significant bits are multiplied which gives the least significant bit of the product (vertical). Then, the LSB of the multiplicand is multiplied with the next higher bit of the multiplier and added with the product of LSB of multiplier and next higher bit of the multiplicand (crosswise). The sum gives second bit of the product and the carry is added in the output of next stage sum obtained by the crosswise and vertical multiplication and addition of three bits of the two numbers from least significant position.

CHAPTER 3 3.1 Logic implementation

The following basic equations are being used in the construction of algorithm. R0 = A0B0 R1 = A0B1+B1A1+C0 R2 = A2B0+B2A0+A1B1+C1 R3 = B0A3+B3A0+A2B1+B2A1+C2 R4 = A3B1+A1B3+A2B2+C3 R5 = A3B2+B3A2+C4 R6 = A3B3+C5 R7 = C6

GATE LEVEL DESCRIPTION OF 4 BIT MULTIPLIER

(FIGURE 3 GATE LEVEL DESCRIPTION OF 4 BIT MULTIPLER)

3.2

RTL Schematic

(FIGURE 3 RTL SCHEMATIC BLOCK REPRESENTATION)

(FIGURE 5. RTL SCHEMATIC WITH INTERNAL ARCHITECTURE)

CHAPTER 4

4.1 I/O Vedic multiplication Algorithm

(figure 6 input/output algorithm)

4.2 SPEED The speed of the designed Vedic multiplier is 16.420ns. Which is faster than the simple multipliers. Vedic multiplier is also very fast in compare of booth multiplier and array multipliers which speed is approx. 22ns.

4.3 RESULT INPUT: A3A2A1A0=1101, B3B2B1B0=1001 OUTPUT: R7R6R5R4R3R2R1R0=01110101

(FIGURE 7 OUTPUT OF VEDIC MULTIPLER)

CHAPTER 5

CONCLUSION

It can be concluded that Vedic multiplier is superior in all aspects like Speed, Delay, and Complexity. Multipliers are also very useful for DSP applications like FFT, Convolution, filtering etc. Ancient Vedic Mathematics gives efficient algorithms or formulae for multiplication. Which increase the speed of devices. Urdhva Triyakbhyam is general mathematical formulae and equally works the best. Applicable to all cases of multiplication.

CHAPTER 6 REFERENCES [1]. Implementation of Vedic Multiplier for Digital Signal Processing, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Journal of Computer Applications® (IJCA). [2].Gianluca Corne a and Jordi Cortadella ―Asynchronous Multipliers with Variable-Delay Counters, IEEE Conference, 2001, pp. 701-705. [3]. Kiwon Choi and Minkyu Song, ―Design of a High Performance 32x32-Bit Multiplier With a Novel Sign Select Booth Encoder, IEEE Conference, 2001, pp. 701-704. [4]. Wen-Chang Yeh and Chein-Wei Jen, ―High-Speed Booth Encoded Parallel Multiplier Design, IEEE Transactions on Computers, Vol. 49, No. 7, JULY 2000, pp. 692-701. [5]. Jung-Yup Kang, Member, IEEE, and Jean-Luc Gaudiot, ―A Simple High-Speed Multiplier Design, IEEE Transactions on Computers, Vol. 55, No. 10, October 2006, pp.1253-1258. [7]. Shiann-Rong Kuang, Jiun-Ping Wang, and Cang- Yuan Guo, ―Modified Booth Multipliers With a Regular Partial Product Array,‖ IEEE Transactions On Circuits And Systems—II: Express Briefs, Vol. 56, No. 5, May 2009, pp.404-408 [8] www.xilinx.com