Small-Signal Modeling of Gate-All-Around - CiteSeerX

http://dx.doi.org/10.5573/JSTS.2012.12.2.230

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.12, NO.2, JUNE, 2012

Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications Jae Sung Lee*, Seongjae Cho**, Byung-Gook Park***, James S. Harris, Jr**, and In Man Kang****

Abstract—In this paper, we present the radiofrequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-nm channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 THz. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of Y22-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%. Index Terms—Gate-all-around, junctionless, MOSFET, small-signal model, Y-parameter

I. INTRODUCTION Junctionless (JL) MOSFET was recently introduced to address the problem for source and drain (S/D) formation

Manuscript received Aug. 21, 2011; revised Nov. 21, 2011. * School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Republic of Korea ** Department of Electrical Engineering, Stanford University, CA 94305, USA *** Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea **** School of Electronics Engineering, Kyungpook National University, Daegu 702-701, Republic of Korea E-mail : [email protected]

in highly scaled devices and thermal budget [1-2]. JL MOSFET is getting more attention for its advantages of small drain-induced barrier lowering (DIBL), small subthreshold swing (SS), and low standby power (LSTP) [3-4]. Also it was proven that it has a merit of outstanding maximum oscillation frequency (fmax) [5]. In this work, we characterized GAA JL MOSFETs by 3dimensional (3D) device simulator. We carried out small-signal modeling applicable to sub-millimeter range equivalent to an operation frequency of 1 THz. JL MOSFETs are comprised of source, drain, and channel regions with the same doping type and concentration. The lightly-doped drain (LDD) regions are absent, unlike the usual MOSFETs. However, the channel depletion region and the gradient of electron concentration between source/drain (S/D) regions and body region are changeable by the gate bias (VGS), which results in VGSdependent S/D resistance. Therefore, the on-state resistance (Ron) of a JL MOSFET is affected by VGSdependent S/D resistances and it can alter the output characteristics at the high-frequency range (in terms of Y22-parameter). In this work, we have confirmed the change of the electron concentration in S/D regions at different VGS values and reflected the effect in the smallsignal models of devices. Accuracy of modeling was verified by comparing results from our approach and an existing study. As a result, we confirmed that the proposed radio-frequency (RF) model exactly predicted high frequency characteristics up to 1 THz regardless of operation mode of the device. Moreover, the verification of the modeling for various devices with different doping concentrations and channel radius has been performed

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for Y-parameters. For securing higher validity of 3D device simulation, multiple models were simultaneously adopted: nonlocal band-to-band tunneling, Auger recombination model combined with Shockley-ReadHall model to consider the recombination and generation in the high-doped channel, field-dependent and concentration-dependent mobility models. Although the parameters were extracted from a circuit simulation (HSPICE) instead of actual devices, the results from device simulation using various models cooperatively provide more credible sources. By this approach, efforts were made for the highest degree of validation that one can expect from a simulation-based research.

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Fig. 2. fT of GAA JL MOSFET at linear and saturation regions (Lg = 30 nm, Rch = 5 nm, and Dn = 2×1019 cm-3).

II. SIMULATION AND SMALL-SIGNAL MODELING Fig. 1 shows a schematic view of the cross-section of GAA JL MOSFET in this work. While source, channel, and drain of a conventional MOSFET form back-to-back pn junctions, all of these regions of JL MOSFET are doped with same type of dopants and concentration. In the simulation, the doping concentration (Dn) of n-type GAA JL MOSFETs was varied from 1×1019 to 1×1020 cm-3 and the channel radius (Rch) was changed from 5 to 20 nm. The channel length (Lg) and oxide thickness were fixed to 30 nm and 2 nm, respectively. Fig. 2 the current gain as a function of frequency and cut-off frequencies (fT’s) of a GAA JL MOSFET with Lg = 30 nm, Rch = 5 nm, and Dn = 2×1019 cm-3 at different operation modes, linear and saturation regions. The values of fT were 390 GHz and 420 GHz for each region, respectively. Fig. 3 shows a non-quasi-static (NQS) small-signal circuit model of GAA JL MOSFETs operating with strong inversion. Unlike a model in a previous research for the JL silicon nanowire (SNW) MOSFETs [5], the proposed NQS model has been comprised in the components of the gate-bias-dependent Gate Source

N+

Oxide Drain

Gate

Fig. 1. Schematic view of cross-section of GAA Junctionless MOSFETs.

Fig. 3. Non-quasi-static (NQS) small-signal circuit model of GAA JL MOSFETs operating in strong inversion mode. Rsi and Rdi are the VGS-dependent source/drain resistances.

S/D resistances (Rsi/Rdi) and independent S/D resistances (Rse/Rde) that are extracted from a known method [6]. Relect can be extracted by a separate extraction method for gate resistance components [7]. However, since we have assumed a metal as the gate material in this simulation, the effect of Relect is negligibly small. To exactly extract parameters for the components of equivalent circuit model, S/D resistances and gate-source capacitance and gate-drain capacitance (Cgse/Cgde) should be extracted and de-embedded. Fig. 4 shows S/D resistances of the device with Dn = 2×1019 cm-3 and Rch = 5 nm as a function of gate voltage (VGS). Rse and Rde of 1.44 kΩ were extracted from the linear fitting. Rsi and Rdi were 1.48 kΩ, which were obtained at VGS = 1 V applied as the driving bias in modeling in this work. Cgse and Cgde of 0.551 aF are provided by a previous research [5]. In order to investigate the VGS-dependence of S/D resistances, we checked the change of electron concentration of the devices. In case of conventional MOSFETs, VGS-

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JAE SUNG LEE et al : SMALL-SIGNAL MODELING OF GATE-ALL-AROUND (GAA) JUNCTIONLESS (JL) MOSFETS FOR ~

(a)

(b)

Fig. 4. Extraction of resistances (a) Rse and Rde, (b) Rsi and Rdi as a function of VGS.

dependent S/D resistances mainly result from the LDD regions. However, Rsi and Rdi of JL MOSFETs are generated by the change of electron concentration at the interface between the channel body and S/D regions. As shown in Fig. 5, the electron concentration between those regions has a gradient by the expansion of the depletion layer according to the gate bias. At a low VGS, the

depletion region of a body expands toward S/D regions. As VGS increases, the electron concentration in the S/D regions near the body also increases and VGS-dependent S/D resistances decrease. In order to validate the accuracy of total S/D resistances (Rs/Rd) of GAA JL MOSFETs with given device geometry, we extracted those parameters at

(a)

(b)

(c)

(d)

Fig. 5. Electron concentration of GAA JL MOSFET (a) VGS = 0 V, (b) VGS = 0.3 V, (c) VGS = 0.6 V, (d) VGS = 0.9 V.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.12, NO.2, JUNE, 2012

different Dn and Rch values. As shown in Fig. 6(a) and (b), the extracted resistances were linearly proportional to 1/Dn and 1/Rch2, respectively. Since the resistivity is inversely proportional to the carrier concentration, resistance is also in the same relation with the concentration which is mainly determined by Dn in semiconductor devices. Also, resistance is inversely proportional to the conduction area so that it appears as a linear function of Rch2 (∝Area). The extracted S/D resistances and Cgse/Cgde were deembedded from Y-parameters, which were obtained by 3D simulation results and then the Y-parameters consisted of only the intrinsic parameters were given. After de-embedding S/D resistances and extrinsic capacitances, the Y-parameters by the intrinsic parameters were as follows:

Y11   2 Rgs C gs2  j (C gs  C gd ) Y12   jC gd

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Y21  g mi  j (C gd  g mi )

(3)

Y22  g dsi  j (C gd  C sd )

(4)

The equations to extract intrinsic parameters are given by the real and imaginary parts of Eqs. (1-4). The Cgs, Cgd, Rgs, gmi, gdsi, τ, and Csd can be expressed as follows:

C gs  ImY11   ImY12  

(5)

C gd   ImY12  

(6)

Rgs  ReY11   2 C gs

2

(7)

(1)

g mis  ReY21   2 0

(8)

(2)

g dsi  ReY22   2 0

(9)

   ImY21    C gd  g mi

(10)

C sd  ImY22    C gd

(11)

Fig. 7(a) and (b) show the parameters extracted by simulation for GAA JL MOSFET with Dn = 2×1019 cm-3 and Rch = 5 nm at linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). All the extracted values are summarized in Table 1. (a) Table 1. Summary of the extracted parameters Linear region (VGS = 1 V, VDS = 0.5 V) Cgs

7.59 aF

8.12 aF

Cgd

0.919 aF

0.147 aF

Rgs

(b) Fig. 6. Total S/D resistance change by (a) Dn and (b) Rch.

Saturation region (VGS = VDS = 1 V)



8.41 kΩ

8.84 kΩ

0.122 ps

0.158 ps

gmi

24.25 uS

25.6 uS

gdsi

16.91 uS

9.34 uS

Rse/Rde

1.44 kΩ

1.44 kΩ

Rsi/Rdi

1.48 kΩ

1.48 kΩ

Csdx

0.204 aF

0.156 aF

Cgse/Cgde

0.551 aF

0.551 aF

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JAE SUNG LEE et al : SMALL-SIGNAL MODELING OF GATE-ALL-AROUND (GAA) JUNCTIONLESS (JL) MOSFETS FOR ~

(a)

(b)

Fig. 7. Parameter extractions (a) Intrinsic resistances and capacitances, (b) gmi/gdsi of GAA JL MOSFET from Y-parameters in the linear and saturation regions.

The model parameters were obtained by 3D device simulation up to 1 THz. The extracted parameters and proposed equivalent circuit model have been verified by HSPICE, a circuit simulator. The presented NQS-based

(a)

(c)

RF model accurately described high-frequency characteristics of the GAA JL MOSFET up to 1 THz. Model verifications were performed under conditions of both linear and saturation regions. Fig. 8 demonstrates

(b)

(d)

Fig. 8. Verification of Y-parameters at VGS = 1 V and VDS = 0.5 V (linear region) and VGS = VDS = 1 V (saturation region) (a) Y11 (b) Y12 (c) Y21 (d) Y22.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.12, NO.2, JUNE, 2012

the verification results for Y-parameters under both conditions, respectively. By introducing the VGSdependent S/D resistances into RF modeling, the accuracy of Y22-parameters has been improved considerably. The source-drain conductance (gdsi) of MOSFET is a parameter indicating the channel resistance (Rc) and the on-state resistance (Ron) of a device consisted of Rc, Rs, and Rd. Since Rs and Rd are connected to Rc in series, the values of Ron and gdsi are directly influenced by changing them. Therefore, the addition of VGS-dependent S/D resistances in this work could improve the accuracy in extracting Ron and gdsi. Y22parameter reflects the conductance of a transistor, and the accuracy improvement of the proposed model is dominantly found in Y22-parameters by consequence. The root-mean-square (RMS) modeling errors of Y22parameters under these bias conditions have been calculated to be only 2.4%, which shows a significant

(a)

(c)

235

reduction compared with the previous NQS modeling error of 10.2%. In order to investigate the model accuracy for the devices with various doping concentrations and dimensions (channel radius), the modeled Y22-parameters from the devices were compared with the parameters simulated by TCAD. Fig. 9(a) through (d) show the validation results for GAA JL MOSFETs with different Dn’s. Because the on-state current (Ion) of JL MOSFET is dominated by the body inversion rather than the current near the surface when it comes to nanowire structure, Dn is one of the most critical parameter for determining Ion of the device [1-3]. The Y22-parameters at the low frequency region indicate the source-drain conductance when the strong inversion is formed in the transistor channel. As shown in Fig. 9(a) and (c), the conductance (gdsi) of GAA JL MOSFETs increases with Dn. The Y22parameters by the proposed model show good agreement

(b)

(d)

Fig. 9. Effect of Dn on Y22-parameters (a) Real parts and (b) Imaginary parts of Y22-parameters in the linear region (VGS = 1 V, VDS = 0.5 V). (c) Real parts and (d) Imaginary parts of Y22-parameters in the saturation region (VGS = 1 V, VDS = 1 V).

236

JAE SUNG LEE et al : SMALL-SIGNAL MODELING OF GATE-ALL-AROUND (GAA) JUNCTIONLESS (JL) MOSFETS FOR ~

(a)

(c)

(b)

(d)

Fig. 10. Effect of Rch on Y22-parameters (a) Real parts and (b) Imaginary parts of Y22-parameters in the linear region (VGS = 1 V, VDS = 0.5 V). (c) Real parts and (d) Imaginary parts of Y22-parameters in the saturation region (VGS = 1 V, VDS = 1 V).

with the TCAD simulation results up to 1 THz. Fig. 10(a) through (d) compares the Y22-parameters for GAA JL MOSFETs with different Rch’s. It is observed that the proposed model matches very well to the RF output characteristics of the devices irrespective of Rch. The verifying plots reveal that the small-signal model with VGS-dependent S/D resistances is very accurate and reliable. The verification of the proposed model for the actual device [8] will definitely improve the credibility, which should be one of the future works related with researches on GAA JL MOSFETs.

the model accuracy for S/D resistances, the RMS modeling errors of Y22-parameters have been suppressed to 2.4% which is a prominent improvement compared with the previous modeling error of 10.2%.

III. CONCLUSIONS

[1] C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J.-P. Colinge, “High-temperature performance of silicon junctionless MOSFETs,” IEEE Trans. Electron Devices, Vol.57, No.3, pp. 620-625, Mar., 2010. [2] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., Vol.94,

We presented on NQS RF model considering the gatebias-dependent S/D resistances and verified its accuracy by 3D device simulation and circuit simulation mixedly up to 1 THz. A method to extract small-signal parameters that forms an equivalent circuit model has been proposed through circuit analysis for Y-parameters. By increasing

ACKNOWLEDGMENTS This Research was supported by Kyungpook National University Research Fund, 2010.

REFERENCES

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.12, NO.2, JUNE, 2012

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No.5, p. 053511, Feb., 2009. C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, R. T. Doria, and J.-P. Colinge, “Low subthreshold slope in junctionless multigate transistors,” Appl. Phys. Lett., Vol.96, No.10, pp. 102106-1-102106-3, Mar., 2010. J.-P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazalov, and R. T. Doria, “Reduced electric field in junctionless transistors,” Appl. Phys. Lett., Vol.96, No.7, pp.073510-1-073510-3, Feb., 2010. S. Cho, K. R. Kim, B.-G. Park, and I. M. Kang, “RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs,” IEEE Trans. Electron Devices, Vol.58, No.5, pp.1388-1396, May, 2011. E. Torres-Rios, R. Torres-Torres, G. ValdovinosFierro, and E. A. Gutierrez-D., “A method to determine the gate bias-dependent and gate biasindependent components of MOSFET series resistance from S-parameter,” IEEE Trans. Electron Devices, Vol.53, No.3, pp.571-573, Mar., 2006. M. Kang, I. M. Kang, Y. H. Jung, and H. Shin, “Separate extraction of gate resistance components in RF MOSFETs,” IEEE Trans. Electron Devices, Vol.54, No.6, pp.1459-1463, Jun., 2007. J.-Y. Kim, M.-K. Choi, and S. Lee, “Accuracy Analysis of Extraction Methods for Effective Channel Length in Deep-Submicron MOSFETs,” J. Semicond. Technol. Sci., Vol.11, No.2, pp.130-133, Jun., 2011.

Jae Sung Lee received the B.S. degree in electrical engineering from the Department of Electronic Engineering, Youngnam University, Daegu, Korea, in 2007. He is currently working toward the M.S. degree in electrical engineering with the School of Electrical Engineering and Computer Science (EECS), Kyungpook National University (KNU). His research interests include design, fabrication, and characterization of nanoscale CMOS, tunneling FET, and silicon nanowire devices.

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Seongjae Cho (S’07-M’10) received the B.S. and Ph.D. degrees in electrical engineering from School of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2004 and 2010, respectively. He worked as a student internship member at the Department of System IC of Hynix Semiconductor in 2003. He worked as a process engineer in 2004 and a teaching assistant for semiconductor process education from 2005 to 2007 at Inter-university Semiconductor Research Center (ISRC) in SNU. Also, he worked with the National Institute of Advanced Industrial Science and Technology (AIST) in Tsukuba, Japan, with the support by Korea Science and Engineering Foundation (KOSEF) in 2009. From Mar. 2010 to Sep. 2010, he worked as a postdoctoral researcher at EECS, SNU, and since Oct. 2010, he has been working in the same position at the Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University, CA, USA. His research interests include design, fabrication, and characterization of nanoscale CMOS, emerging nonvolatile memory, optoelectronic, and photonic devices and integrated systems. He authored and co-authored over 130 papers published in journals and presented in conferences. Dr. Cho served as the student chair of the IEEE student branch at SNU from 2007 to 2010. He is a member of IEEE EDS, a lifetime member of IEEK (The Institute of Electronics Engineers of Korea), a member of KPS (The Korean Physical Society), and a member of IEICE (The Institute of Electronics, Information and Communication Engineers). He received Distinguished Research Achievement Awards from EECS, SNU, in 2009 and 2010, respectively, and Doyeon Paper Award from ISRC, SNU in 2010.

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JAE SUNG LEE et al : SMALL-SIGNAL MODELING OF GATE-ALL-AROUND (GAA) JUNCTIONLESS (JL) MOSFETS FOR ~

Byung-Gook Park (M’90) received his B.S. and M.S. degrees in electronic engineering from Seoul National University (SNU) in 1982 and 1984, respectively, and his Ph.D. degree in electrical engineering from Stanford University in 1990. From 1990 to 1993, he worked at the AT&T Bell Laboratories, where he contributed to the development of 0.1 micron CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25 micron CMOS. In 1994, he joined SNU as an assistant professor in the School of Electrical Engineering (SoEE), where he is currently a professor. In 2002, he worked at Stanford University as a visiting professor, on his sabbatical leave from SNU. He was leading the Inter-university Semiconductor Research Center (ISRC) at SNU as the director from June 2008 to June 2010. Currently, he is researching at Stanford University as a visiting professor. His current research interests include the design and fabrication of nanoscale CMOS, flash memories, silicon quantum devices, and organic thin film transistors. He has authored and co-authored over 580 research papers in journals and conferences, and currently holds 34 Korean and 7 U.S. patents. He has served as a committee member on several international conferences, including Microprocesses and Nanotechnology, IEEE International Electron Devices Meeting (IEDM), International Conference on Solid State Devices and Materials (SSDM), and technical program and general chairs for IEEE Silicon Nanoelectronics Workshop (SNW). Also, he has been serving as an editor of IEEE Electron Device Letters. He is currently serving as an executive director of the Institute of Electronics Engineers of Korea (IEEK) and the board member of IEEE Seoul Section, Region 10. He received “Best Teacher” Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in 2003, Haedong Paper Award from IEEK in 2005, and Educational Award from College of Engineering, SNU, in 2006. Also, he received Haedong Academic Research Award from IEEK in 2008.

James S. Harris, Jr. received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1964, 1965, and 1969, respectively. In 1969, he joined Rockwell International Science Center, Thousand Oaks, CA, where he was one of the key contributors to ion implantation, molecular beam epitaxy, and heterojunction devices, leading to their preeminent position in GaAs technology. In 1980, he became the Director of the Optoelectronics Research Department. In 1982, he joined the Solid State Electronics Laboratory, Stanford University, as a Professor of Electrical Engineering, where he was the Director of the Solid State Electronics Laboratory (1984-98), the Director of the Joint Services Electronics Program (1985-99), and is currently the James and Ellenor Chasebrough Professor of Electrical Engineering, Applied Physics, and Materials Science in the Center for Integrated Systems. His research interests include physics and application of ultra-small structures and novel materials to new high-speed and spin-based electronic, and optoelectronic devices and systems. He is the author or coauthor of more than 650 publications. He holds 14 issued U.S. patents. Dr. Harris is a Fellow of the American Physical Society. He was the recipient of the 2000 IEEE Morris N. Liebmann Memorial Award, the 2000 International Compound Semiconductor Conference Walker Medal, the IEEE Third Millennium Medal, and the Alexander von Humboldt Senior Research Prize in 1998 for his contributions to GaAs devices and technology. He has been a Member of the National Academy of Engineering of the U.S. since 2011.

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In Man Kang (M’11) received the B.S. degree in electronic and electrical engineering from School of Electronics and Electrical Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2001, and the Ph.D. degree in electrical engineering from School of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2007. He worked as a teaching assistant for semiconductor process education from 2001 to 2006 at Inter-university Semiconductor Research Center (ISRC) in SNU. From 2007 to 2010, he worked as a senior engineer at Design Technology Team of Samsung Electronics Company. In 2010, he joined KNU as a full-time lecturer of the School of Electronics Engineering. His current research interests include CMOS RF modeling, silicon nanowire devices, tunneling transistor, low-power nano CMOS, and light emitting diodes. He is a member of IEEE EDS and a member of IEEK (The Institute of Electronics Engineers of Korea).

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