Soil Moisture Monitoring Using Field Programmable Gate Arraywww.researchgate.net › publication › fulltext › Soil-Moist

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Soil Moisture Monitoring Using Field Programmable Gate Array Muhammed Ihsan Husni, Mohammed Kareem Hussein, Mohd Shamian Bin Zainal, Shipun Anuar Bin Hamzah, Danial Bin Md Nor, Hazwaj Bin Mhd Poad Faculty of Electrical and Electronic Engineering Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat, Malaysia

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This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity. Hardware descriptive language has been used for the implementation of proposed topology on Field Programmable Gate Arrays. The hardware used for this purpose is an Altera board. The simulated results take into consideration the environmental factors such as the humidity, soil moisture content and the temperature. The proposed system continuously monitors the environmental changes for any updates. The system also controls a water motor that is turned on as the system senses the reduction in moisture content. The system implementation on hard wave level show promising results and have been discussed in detailed.

Received Jan 12, 2018 Revised Mar 29, 2018 Accepted Apr 12, 2018 Keywords: Altera FPGA Remote Monitoring Soil

Copyright © 2018Institute of Advanced Engineering and Science. All rights reserved.

Corresponding Author: Muhammed Ihsan Husni, Faculty of Electrical and Electronic Engineering Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat, Malaysia. Email: [email protected]

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INTRODUCTION Soil moisture is a key variable in controlling the exchange of water and heat energy between the land surface and the atmosphere through evaporation and plant transpiration. As a result, soil moisture plays an important role in the development of weather patterns and the production of precipitation. Therefore, used a particular Soil Sensor and integrated it with FPGA & Verilog code will help to control the benefit quantity of water for the soil. The first integrated circuits that were developed in the early 1960s contained less than 100 transistors on a chip and are called small-scale integrated (SSI) circuits. The number of transistors continued to increase over the time, this trend has continued to the present day with 1,000,000 transistors on a chip by the late 1980s, 10,000,000 transistors on a chip by the mid-1990s, over 100,000,000 transistors by 2004, and up to1, 000,000,000 transistors on a chip today. This exponential growth in the amount of digital logic that can be packed into a single chip has produced serious problems for the digital designer. How can an engineer, or even a team of engineers, design a digital logic circuit that will end up containing millions of transistors? A completely different architecture was introduced in the mid-1980‟s that uses RAM-based lookup tables instead of AND-OR gates to implement combinational logic. These devices are called field programmable gate arrays (FPGAs). The device consists of an array of configurable logic blocks (CLBs) surrounded by an array of I/O blocks. The traditional way of designing digital circuits is to draw logic diagrams containing SSI gates and MSI logic functions. However, by the late 1980s and early 1990s such a process was becoming problematic. How can you draw schematic diagrams containing hundreds of thousands or millions of gates? As Journal homepage: http://iaescore.com/journals/index.php/ijeecs

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ISSN: 2502-4752

programmable logic devices replaced TTL chips in new designs a new approach to digital design became necessary. Computer-aided tools are essential to designing digital circuits today. What has become clear over the last decade is that today‟s digital engineer designs digital systems by writing software! This is a major paradigm shift from the traditional method of designing digital systems. Many of the traditional design methods that were important when using TTL chips are less important when designing for programmable logic devices. HDL is one of the two most common Hardware DescriptionLanguages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. HDL‟s allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. The basic model design scheme is presented as a flow chart in Figure 1. 1. Algorithmic level (much like c code with if, case and loop statements). 2. Register transfer level (RTL uses registers connected by Boolean equations). 3. Gate level (interconnected AND, NOR etc.). 4. Switch-level (the switches are MOS transistors inside gates).

Figure 1. Basic Design Methodology The DE0-Nano board introduces a compact-sized FPGA development platform suited for to a wide range of portable design projects, such as robots and mobile projects [1]. The DE0-Nano is ideal for use with embedded soft processors—it features a powerful Altera Cyclone IV FPGA (with 22,320 logic elements), 3