This paper presents an overview of substrate coupling noise (SCN) phenomenon
in high-speed SOC and digital integrated circuits (ICs). Various design ...
ECE465: PERFORMANCE ISSUES IN VLSI IC DESIGN, UNIVERSITY OF ROCHESTER, DECEMBER 2009
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Substrate Coupling Noise: Modeling and Mitigation Techniques Raj S. Parihar, Student Member, IEEE
Abstract—Thirst for high performance and increased functionality has forced designers to integrate large number of transistors on same die and sometime on same substrate. System-on-a-chip (SOC) – a trend in which analog, digital, and RF circuits share common substrate – is becoming popular primarily due to ease of large scale heterogeneous integration. However, one of the major concerns in such systems is the noise which gets coupled from noise sources to more sensitive blocks through common substrate. In past, noise issues were investigated in analog circuits and digital circuits were less vulnerable to such problems until recently. This paper presents an overview of substrate coupling noise (SCN) phenomenon in high-speed SOC and digital integrated circuits (ICs). Various design methodologies to efficiently model the SCN are reviewed and their key aspects are discussed. Few simple yet important noise mitigation techniques and state-of-the-art solutions to deal with SCN problems are also presented. Finally, some of the avenues for future research directions are identified and summarized. Index Terms—Substrate coupling noise, substrate extraction, modeling techniques, noise mitigation techniques, isolation techniques.
I. INTRODUCTION
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HE increased demand for high performance and low power has resulted into integration of RF, digital, and analog circuits together on same substrate. While the dense integration improves the performance substantially and saves additional silicon area it does come at the cost of degraded noise margin [3], [4]. One of the key issues in modern high speed SOC design is the SCN associated problems which is due to common substrate for noise sources i.e. digital blocks and noise sensitive blocks i.e. low-swing analog blocks [1]–[3]. High frequency switching noise compounded with Manuscript received December 10, 2009. This work was done as per the course requirement of “ECE465: Performance and Issues in VLSI Design’ at University of Rochester, Rochester, NY – 14627. Raj S. Parihar is with the Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627 USA. (phone: 585-752-1706; e-mail: parihar@ ece.rochester.edu).
scaled supply voltage reduces the noise margins and exposes all kind of circuits to severe noise problems. Large scale integration has started a new trend, called SOC, where fundamentally different kind of circuits are integrated on same substrate. The main disadvantage of SOC is that common substrate provides a good medium for noise to get coupled from noise sources to more sensitive blocks [2]. Substrate coupling – only identified recently – becomes even stronger as feature size continues to scale down. Such coupling is undesired in most of the cases because it does not only cause the voltage fluctuations but sometime may result into functional failures of digital circuits as well. The paper is organized as follows. Various sources of noise and coupling mechanism are described in section II. Some of the state-of-art modeling techniques are reviewed in section III. Section IV presents few effective noise mitigation techniques and circuit solutions to deal with SCN problem. The paper is concluded in section V along- with some of the general guidelines. Finally, directions for future research in substrate coupling are presented in section VI. II. SUBSTRATE COUPLING MECHANISM Substrate coupling broadly describes the current injection into the substrate by high frequency voltage sources. Injected noise couples to nearby located devices through the substrate and appears across either the supply voltage or input/output signals. This section describes the phenomenon of substrate coupling and its adverse effects on overall performance of high speed circuits. A. What is Substrate Coupling? Substrate coupling is most commonly known as coupling of digital noise through substrate to other blocks such analog. The substrate has finite resistance and no longer can be modeled as a point or node. Typically substrate terminals of various devices are connected to common ground or supply. This helps the noise to couple from noisy (mainly high speed digital) node to sensitive (primarily analog) nodes as depicted in Fig.1.
ECE465: PERFORMANCE ISSUES IN VLSI IC DESIGN, UNIVERSITY OF ROCHESTER, DECEMBER 2009
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the node – as shown in Fig. 2 – by using the boundary conditions [8], [9].
Fig. 1. Noise coupling from digital to analog node. (a) Physical view. (b) Circuit view
Substrate noise injection at device level is dominated by substrate currents from impact ionization. At the circuit level, it is mainly due to junction capacitances and capacitive coupling between source/drain and substrate. At higher level – package level – it is mainly due to inductive coupling which results from large I/O bonding wires. B. Impact on Circuit Performance Two effects which are related to substrate noise are MOS threshold voltage modulation due to fluctuating body biasing and change in DC bias current. Threshold voltage modulation and change in biasing current may lead to degradation of gain and reduction in bandwidth [2]. Parasitic capacitances between substrate and drain/source lead to crosstalk problem. C. Substrate Coupling Methodologies There are two interdependent aspects of substrate coupling methodology – modeling of substrate noise effectively and employ the mitigation techniques to avoid it. This also means that the algorithms to model the substrate should have liner or polynomial time – as oppose to exponential time – and finite memory requirement. Brief overview of various modeling techniques which can be used to model SCN are presented in section followed. III. NOISE MODELING TECHNIQUES The solution of SCN problem commence from modeling it accurately and also efficiently. Due to finite resistivity of substrate it can no longer be modeled as a point or node but rather 3-D mesh of impedances. This section presents various modeling technique to appropriately model the substrate of small and large circuits as a mesh of finite impedances. A. Integral Methods to Model Substrate Substrate can be modeled as multiple nodes and finite resistances between any two nodes [3]. In order to find out the “exact” resistances and capacitance we need to solve the Maxwell equations for a cube region around
Fig. 2. Detailed substrate extraction using Maxwell equations
Small circuit extraction is being done using exact methods and by finding out the correct voltages and currents across the substrate [9]. Despite of being most accurate 3-D electro-magnetic equations are not trivial to solve even for medium scale circuits. To model large circuits, approximation based methods or macro-models are best suited which are explained in next sub-section. B. Efficient Modeling Techniques Due to computational inefficiency of integral based modeling techniques designers have come up with various modeling techniques which are efficient for large scale circuits. One of the challenging tasks is to model the large circuits with high accuracy and reasonable computational efficiency.
Fig. 3. Lumped impedance model suitable for large circuits
Instead of modeling substrate as a 3-D mesh of impedances we can lump the impedances among multiple substrate contacts [1]. This approximation reduces the number of impedances to one between any two substrate contacts. Another efficient way is to use macro-models to efficiently capture the behavior of circuits using few components. A simple macro-model is proposed in [7] that identifies the dominant source of noise and ignores others. Another possible solution tries to combine the substrate contacts into regions, based on the voltage drop among them. These large regions where the voltage drop is insignificant can be modeled as node and coarser grain extraction techniques can be used for such regions [6]. On the other hand, where drops are more those regions can be extracted using finer extraction
ECE465: PERFORMANCE ISSUES IN VLSI IC DESIGN, UNIVERSITY OF ROCHESTER, DECEMBER 2009
techniques. This reduces the number of nodes and impedances to be extracted. IV. NOISE MITIGATION TECHNIQUES After substrate is modeled using appropriate technique the next task is to employ economical mitigation techniques which are just sufficient to avoid the level of noise present. In this section some of the state-of-art physical design and circuit based techniques are presented which can be used either as stand alone or in hybrid fashion. A. Physical Design Techniques Simplest technique is to use of compact layout as far as possible to avoid SCN. It has been shown that compact layout avoids the non-uniform noise across the chip which is much easier to deal [11]. Strategies to place substrate contact at appropriate location – depending upon resistance and current path – are being developed in [13], [14]. The bulk type and epi-type substrate have different resistances thus require different placement. Noise source could be a digital node and SC1 is substrate contact placed between victim node (SC2) and noise source. The intention is that SC1 should be able to catch significant noise so that it does not propagate to SC2 as shown in Fig. 4.
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been shown that dynamic registers produce less tractable noise whereas static registers’ noise is more predictable. This is the reason why static registers are always preferred in applications where we need high noise immunity [11]. Differential ended signals and circuits are least susceptible to noise which makes them preferred choice over single ended signals and blocks. C. Isolation Techniques One way to deal with SCN is to physically isolate the noise source and victims by placing them furthest away from each other. This sub-section describes various isolation techniques which try to separate the noise source from noise victim on the same die. The simplest method is to distance isolation [5]. Physically separating the blocks improves the noise handling capability. A distance of 1000 um reduces the noise approximately by 30 dB as shown in Fig. 6 [4].
Fig. 6. Reduction is noise as a function of distance
Fig. 4. Efficient substrate placement depending upon the resistivity of substrate and current path
B. Circuit Design Techniques Guard rings and active guard filters are most common circuit techniques to deal with SCN. Active guard-band filtering is a circuit technique that controls the noise source using a guard-band structure [12]. Instead of using the ground connection of conventional guard bands, a noise cancellation signal is actively supplied to cancel the digital noise through the guard band as depicted in Fig. 5.
Isolation of analog and digital blocks either through guard ring or some other structure also helps in a great deal. Noise aware floorplanning is good to solve some of the noise issues. A typical floorplanning is depicted in Fig. 7. The key idea is to identify and separate the blocks which are more susceptible to noise. For example, low amplitude single ended analog circuits are most vulnerable thus they are placed furthest away from most noisy high-speed digital circuits [14].
Fig. 7. Noise-aware floorplanning that keeps noise sources furthest away from vulnerable blocks
V. CONCLUSIONS
Fig. 5. Active cancellation circuit techniques
Register positioning techniques and orientation also play an important role in mitigating the noise. It has
Switching noise of digital blocks is the dominant component of coupling noise which affects more sensitive analog and RF blocks integrated on the same substrate. The simplest way to deal with the SCN is to use separate substrate and power supply lines for analog
ECE465: PERFORMANCE ISSUES IN VLSI IC DESIGN, UNIVERSITY OF ROCHESTER, DECEMBER 2009
and digital block. However, one of the best known solutions is to use the guard rings around the digital blocks and place appropriate substrate contacts that changes the substrate resistance thus the current injection path as well. A common practice is to connect the guard rings to external “quiet” ground and not to the digital or analog grounds. Differential ended analog signals and circuits are robust for noisy ambiance and exhibit good noise rejection because they have capability to reject/cancel any noise which gets coupled with signal. Scaling of feature size and supply voltage would exacerbate the problem of the substrate coupling noise. The best way to deal with SCN is to use a holistic approach to employ mix of solutions i.e. physical techniques and circuit based techniques together. Hybrid solutions are more likely to be optimized solutions for multiple resources i.e. power, die area, speed, and design effort. VI. FUTURE DIRECTIONS Modeling of substrate coupling with high accuracy for large integrated circuit is a daunting and resource consuming task. Approximations lead to substantial errors in exact noise voltages and accurate extraction require lot of memory for computation and also high processing power. The future research in substrate coupling is likely to address the problem of efficiently modeling the substrate in large scale circuits. Researchers are likely to develop macro-models which capture the SCN in more efficient way. High performance also demands low power design and in order to achieve low power the most attractive technique is to scale down the voltage which exacerbates the noise margin. With reduced noise margin the substrate coupling would present additional degree of complications which would require completely new class of solutions – low power substrate coupling noise mitigation techniques. The substrate is still modeled as a 3-D cube of resistances and sometime cube of resistances and capacitances. However, the most likely scenario would be to model the substrate as RLC cubes in future. Integration of the substrate extraction algorithms and mitigation techniques i.e. insertion of guard rings into existing CAD flow would present another set of new challenges to EDA industry.
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Raj S. Parihar (S’09) received the B.E. degree with honors in electrical and electronics engineering from Birla Institute of Technology and Science, Pilani, India in 2006. He is currently pursuing the Ph.D. degree in electrical and computer engineering at the University of Rochester, Rochester, NY.
