Survey of C-based Application Mapping Tools for ...

Survey of C-based Application Mapping Tools for Reconfigurable Computing

Brian Holland, Mauricio Vacas, Vikas Aggarwal, Ryan DeVille, Ian Troxel, and Alan D. George High-performance Computing and Simulation (HCS) Research Lab Department of Electrical and Computer Engineering University of Florida

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#215 MAPLD 2005

Outline  

Introduction General Survey 

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CARTE CATAPULT C B E N C H M S A U R R K V E Y

Ten C-based Application Mappers

Benchmarking & Results 

Finite-Impulse Response (FIR)

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N-Queens

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Radix Sort

Lessons Learned Conclusions Acknowledgements References

DIME-C HANDEL C IMPULSE C MITRION C NAPA C SA-C STREAMS C SYSTEMC

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Motivation for Application Mappers 

Motivation for Application Mappers 

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HDL programming has shortcomings 

Limited applicability to application developers

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More involved development process (vs. software)

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Requires training beyond application level

HDL

Instead, can we find and exploit an environment that allows a measure of hardware control along with increased productivity? 

Can we bring RC performance benefits to application developers?

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Would this be practical/possible in traditional HDL? 

HDL is well below the level of traditional application programming

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Consequently, we need to move to a higher level of abstraction

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Introduction

C Code

COMPILER

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Selecting a Higher Level of Abstraction 

CAD tools: Visual appealing, but tedious for large projects

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New language: Optimal, but requires complete retraining

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Traditional or Object-Oriented languages: Which? How?

HDL

Netlist

Configuration File

Ideally, use pure ANSI-C, “The Universal Language” 

Requires no additional knowledge or special training

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Port existing C programs into hardware implementations (HDL)

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Translation can be handled by a hardware compiler

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Programmer concentrates on algorithmic functionality

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Commonalities 

General characteristics of C-based application mappers: 

Companies create proprietary ANSI C-based language

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Languages do not have all ANSI C features

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Extra pragmas are included for corresponding compilers

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Additional libraries of functions/macros for further extensions

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Must adhere to specific programming “style” for maximum optimization

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Emphasis on both hardware generation and I/O interfaces ANSI-C

VHDL

void FIR(int INPUTA, int OUTPUTB) {

/*user source*/

COMPILER

Entity FIR is Port ( rst, clock: in std_logic; INPUTA_en: in std_logic; INPUTA_data: in std_logic_vector(31 downto 0); OUTPUTB_en: in std_logic; OUTPUTB_data: out std_logic_vector(31 downto 0)); end;

} /*user source in VHDL*/

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Spectrum of C-based Application Mappers SURVEY PORTION Catapult C

Carte

Impulse C

DIME-C

SA-C

SystemC

Mitrion C

Handel C

Streams C

Napa C

Open Standard

Generic HDL Multiple Platforms

Generic HDL (Optimize for Manufacturer’s Hardware)

Targets a Specific Platform/Configuration

RISC/FPGA Hybrid Only

Cycle Accurate

BENCHMARK SECTION VHDL

Deterministic

VHDL

Not Cycle Accurate

Limited Predicitiblity

Co ntrol

Handel C

DIME-C Impulse C ANSI-C

ANSI-C

Software

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DIME-C Handel C Impulse C

Some HW Pragmas

Many HW Pragmas

Effort HDL

THE LAW OF CONSERVATION OF PAIN

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Carte

SRC Computers 

Mentor Graphics

[1]

C/Fortran FPGA environment 

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Catapult C 

Direct mapping of C/Fortran code to configuration level Software emulation and simulation of compiled code for debugging Capable of multiprocessor and multi-FPGA computational definitions Allows explicit data flow control within memory hierarchy

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Algorithmic synthesis tool for RTL generation 

RTL from “pure” untimed C++

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No extensions, pragmas, etc.

Compiler uses “wrappers” around algorithmic code  

Targets SRC’s MAP processor Produces “Unified Executables” for HW or SW processor execution Runtime libraries handle required interfacing and management

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[2-3]

External: manages I/O interface Internal: constrains synthesis to optimize for chosen interface

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Explicit architectural constraints and optimization

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Output: RTL netlists in VHDL, Verilog, and SystemC

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DIME-C Nallatech

FPGA prototyping tool

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Designs are not cycle-accurate

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Celoxica

[4]

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Handel C

Allows application synthesis for a higher clock speed

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Environment for cycle-accurate application development

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All operations occur in one deterministic clock cycle

Compilation/Optimization 

Pipeline/parallelize where possible

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Included IEEE-754 FP cores

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Dedicated (integer) multipliers

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Currently in beta, expected release: 4Q05 Output: synthesizable VHDL and DIMEtalk components

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[5]

Makes it cycle-accurate, but clock freq reduced to slowest operation Decisions/Loops are “penalty-free” but can significantly impact timing

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Language has pragmas for explicitly defined parallelism

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Compiler can analyze, optimize, and rewrite code

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Output: VHDL/Verilog, SystemC, or targeted EDIFs #215 MAPLD 2005

Impulse C

Impulse Accelerated Technologies 

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Processes - independent, potentially concurrent, computing blocks

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Streams – communicate and synchronize processes

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Each process implemented as separate state machine

Output: Generic or FPGAspecific VHDL

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“Processor” creates abstraction layer between C code and FPGA

Compilation 

However, focuses on compatibility with C development environments

[7]

“Softcore” processor tactic 

Compilation 

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Uses Streams-C methodology 

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Mitrion

[6]

Language/compiler for modeling sequential apps. 

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Mitrion C

C code is mapped to a generic “API” of possible functions Processor instantiated on FPGA, tailored to specific application Custom instruction bit-widths, specific cache and buffer sizes

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Currently in beta, expected release: 4Q05

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Output: a VHDL IP core for target architectures #215 MAPLD 2005

Napa C

National Semiconductor 

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Capitalize on single-cycle interconnect instead of I/O bus

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Hand-optimized pre-placed, prerouted module generators

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Designed to implicitly express data-parallel operations Image and signal processing

Compiler (UC-Irvine, UC-Riverside, Colorado State Univ.)

Compiler generates hardware pipelines from C loops

Targets NS NAPA1000 hybrid processor 

[9-12]

High-level, expression-oriented, machine-independent, singleassignment language

Datapath Synthesis Technique 

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Colorado State University

[8]

Language/compiler for RISC/FPGA hybrid processor 

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SA-C

Fixed-Instruction Processor (FIP), Adaptive Logic Processor (ALP)

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Loop optimizations

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Structural transforms

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Execution block placement

Target Platforms 

ALP also compiles to RTL VHDL, structural VHDL, structural Verilog 10

UC Irvine Morphosys; Annapolis WildForce, StarFire, WildFire #215 MAPLD 2005

Streams C

Los Alamos National Laboratory 

Open SystemC Initiative (OSCI)

[12-14]

Stream-oriented sequential process modeling 

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SystemC 

Essentially, data elements moving through discrete functional blocks

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Generates multi-threaded processor executables and multiple FPGA bitstreams

Includes functional-level simulation environment

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Output: synthesizable RTL

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Hierarchical decomposition of a system into modules Structural connectivity between modules using ports/exports Scheduling and synchronization of concurrent processes using events

Event-driven simulator 

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Core language, modules & ports for defining structure, and interfaces & channels

Supports functional modeling 

Allows parallel C program translation into a parallel arch.

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Open-source extension of C++ for HW/SW modeling 

Compiler

[15-16]

Events are basic dynamic/static process synchronization objects #215 MAPLD 2005

About the Benchmarks 

Three classic algorithms used for benchmarking

10 8 6

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Finite-Impulse Response (FIR)  

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Simple 51-tap FIR filter for standard DSP applications Compare compiler solutions and analyze their usage metrics

1

3

5

7

9

11

13

15

17

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Sorts using ‘binary bins’, minimizing resources Illustrates resource metrics in RAM-intensive applications

Implementation Details

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23

25

27

-6 -8 -10

0

110

100

1

111

101

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DIME-C, Handel C, Impulse C, VHDL, and ANSI-C (for baseline timing)

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Experiments performed on Nallatech BenNUEY-PCI card with VirtexII-6000 FPGA

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Resource utilization based on post place-and-route data

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Runtime represents communication time (setup and verification I/O is negated)

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Handel C and Impulse C require VHDL wrappers which can increase resource usage

Holland

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-4

Classic embarrassingly parallel HPC backtracking search problem Showcases the potential of optimized implementations

Radix Sort 

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2

-2

N-Queens 

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4

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Finite-Impulse Response 100

FIR Resource Utilization Statistics

Speedup over 2.4GHz Xeon 4

% Usage

80

60

3

40

2

20

1

0 Slices

Multipliers DIME-C

Handel C

Block RAMs Impulse C

Clock Freq

0 DIME-C

VHDL

Handel C

Impulse C

VHDL

gcc -O3

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FIR filter containing 51 taps, each 16-bits wide (based on algorithms in [4,6])

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Various application-mapper languages do not have a consistent I/O interface

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Could not create a consistent streaming channel with requisite blocking in every tool

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Instead, FIR algorithm operates on values stored in a block RAM

Obtains speedup through parallel multiplication, efficient memory accesses 

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gcc -O0

The 51 coefficients and variables are stored in local variables

Additional performance boosts are possible in multi-channel DSP processing

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N-Queens Speedup over 2.4GHz Xeon

N-Queens Resource Utilization Statistics

6

100

5

80

% Usage

4 60

3 40

2

20

1 0

0 Slices DIME-C

13

Clock Freq Handel C

Impulse C

DIME-C

VHDL

14

15

Handel C

Impulse C

16 VHDL

17 gcc -O3

gcc -O0

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Represents a purely computational algorithm; virtually no communication overhead

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Algorithm contains several parallelizable code segments, exploitable for speedup

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Implementations are based upon same baseline C code 

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N

Every available technique and compiler optimization is employed to boost performance

Notes: 

Handel C N-Queens is a benchmark from our MAPLD’04 paper with additional refinements

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VHDL N-Queens is culmination of a semester-long endeavor into algorithm’s parallelism

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DIME-C and Impulse C N-Queens are results of experimentation with beta compilers 14

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Radix Sort Radix Sort Resource Utilization Statistics

Speedup over 2.4GHz Xeon

1.0

100

% Usage

80

60 0.5

40

20

0 Slices DIME-C

Block RAMs Handel C

Impulse C

Clock Freq

0.0 DIME-C

VHDL

Handel C

Impulse C

VHDL

gcc -O3

gcc -O0

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Sorts values one bit at a time (saving significant resources vs. sorting on digit at a time)

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Represents a “worst-case” legacy algorithm, containing no functional-level parallelism

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Every element in every iteration depends on every previous element in every iteration

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Ideal for software processor with fast cache, challenging in FPGA hardware

Speedup comes through efficient RAM usage and compiler optimizations/pipelining 

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Reduce quantity and addressing complexity of RAM accesses whenever possible

Metrics are based on sorting 600 32-bit integers contained within a block RAM

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Some Optimization Techniques Keep expensive computational operations to a minimum Multiplication, division, modulo, greater/less than, and floating point are *slow*

BAD

temp = a[0]; for(i=0;i