Synchronous state machine inner FPGA controlling ...

Synchronous state machine inner FPGA controlling PFC boost converter Tiago Kommers Jappe

Samir Ahmad Mussa

Richard Henry Sutter Rosendo

Federal University of Santa Catarina INEP−Power Electronics Institute Florian´opolis, SC, Brazil Telephone: +(55)48-9721-9204 Email: [email protected]

Federal University of Santa Catarina INEP−Power Electronics Institute Florian´opolis, SC, Brazil Telephone: +(55)48-9721-9204 Email: [email protected]

Federal University of Santa Catarina INEP−Power Electronics Institute Florian´opolis, SC, Brazil Telephone: +(55)48-9721-9204 Email: [email protected]

Abstract—The FPGA device is an IC that can be programmable by software, to implement any logical function. Its inner architecture offers possibility to execute complex algorithms, even some parts running in parallel, improving law control dynamics. In consequence, the FPGA can control power electronics converters successfully. The several segments of the converter control are connected and synchronized by a state machine. Thus, this paper proposes a design of a synchronous state machine to control a PFC boost converter with FPGA. The communication between FPGA and ADC is implemented by SPI communication. The controllers and PWM modulator are build in FPGA to control the converter. Experimental results show the mains signals of state machine and also the boost converter in operation.

I. I NTRODUCTION The FPGA (Field Programmable Gate Array) is a programmable digital logic device by software. Thus, it can execute any logical function such as numeric processors, digital interface, controllers and decoders only in a single IC. The FPGA architecture contains programmable logic components called Configurable Logic Blocks (CLB), and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together. The CLB can be configured to make complex combinational functions, or only simple logic gates like AND and XOR. In most FPGA, the CLB also include memory elements, which can be simple flip-flops or more complete blocks of memory. FPGAs are programmed using a logic circuit diagram or a source code in hardware description language (HDL). Digital Signal Processors (DSPs), such as microcontrollers have been used to control power electronics converters successfully. The high calculation speed these devices is applied to implement control algorithms for numerous applications by Software Routines (SR). Although, in some situations, is difficult to implement algorithms by way of softwares routines, for example multi-level modulation techniques (phase-shifted multicarrier SPWM and level-shifted multicarrier SPWM) or complex control algorithm (predictive or adaptive control). These limitations are due to fixed hardware architecture inner the microcontrollers and DSPs. In this context, FPGA devices are more attractive than SR implementation, because inherent parallelism of the logical resources on an FPGA allows to

Conventional DSP Device Data in

Data in

REG

X

+

C0

MAC

Data out

Fig. 1.

REG1

X

REG2

C1

X

REG3

C2

X

REG255

C255

X

UNIT

256 Loops needed to process

(a)

FPGA

+ Data out

All 256 MAC operations in single clock cycle

(b)

FPGA and Processor executing the same task, (a)-DSP, (b)-FPGA.

distinguish the modulation and control of the power electronics converter and consequently to improve the law control dynamics. In figure 1 is demonstrated an example of implementation of 256 multiply-accumulate operations between FPGA and numeric processor to explain the use of parallelism of the logic resources on an FPGA. II. FPGA APPLIED IN POWER ELECTRONICS Were the Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, who invented the first commercially viable field programmable gate array in 1985. Presently the main FPGA manufacturers are Actel, ALTERA, QuickLogic and Xilinx. FPGA has been used in power electronics [1]–[9] however the proceeding how the controllers are implemented it is not the main objective. Furthermore, generally the controllers are implemented by software routines, without to use all FPGA resources [2]. In [10] was proposed a DSP/FPGA hybrid system, that is an integrated and flexible hardware and software environment for electric drives control. Therefore, this paper proposes discrete time control design in FPGA, demonstrating the proceeding of controller implementation. Thus, using parallelism of the logic resources of FPGA is possible to improve the control dynamics. The control will be implemented in a single-phase PFC boost converter to validate the project methodology. In [2] an FPGA is also used to control a PFC boost converter, but in this case, a numeric processor was implemented inner FPGA, optimized to control that converter. Thus, there

BEGIN

BEGIN

Inicialization variables and constants

Inicialization variables and constants

iREF[k] Error = IREF[k]-IL[k] Error[k] Current Control Loop IM[k] IM[k] PWM Modulator NO

NO

Timer Interruption

Timer Interruption YES

YES

Variable Acquisition (Vin ) (IL) (VO)

Variable Acquisition (Vin ) (IL) (VO) (Vin )

(Vin )

Sinuisoidal Reference A[k]=ABS (Vin[k])

RMS value of (Vin ) C[k]=RMS value

(VO ) DC Voltage Feedback Control (VO ) B[k]=PIV

(C[k] )

iREF [ k ] =

A[ k ].B[ k ]

Sinuisoidal Reference A[k]=ABS (Vin[k]) RMS value of (Vin ) C[k]=RMS value

Multiply (A[k] )

Return to loop

(B[k] )

C[ k ]

DC Voltage Feedback Control (VO ) B[k]=PIV

iREF[k] Error = IREF[k]-IL[k] Error[k] Current Control Loop IM[k] IM[k]

Multiply

iREF [ k ] =

A[ k ].B[ k ] C[ k ] iREF[k]

PWM Modulator Return

Fig. 2. (a) Block Diagram of average current mode control implemented by FPGA. (b) Block diagram of average current mode control implemented by software routine.

are different ways to use FPGA device to implement the control in a power electronics converter. In this work, a dedicated hardware will be implemented to control all stages of a single-phase PFC boost converter (inrush, controllers, protection system etc). III. FPGA CONTROLLING PFC BOOST CONVERTER Discrete-time controllers applied in power electronics, generally, are implement alike the block diagram of Figure 3. Usually, there is an interrupt system, for example, events such as an internal timer overflow/underflow, completing an analog to digital conversion, a logic level change on an input such as from a button being pressed, and data received on a communication link. Posteriorly, the signals of power converter are sampled and computed by the law control. And, finally the signal is dispatched to digital PWM modulator. When the way to implement the controllers is by software routines, all strategy of control is executed in serial form, determined by clock frequency. For instance, to implement the average current mode control in PFC boost converter, the main sequence of algorithm is similar the Figure 2(b). Thus, after timer interruption, the ADC (Analog-Digital Converter) begins the data acquisitions. Generally, were used multiplexed AD channels in order to sample the signals needed for calculation. So, the processing error is further increased due to

the longer processing time of channels multiplexed. After data acquisition, all calculation begins. The sinusoidal waveform, feedforward AC voltage controller and DC feedback controller are executed in sequential form determining the reference signal to inductor current controller. Subsequent to current controller, the duty ratio of PWM is determined and updated. The main idea is all parts of control strategy being executed in serial and sequential form. Therefore, there is a delay between the instant of data acquisition and duty cycle update and a large delay will generally result in decrease of system stability. Otherwise, in FPGA the controllers can be implemented in dedicate hardware and thus some parts of control strategy might be executed in parallel. The Figure 2(a) demonstrates a form to implement average current mode control in singlephase PFC boost converter, by FPGA. In the data acquisition, it is not necessary to use multiplexed AD channels, because inherent parallelism of the logic resources on an FPGA. Furthermore, after data acquisitions, the sinusoidal waveform, feedforward AC voltage controller and DC feedback controller are executed independently in parallel. Therefore, the delay between the instant of data acquisition and duty cycle update is smaller than DSP implementation. In this moment, the synchronous state machine build in FPGA will be demonstrated. Thus, all logic sequence of strategy control is depicted.

cycles of clock between conversion and transference time. The both PI controllers requested 10 cycles of clock to process their difference equation. The data bus used in this project was 16 bits but this is not a FPGA limitation and the clock frequency employed in this project was 50 MHz.

0 TIMER INTERRUPTION

1

1

B. SPI Communication PWM MODULATOR

ADC AQUISITION

1

1

In the SPI communication it is necessary to follow the time specification of IC AD7367. The time line, presented in Figure 6, determines how this IC operates. After begin of conversion (CN V ST ) is necessary to wait the conversion time (BU SY ) and then to realize the SPI communication by serial clock (SCLK).

1 – YES 0 - NO

LAW CONTROL

CNVST

Fig. 3.

tQUIET

BUSY

Block diagram of a generic discrete-time controller.

CONVERSION TIME

CS

INTERRUPCAO

SCLK sub1_16bit

A. Synchronous state machine vmax[15..0]

The synchronous state machine controls ADC acquisition, both PI controllers (inductor current and DC voltage) and PWM modulator, as per Figure 4 and Figure 5.

dataa[15..0] 1 inst34

A B

1

result[15..0]

mux4_16bit

Fig. 6.

SPI

DC Voltage Controller

16

16

Current Controller

ADC Conversion

PWM

compare END

dataa[15..0] aeb datab[15..0]

vmax_reset

Time events sequence for SPI communication. inst9 data3x[15..0] data2x[15..0] data1x[15..0] data0x[15..0]

gnd[14..0],vcc[0]

Synchronous State Machine

14

portadora[15..0] PERIOD OF DATA ACQUISITION AND TRANSMISSION

START

A-B

vmax_comparador

SERIAL CLOCK

vmax[15..0] The Figure 8 demonstrates theresult[15..0] logic circuit, implemented gnd[15..0] in FPGA, to control SPI communication between FPGA inst55 sel[1..0] AD channels, there are and AD7367. On account of three config[1],toogle three identical circuits, as in Figure 8, operating inner FPGA independently.

Aritmetic Operation

SPI

16

ADC Conversion

Inductor Current

SPI

SPI

_CNVST1

clock50

16

clk _CNVST clock_spi _CS start SCLK BUSY READY DoutA dataA[13..0] DoutB dataB[13..0]

clock35

ADC Conversion

start_spi

Clock Signal

BUSY1

Clock

DoutA1 DoutB1

Synchronous state machine. wait

Fig. 4.

...

...

_CS1 SCLK1 ready_spi1 dataA1[13..0] dataB1[13..0]

control_clr

DC Voltage

inst

CLOCK

wait control_clr

35 Clock Cycle AD Conversion time and SPI

10 Clock Cycle

Fig. 8.

Digital circuit to implement SPI communication.

AC Voltage Aquisition DC Voltage Aquisition

t2

DC Voltage Controller

estagio2 to control AC current and DC voltage of PFC In this project, boost converter estágio2 were applied PI controllers. The difference equation (1) of PI controller (2) is presented in block diagrams input_pii[15..0] PI in Figure 9. The implementation of this PI controller in FPGA CTL_V_saturador clock inst47 clock is depicted in Figure 10. data3x[15..0] sel init_pii

Inductor Current Controller

data2x[15..0]

Time events sequence for synchronous state machine. data1x[15..0]

result[15..0]

datab[]

1 0

result[]

init input[15..0] A[15..0] 1 B[15..0]

da

da

output[15..0] rdy_pii

rdy

GND

t1

Fig. 5.

C. Law Control

Inductor Current Aquisition

data0x[15..0] u[k]dataa[] = u[k − 1] + ACTE_Ai (1) 0 .error[k] − A .error[k − 1] 32604 A total of three variables are necessary to controlinst24strategy,sel[1..0] BUSMUX 16 ctlsat_i[1..0] Y[n]=Y[n-1]+Ae[k]+Be[k-1] where: Parameter Value inst8 so in this project, there were used three ADC channels by IC WIDTH 16 inst17 CTE_Bi GND AD 7367 (14 bits). Thus, three channels of SPI communication A0 = 35414 KP 16 inst9 were implemented in FPGA, operating in parallel, requiring 35 A1 = KP .e−2πFZ TA

inst

es

Fig. 7. (a) Interval to execute PI controller; (b) Interval to execute all synchronous state machine (AD acquisition, SPI communication, PI controllers and PWM modulator).

P I[z] = KP 1 Z

E. Digital Pulse Width Modulator

z − e−2πFZ TA z−1

(2)

A1 -

A0

Limiter

+

Limiter

∑

U[k]

+ 1 Z

Fig. 9.

Block diagram of PI controller.

BUSMUX GND

PI clock

clock init input[15..0] A[15..0] B[15..0]

init_pii

CTE_Ai

inst48

result[]

out_pii[15..0]

1

sel

16

TA

estágio2

inst17

iM[k]

Current Control

estagio2

16

CTE_Bi 35414

rdy_pii

rdy

0

datab[]

output[15..0]

TA

-

32604

dataa[]

+

Error[k]

The PWM modulator in discrete-time control system has some particularity relative to analog modulator. The waveform of carrier has numeric limitation and thus limit cycle errors can happen. To avoid this phenomenon, the PWM modulator was implemented with individual synchronous state machine operating in parallel with controllers. Thus, the frequency of clock signal of PWM modulator is bigger than the clock frequency of controllers machine. To reduce the delay time between data acquisition and PWM update the multisampling strategies can be adopted [11]. In this project, the frequency of sampling was the double of switching frequency. The Figure 11, shown a block diagram of a discretetime PWM.

Y[n]=Y[n-1]+Ae[k]+Be[k-1]

Fig. 10.

MosFET Driver

PI controller implemented in FPGA. Ts

D. Inrush and protection system An inrush current protection system was development to limit the transitory current when the converter is first energized. A pre-charge circuit, with a resistor in series with the line, was used to limit the current charging of output capacitors. To keep a watch on DC output voltage after a few cycles (∆t = 100ms), the pre-charge circuit is disconnected. Just after this stage, the PWM modulator is abled and the converter operates as PFC. The protection system to measure the input current and output DC voltage. In the case of overcurrent the switch (MOSFET) is turn off. The same thing to DC output voltage, if overvoltage happens, the switch is turn off.

Ts Ts – Switching period TA – Acquisition event

Fig. 11.

Block diagram of Digital Pulse Width Modulator.

IV. E XPERIMENTAL R ESULTS The experimental investigation was performed based on a single-phase PFC boost converter, Figure 13, with the specifications listed in Table I. The main objective is to validate the synchronous state machine and demonstrate the PFC boost converter in operation.

Fig. 12.

Mains signals of synchronous state machine demonstrating in (a) the sampling frequency = 100 kHz ; (b) the switching frequency = 50 kHz.

TABLE I S INGLE -P HASE PFC B OOST S PECIFICATIONS Power Switching Frequency RMS AC Input Voltage Output DC Voltage Sampling Frequency

update the PWM. In Figure 12 is presented other signals of synchronous state machine and also the duty cycle of PWM. The sampling frequency is the double of switching frequency, to reduce the delay time between data acquisition and PWM update.

600 W 50 kHz 220 V 400 V 100 kHz

LB

DBoost

2mH

MUR860

VAC(wt) vin(t)

S

B. PFC Boost Converter

APT5025

vO(t) Ro

Co 1000uF 500V

266 Ω 600 W

VAC(wt)=310.sin(377.t) Intrumentation System (Anti-Aliasing Filter) MOSFET Driver

AD Converter AD7367

AD Converter AD7367

14

vin[k]

AD Converter AD7367

14

14

iL[k]

Low-Pass Filter

DC Voltage Controller

vO[k]

anti wind-up PI

-

+

In Figure 14 is depicted the AC current, AC voltage and DC voltage of PFC boost converter operating with digital control implemented in FPGA. The AC current has the same shape of AC voltage and DC voltage is regulated. These results are in steady state operating and demonstrate the average current mode control implemented successfully, by digital control, in an FPGA. In Figure 15 is shown current harmonic amplitude as a % of the component fundamental of input current.

400V

DC output voltage

Reference C[k]

iM[k] Controller

-

PWM Modulator

Fig. 13.

A[k]

PI

+

A[k].B[k] C[k]

Current Controller

-

+

iR[k]

AC input current

B[k]

FPGA Altera EP2C35F672C6

PFC Boost converter controlled by FPGA.

A. Synchronous State Machine The controllers inner the synchronous state machine require just 5 clock cycles to process the difference equation. In the Figure 7(a) there are demonstrated the experimental results of the interval necessary to executed this controller. And finally the Figure 7(b) presents all signal of synchronous state machine. After timer interruption (INIT),it begins the data acquisition and transference between AD 7367 and FPGA. In the end of SPI conversion, the controllers will process the data and send to the PWM modulator to update the duty cycle. All system demands just 700ns to process and

AC input voltage

Fig. 14.

Experimental results of AC current, AC voltage and DC voltage.

V. C ONCLUSION Discrete-time controllers have been used to control power electronics converters exhaustively, because of several advantages than analog control. Generally DSP’s and microcon-

Fig. 15.

Harmonic amplitude as a % of the fundamental.

trollers were used due to high calculation speed to implement the law control by software routines. Nevertheless, in some situations FPGA device are better than software routines implementation. Furthermore, using parallelism of the logic resources of FPGA, is possible to improve control dynamics. This paper show the design of synchronous state machine, implemented in FPGA, to control a single-phase PFC boost converter. Thus, a dedicated hardware was implemented to control all parts of converter (in-rush, controllers and protection system), without any software routine. The synchronous state machine inner FPGA determines when each part of control strategy should operate, and thus, this complex logic structure was analyzed incisively. Experimental results demonstrate the main signals of the state machine in FPGA and also, the PFC boost in steady state operating. ACKNOWLEDGMENT The authors gratefully acknowledge the financial assist provided by CAPES, the support of UFSC (Federal University of Santa Catarina) and INEP (Power Electronics Institute). R EFERENCES [1] W. Zhang, Y.-F. Liu, and B. Wu, “A new duty cycle control strategy for power factor correction and FPGA implementation,” IEEE Transactions on Power Electronics, vol. v.21,n.6,p.1745-1753, November 2006. [2] D. Borgonovo, M. Heldwein, and S. Mussa, “Application of the NIOS II processor-FPGA on the digital control of a single-phase PFC rectifier,” in Control and Modeling for Power Electronics, 2008. COMPEL 2008. 11th Workshop on, Aug. 2008, pp. 1–7. [3] D. Bester, J. du Toit, and J. Enslin, “High performance DSP/FPGA controller for implementation of computationally intensive algorithms,” in Industrial Electronics, 1998. Proceedings. ISIE ’98. IEEE International Symposium on, vol. 1, Jul 1998, pp. 240–244 vol.1. [4] J. Rodriguez-Andina, M. Moure, and M. Valdes, “Features, design tools, and application domains of FPGAs,” Industrial Electronics, IEEE Transactions on, vol. 54, no. 4, pp. 1810–1823, Aug. 2007. [5] M.-W. Naouar, E. Monmasson, A. Naassani, I. Slama-Belkhodja, and N. Patin, “FPGAs-based current controllers for ac machine drives − A review,” Industrial Electronics, IEEE Transactions on, vol. 54, no. 4, pp. 1907–1925, Aug. 2007. [6] Y. F. Chan, M. Moallem, and W. Wang, “Design and implementation of modular FPGAs-based PID controllers,” Industrial Electronics, IEEE Transactions on, vol. 54, no. 4, pp. 1898–1906, Aug. 2007. [7] O. Lopez, J. Alvarez, J. Doval-Gandoy, and F. Freijedo, “Multilevel multiphase space vector PWM algorithm,” Industrial Electronics, IEEE Transactions on, vol. 55, no. 5, pp. 1933–1942, May 2008.

[8] E. Bueno, A. Hernandez, F. Rodriguez, C. Giron, R. Mateos, and S. Cobreces, “A DSP- and FPGA-based industrial control with highspeed communication interfaces for grid converters applied to distributed power generation systems,” Industrial Electronics, IEEE Transactions on, vol. 56, no. 3, pp. 654–669, March 2009. [9] X. Lin-Shi, F. Morel, A. Llor, B. Allard, and J.-M. Retif, “Implementation of hybrid control for motor drives,” Industrial Electronics, IEEE Transactions on, vol. 54, no. 4, pp. 1946–1952, Aug. 2007. [10] Z. Bielewicz, L. Debowski, and E. Lowiec, “A DSP and FPGA based integrated controller development solutions for high performance electric drives,” in Industrial Electronics, 1996. ISIE ’96., Proceedings of the IEEE International Symposium on, vol. 2, Jun 1996, pp. 679–684 vol.2. [11] L. Corradini and P. Mattavelli, “Modeling of multisampled pulse width modulators for digitally controlled dc–dc converters,” Power Electronics, IEEE Transactions on, vol. 23, no. 4, pp. 1839 –1847, july 2008. [12] A. Peterchev and S. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters,” Power Electronics, IEEE Transactions on, vol. 18, no. 1, pp. 301–308, Jan 2003. [13] H. Ren and T. Ninomiya, “The overall dynamics of power-factorcorrection boost converter,” in Power Electronics Specialists Conference, 2005. PESC ’05. IEEE 36th, June 2005, pp. 577–581.