International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July 2013 pp- 13-21
Synthesis of R-L-C Circuit Using Embedded System Design Techniques FPGA Mazin Rejab Khalil1, Shaima Mohammed Ali2 * (Department of Computer Technical Engineering, Technical College, Mosul, Iraq) ** (Department of Computer Technical Engineering, Technical College/ Mosul, Iraq
[email protected])
ABSTRACT The paper aims to synthesize R-L-C circuit with the aid of Embedded Design Techniques (EDTs). Soft-core processor system is developed and configured on Spartan 3E FPGA slice. The system is programmed by C language and accommodated to synthesize R-L-C circuit. Cauer synthesis method based on the Continued Fraction Expansion analysis is used to infer the form of the circuit, type of components and their values from the transfer function of the circuit. The work provides a simple algorithm to synthesize analog filters with the aid of soft-core processor system.
Keywords- Continued Fraction Expansion Method, Cauer Method, Embedded Design Techniques, FPGA.
I. INTRODUCTION Embedded design techniques facilitate constructing a processor system with its peripherals to be configured on FPGA. Soft-core processors provide several advantages over custom designed processors such as reduced cost, flexibility, platform independence and greater immunity to obsolescence [1]. Embedded Systems consist of hardware and software components that are working together to perform a specific application. Synthesizing R-L-C circuit using continued fraction expansion depends a transfer function as described [2] in equation: (1)
=
⋯ ⋯
(1)
In order to synthesize a driving point function into a passive network using resistors, inductors and capacitors, it must be positive real and satisfy the constraints of stability and causality. Immittance is the word used generically for impedances and admittances [3]. The function to be stable, its poles must be restricted to the left-half plane or the jw axis, Where the denominator polynomial of the system function belongs to a class of polynomial Known as Hurwitz polynomials [3]. F(s) is said to be Hurwitz if F(s) is real when s is real. And the roots of F(s) have real parts which are zero or negative. In this work the designed processor system is programmed to fulfill the synthesis procedure of R-L-C circuit by analyzing the transfer function to deduce the type of components composing the circuit, their connective and their values. The design procedure includes explaining the principles of embedded design techniques and the construction of the processor system, synthesis techniques and continuous fraction expansion, results and discussion.
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July 2013 pp- 13-21
Embedded Processor System Xilinx Platform Studio (XPS) provides an integrated environment for creating software and hardware specification flows for embedded processor systems based on MicroBlaze™ [4]. Hardware platform is a term that describes the flexible, embedded processing subsystem creating with Xilinx technology for the application needs. The hardware platform consists of processor and peripherals connected to the processor buses, which is captured in the Microprocessor Hardware Specification (MHS) file. MHS file defines the system architecture, peripherals, and embedded processors. It also defines the connectivity of the system, the address map of each peripheral in the system and configurable options for each peripheral. A software platform [4] is a collection of software drivers and the operating system on which the application is built. The embedded software platform defines the drivers associated with the peripherals included in hardware platform, selected libraries, and standard input/output devices; interrupt handler routines, and other related software features, it also defines software applications to be run on processor, the Microprocessor Software Specification (MSS) file together with software applications, are the principal source files that represent the software component of embedded system. The designed embedded soft-core processor system is shown in Fig.1
Fig.1 The block diagram of the designed embedded softcore processor system The soft-core processor system consists of the following items: • MicroBlaze Processor • Local Memory Bus (LMB). • BLOCK RAM (On-chip memory) • LMB BRAM controllers for BRAM • On-chip Peripheral Bus (OPB). • Debug Module (OPB_MDM) • 2UART (OPB_UARTLITE) DCE/DTE. • DDR-SDRAM • Multi-Port Memory Controller (MPMC) • Clock generator. • Processor System Reset. • Dip Switches • LED. The MicroBlaze processor is a 32-bit Harvard Reduced Instruction Set Computer (RISC) architecture optimized for implementation in Xilinx FPGAs with separate 32-bit instruction and data buses running at full speed to execute programs and access data from both on-chip and external memory at the same time [1]. The processor has up to three interfaces for memory accesses: Local Memory Bus (LMB), IBM’s On-chip Peripheral Bus (OPB), and Xilinx Cache Link (XCL). The LMB provides single-cycle access to on-chip dual-port
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July July 2013 201 pp- 13-21
block RAM (BRAM).The OPB interface provides a connection to both on on-chip and off-chip chip peripherals and memory. The Cache Link interface is intended for use with specialized external memory controllers. The universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface fo forr asynchronous serial data transfer. This soft IP core is designed to interface with the PLBV46 [5].This is used to display result on hyper terminal. External Memory Controller (EMC) provides the control interface for external 16 Mbytes flash PROM [6]. Multi-Port Port Memory Controller MPMC is a fully parameterizable memory controller that supports 64 Mbytes DDRDDR SDRAM memories which is used for program execution [7].
II. SYNTHESIS TECHNIQUES A network with a finite number of elements (R, L, and C) has a driving point immittance of the form [3] in equation: (2)
=
⋯ ⋯
2
Where all coefficients ai and bi are real. Also, due to the constraints imposed by causality and stability F(s) must be what is called a positive real (p.r.) function; Re{ F(s)} > 0 if Re{ s} > 0 (3) Re{ F(s)} ≥ 0 if Re{ s} = 0 (4) These conditions ((2), (3) and (4)) )) form necessary and sufficient conditions for the realizability of F(s) with R, L and C components only [3].
III. CONTINUED FRACTION EXPANSION PANSION The continued fraction expansion is the ratio of the odd to even parts or even to odd parts of Hurwitz polynomial yield all positive quotient terms. Suppose we denote the ratio as r(s) = N(s) / D(s) or r (s) = D(s) / N(s), then the continued fraction expansion based on Cauer method is an express express-ion in the form as shown in equation: (5) [3] . (5)
Where the quotients q1, q2… qn must be positive, and to obtain continued fraction expansion we must perform a series of long divisions. Suppose r (s) = D(s) / N(s) where D(s) is higher in degree than N(s). The process of obtaining the continued fraction expansion of r(s) simply involves division and inversion. Each quotient represents a physically realizable component [8] .Number of elements p equals number of non-zero non quotients in obtained continued fractionn [8] as shown equation: (6) (6)
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July July 2013 201 pp- 13-21
Where Z represent impedance. Y represent admittance. The quotients became alternately impedances or admittances, connected in ladder network. Impedances are placed in ladder network as longitudinal (series) elements; admittances are placed in ladder network as shunt elements as shown Fig.2
Fig.2 Ladder network
IV. SYNTHESIS ALGORITHM In order to synthesize a network from a given system transfer function, the following steps are adopted: 1. 2. 3.
4. 5.
Define the variables N1, N2 to represent the number of nonzero coefficient in the numerator and denominator respectively. Store in ascending order the numerator coefficient and corresponding exponent of "s" in a matrix named (b_NUM). Store in ascending order the denominator coefficient and corresponding exponent of "s" in a matrix named (a_DEN). Defining the type of transfer function to be "Z" for impedances and "Y" for admittance. Check the number of nonzero coefficient in the numerator (N1) and denominator (N2). a. If (N1> N2) interchange the deno deno-minator minator with numerator. Create tracking algorithm to track the number of interchange process. Establish the process of continued fraction expansion. b. If (N1≤ ≤ N2) (or the previous step achieved and negative terms are still obtained in the reminder), reveres the arrangement of both numerator and denominator polynomials in "s". c. If negative term during the process is obtained in the reminder, rearrange both numerator and denominator polynomials in "s", during the process in order to keep the quotients positive. d. If the program fails to eliminate negative terms, it will display mess message age that the transfer function is not synthesizable by using continued fraction expansion. e. Final step is to display the resultant circuit, the type of component composing the circuit, their connection and their values.
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July 2013 pp- 13-21
The flow chart of the synthesis program that is executed on the soft-core processor system is shown in Fig.3 START
Input Nonzero Coefficient
Input numerator coefficient and exponent of NUM in
b_NUM Input numerator coefficient and exponent of DEN.in
_ Input the Type of Immittance
Y
N
N1>N2
Reveres F(s) To 1/F(s) / NUM DEN
Normal F(s) DEN /NUM
Continued fraction process
Continued fraction process
1 Negative
Test residue
Ascending order of "s" both NUM, DEN
Continued fraction process
Positive
RESULT
Y(s) Z(s)
LC
CL Circuit
RESULT
Y(s)
RL , Z(s) RC OR RLC circuit
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July 2013 pp- 13-21
1
Positive
Negative
Test residue
Ascending order of "s" both NUM, DEN
RESULT Y(s)
LC
Z(s)
CL circuit
Continued fraction process
RESULT Y(s)
RL
Z(s)
RC OR RLC circuit
Fig.3 The flowchart of the synthesis program.
V. RESULTS The performance of the designed system is tested for synthesizing the following transfer Function. 1. Zs =
s + 5s + 4 7 s + 5s + 6
2. ys =
2s + 8s + 6 8 s + 8s + 12
3. Zs =
2s + 12 s ! + 16s 9 s " + 4s + 3
Fig.4 displays the result of the synthesizing the transfer function described by equation: (7) the synthesized circuit is RLC type and arranged in the form of Fig. 5
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July July 2013 201 pp- 13-21
Fig.4
Fig .5 Fig.6 displays the result of synthesizing the transfer function described by equation: (8) the synthesized circuit is RC type and arranged in the ladder form of Fig.7
Fig.6
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July July 2013 201 pp- 13-21
Fig.7 Fig.8 displays the result of synthesizing the transfer function described by equation: (9) the synthesized circuit is LC type and arranged in the ladder form of Fig. Fig.9
Fig.8
Fig.9
VI. CONCLUSION An Embedded designed processor system is designed and adapted to be used in synthesizing RLC circuit. The work shows that the field programmable gates array (FPGAs) can be exploited in the field of transfer functions realization which is necessary for designing gning analogue filters. This conjunction between embedded design, FPGAs and circuit theory creates a novel path for designing analogue filters.
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International Journal for Research and Development in Engineering (IJRDE) www.ijrde.com
Vol.2: Issue.1, June-July 2013 pp- 13-21
REFERENCES [1] Rod Jesman, Fernando Martinez Vallina ,MicroBlaze Tutorial Creating a Simple Embedded System and Adding Custom Peripherals Using Xilinx EDK Software Tools: A tutorial review,. Embedded Computing and Signal Processing Laboratory – Illinois Institute of Technology http://ecasp.ece.iit.edu. [2] SONAL S. KHILARI, Transfer Function And Impulse Response Synthesis Using Classical Techniques, master of science in electrical and computer engineering, Massachusetts University Amherst, 2007. [3] F.F. Kuo, Network Analysis and Synthesis, (Wiley, 1966). [4] XILINX INC., Platform Studio Help: A tutorial review, version 10.1 www.xilinx.com. [5] Xilinx Company, XPS UART Lite (v1.01a): A tutorial review, Proc. DS643, April 19, 2010 .http://www.xilinx.com [6] Xilinx INC., XPS Multi-Channel External Memory Controller (v3.01a): A tutorial review, Proc. DS575 Apr 19, 2010 .http://www.xilinx.com [7] Xilinx Company, Multi-Port Memory Controller (MPMC) (v6.00.a): A tutorial review, Proc. DS643, April 19, 2010. www.xilinx.com. [8] Ph. D. Sikorski, T., Materials for the classes on Selected Problems in Circuit Theory http://eportal.eny.pwr.wroc.pl/
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