Test Infrastructure Design for Core-Based System

Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints Thomas Edison Yu†, Tomokazu Yoneda†, Krishnendu Chakrabarty‡ and Hideo Fujiwara† † Nara Institute of Science and Technology ‡ Duke University

Nara Institute of Science & Technology

Outline • Background – Core-based testing – Power / Heat-related problems during test – Limits of power-constrained SoC testing • Related Works • Objectives • Proposed Method: – Fixed-TAM architecture – Scheduling techniques – Thermal model & cost function • Experimental Results • Summary 2

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Core-Based System-on-Chip • SoC (System-on-Chip)： – One-chip system – Use pre-designed functional blocks called IP cores – Reduced design and manufacturing cost • IP design and test re-use

• Test challenges – – – –

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High test data volume Limited access to internal circuitry Long test application time (TAT) High test power and temperature

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Design for Test (DFT) for SoCs • TAM (Test Access Mechanism)

• Wrapper – Isolates CUT from other cores during test – Interfaces TAM & core – Enables test reuse

– Dedicated test bus connecting test source/sink and core-under-test (CUT)

WRAPPER MPU 1G H z DRAM 500M H z

Source

Limited # of I/O pins 4

TAM

Sink

TAM

UDL 300MHz

M PEG 200M H z

I/O 100MHz

DSP 150M Hz

Most cores not directly controllable or observable http://www.naist.jp/

Test Scheduling • Determine test sequence for each core • Minimize test time under certain constraints – Power, TAM width, temperature, etc. – Parallel testing results in high test power and temperature TAM Overall TAM width

Core 1

Core 2

Core 3

TAM width x Time

Core 6 5

Core 4 Core 5 Time t http://www.naist.jp/

Power & Heat-related Issues During Test • High test power dissipation – can cause chip damage or random errors – result in yield loss

• High power dissipation can cause overheating – every 20oC rise in temperature = approx. 5-6% timing delay – chip packaging are designed for worst case typical application

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Limits of Power-constrained SoC Testing Ignore non-uniform spatial power distribution across chip

Testing 5 cores in parallel

– layout, core proximity affects temperature – can’t ensure thermalsafety

•

11 22 33 P=100 P=100 P=100 P=100 P=100 P=100

11 22 33 P=100 P=100 P=100 P=100 P=100 P=100

44 55 66 P=100 P=100 P=100 P=100 P=100 P=100

44 55 66 P=100 P=100 P=100 P=100 P=100 P=100

77 88 99 P=100 P=100 P=100 P=100 P=100 P=100

77 88 99 P=100 P=100 P=100 P=100 P=100 P=100

Max. Power and Temp. for p93791 SoC

Ignore effect of time on temperature

60000

180

Max. Power

Max. Temp.

160

50000 140

Max. Power

40000

120

100 30000 80

20000

Max. Temp. (C)

•

60

40 10000 20

0

0 1

2

3

4

5

Schedule No.

*Results using HotSpot temp. simulator (Skadron et al., ISCA’03)

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Objectives • Given an SoC, test data and maximum allowable temperature, Propose a thermal-safe test architecture design and test scheduling methodology – the given thermal constraint is satisfied at any time during test – the test application time is minimized

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Related Works • Thermal-safe test scheduling (Rosinger et al., DATE’05) – group cores with fixed wrappers into test sessions – minimize temperature per session

• Uniform heat distribution (Liu et al., DFT’05) – use layout information to determine wrapper configuration and test schedule

• Test set partitioning and interleaving (He et al., DFT’06)

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– partition test set when temperature constraint is exceeded – interleave test partitions sequentially, allow other cores to cool down http://www.naist.jp/

Characteristics of Related Works • Use constant power per core • Ignore effects of active cores on non-active cores • Do not optimize both the TAM and Wrapper configuration • Thermal-safe TAM / Wrapper Co-optimization (Yu et al., ATS’07) – use cycle-accurate power profiles per core wrapper configuration – consider heat exchange across all cores and test sequence via heat dissipation paths – first work to optimize TAM and Wrapper under a thermal constraint 10


Research Contributions • Improvements over work done for ATS`07 – – – –

Allow schedule reshaping Allow dynamic test partitioning and interleaving Allow insertion of bandwidth matching circuitry Find solutions under much tighter temperature constraints

• Preserve advantages of ATS`07 work – Cycle-accurate power and temperature profiles – Consider inter-core temperature effects – Optimize TAM & Wrapper architecture

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Target Test Architecture • Characteristics: 1. TAM has fixed partitioning 2. Cores are assigned to only one TAM partition 3. Cores in the same TAM scheduled sequentially, order is variable 4. Cores in different TAMs can be scheduled in parallel c1 c1

c3 c3

c5 c5

c5

c8 c8

c6 c10

TAM 1 = 16bits TAM 1 = 16bits

c2 c2

c6 c6 TAM 2 = 8bits TAM 2 = 8bits

c4 c4

c7 c7

c9 c9

TAM 3 = 8bits TAM 3 = 8bits

SoC SoCd695 d695 12

c10 c10

c3

c3 c1

c5 c6 c10

Schedule A

c8 c2 c7 c4 c9 c1 c8 c2 c4 c7 c9

Schedule B

Time t http://www.naist.jp/

Test Schedule Reshaping, Partitioning & Interleaving • Test schedule reshaping – Reconfigure schedule to minimize temperature of target core – Ex. Avoid testing hot cores in parallel and in sequence

c4

c9 c6 c10

• Test partitioning and interleaving

c5

– Partition test before temperature exceeds constraint c5 c6 c10 13

c5

c3 c1 c8 c2 c7

c4 c9

Max. Temp = 110oC

c7

c8 c2

c6 c4

c10

c1

c3 c8

c5a c3 c5bc1

c3 c1

c8 c2

c7 c2

c9

Max. Temp = 100oC

c7

c6 c10

c4 c9

Max. Temp = 95oC http://www.naist.jp/

Bandwidth Matching • Frequency throttling – lower scan frequency => lower power

• Add bandwidth matching circuitry to TAM partition – 2*TAM width, ½ freq. => temperature reduction ideally w/o TAT increase

Core Core 11

Core Core 22

Core Core 33

TAM

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Bandwidth Matching • Frequency throttling – lower scan frequency => lower power

• Add bandwidth matching circuitry to TAM partition – 2*TAM width, ½ freq. => temperature reduction ideally w/o TAT increase

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Core Core 22

TAM TAM

Core Core 33

MUX MUX

DMUX DMUX

Core Core 11


Proposed Method Flow Initial TAM design & schedule

•

Thermal simulation maxT≦Tempmax

– YES

NO Reshape possible

YES

•

Reshape schedule

YES

Do partitioning

need heuristic scheduling algorithm

Thermal simulation is time consuming –

NO Can partition hot core?

Scheduling is NP-Hard

–

need simplified thermal model need simple thermal cost function

NO Virtual TAM limit reached?

YES

END

NO

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Do bandwidth matching http://www.naist.jp/

Thermal Model • Model SoC as a network of thermal resistances – first proposed by P. Rosinger, K. Chakrabarty, et.al (DATE’05) – takes advantage of thermal and electrical duality – only consider lateral thermal resistances •Models lateral heat flow •More heat flow from cores = higher temperature

CORE1

CORE2

R2,North

R1,North

R1,west

R1,2 R1,3

TAM

R2,1

R2,East R2,3

CORE3

R3,1

R3,2

Core 1 R3,South

Core 3 Core 2 17

t


Thermal Cost Function •

Initial TAM design & schedule

Tcontj (ci): thermal contribution of Core j to Core i

Thermal simulation

Tcont j (c i ) = maxT≦Tempmax

YES

YES

Reshape schedule

NO

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Do bandwidth matching

TATi

RTOT , j : Total lateral resitance of core c j Pavg j : Average power dissipation of c j Trel ji : Relative test time of c j and c i

YES

Do partitioning

Minimize thermal contribution to hotspot core

NO Virtual TAM limit reached?

Trel ji

from core c j to c i , (Rii = 0)

NO Can partition hot core?

RTOT , j

× Pavg j ×

where : R ji : Lateral thermal resistance

NO Reshape possible

R ji

YES

END

Reset cost values and revert to initial schedule http://www.naist.jp/

Experimental Setup • Benchmark ITC’02 SoCs – d695, p22810 with hand-crafted layouts – cycle-accurate power profiles from Samii et al. (“Cycle- Accurate Test Power Modeling and its Application to SoC Test Scheduling,” Proc. of IEEE International Test Conference (ITC), pp. 110, 2006)

• Scheduling parameters – TAM = 16, 24, 32, 64 – Tmpmax : initially set to max temperature of schedule under no power & thermal constraint • decreased by 5oC intervals 19


Max. Temperature & Power vs. Temp. Constraint

Max. Temp, Max. Power vs. Temp. Constraint

120.00 110.00 100.00 90.00 80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00

1800 1600

Max. Temp.

Max. Power

1400 1200 1000 800

Relatively constant max. power but temperature was lowered further

600 400

Max. Power (switches)

Max. Temp. (deg. C)

• d695 with TAM = 16bits

200 0 ∞

106.28101.28 96.28 91.28 86.28 81.28 76.28 71.28 66.28 61.28 56.28 Temp. Constraint (deg. C)

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Max. Temperature & TAT vs. Temp. Constraint

120.00 110.00 100.00 90.00 80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00

Max. Temp, TAT vs. Temp. Constraint

140000 120000

Max. Temp.

TAT 100000 80000 60000

TAT (cycles)

Max. Temp. (deg. C)

• d695 with TAM = 16bits

40000 20000 0 ∞ 106.28101.28 96.28 91.28 86.28 81.28 76.28 71.28 66.28 61.28 TAT 56.28 Relatively minimal

change but temperature was lowered further

Temp. Constraint (deg. C)

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Max. Temperature & Power vs. Temp. Constraint • p22810 with TAM = 32bits

Max. Temp. (deg. C)

160

Max. Temp, Max. Power vs. Temp. Constraint Max. Temp.

Max. Power

140 120

6000

80 60 20

10000 8000

100

40

12000

4000

lower max. power doesn’t ensure lower temperature

2000

Max. Power (switches)

180

0

16 ∞ 1. 1 15 7 6. 1 15 7 1. 1 14 7 6. 1 14 7 1. 1 13 7 6. 1 13 7 1. 1 12 7 6. 1 12 7 1. 1 11 7 6. 1 11 7 1. 1 10 7 6. 1 10 7 1. 17 96 .1 7 91 .1 7 86 .1 7 81 .1 7 76 .1 7 71 .1 7

0


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Max. Temperature & TAT vs. Temp. Constraint • p22810 with TAM = 32bits

Max. Temp. (deg. C)

160

Max. Temp, TAT vs. Temp. Constraint Max. Temp.

600000

TAT 500000

140

400000

120 100

300000

80

200000

60 40

TAT (cycles)

180

100000

20

0

16 ∞ 1. 1 15 7 6. 1 15 7 1. 1 14 7 6. 1 14 7 1. 1 13 7 6. 1 13 7 1. 1 12 7 6. 1 12 7 1. 1 11 7 6. 1 11 7 1. 1 10 7 6. 1 10 7 1. 17 96 .1 7 91 .1 7 86 .1 7 81 .1 7 76 .1 7 71 .1 7

0


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Minimum Temperature Comparison Max. 40% reduction in minimum temperature

TAM=16

TAM=24

SoC

ATS’07

Proposed

dTAT(%)

ATS’07 Proposed dTAT(%)

d695

92.79C

55.8C

-152

91.49C

58.46C

-46

p22810

133.02C

77.71C

-53

110.1C

102.29C

7

TAM=32

24

TAM=64

SoC

ATS’07

Proposed

dTAT(%)

ATS’07 Proposed dTAT(%)

d695

77.15C

69.91C

16

84.71C

80.59C

26

p22810

109.36C

71.17C

-98

107.25C

92.79C

-20 http://www.naist.jp/

Summary • Studied the impact of test-set partitioning, bandwidth matching on thermal-aware TAM / Wrapper optimization and test scheduling • Algorithm based on computationally tractable thermal-cost model makes thermal simulation more useable; ensures thermal safety • The results show that: – method allows more flexibility to trade-off temperature and TAT while minimizing TAT increase – method provides solutions even under tight temperature constraints, including situations where previous work fails to find a solution

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