The Front-End Readout as an Encoder IC for ... - Semantic Scholar

sensors Article

The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors Trong-Hieu Tran, Paul Chang-Po Chao * and Ping-Chieh Chien Department of Electrical Engineering, National Chiao Tung University, Hsinchu 200, Taiwan; [email protected] (T.-H.T.); [email protected] (P.-C.C.) * Correspondence: [email protected]; Tel.: +886-3-513-1377; Fax: +886-3-575-2469 Academic Editors: Teen-Hang Meen, Shoou-Jinn Chang, Stephen D. Prior and Artde Donald Kin-Tak Lam Received: 8 June 2016; Accepted: 23 August 2016; Published: 2 September 2016

Abstract: This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm2 , while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is −0.79–0.95 LSB while the differential non-linearity (DNL) is −0.68–0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within ±15 µm for a measuring range of 10 mm. Keywords: magnetic linear scales; encoder readout IC; programmable gain amplifiers (PGAs); successive approximation register (SAR) analog-to-digital converters (ADCs)

1. Introduction The developments of precise measurement and positioning devices have been applied to manufacture processing and testing equipment in the fields of electronic and semiconductor industries. In these devices, linear scale encoders are widely used to detect angular and/or translational positions of the moving part in high-precision machines and robots as the most common position sensors [1–13]. However, the frequency response of the conventional encoders is limited; thus, they cannot be used in the case of high-speed motions. This problem can be mitigated with a high-resolution linear scale equipped with a high-speed front-end readout and signal processing chip, which can output harmonic signals to obtain greater accuracy and higher resolution. Among different scales, it is known that magneto-resistance (MR) scales, as compared to other scales, especially optical scales [2–10], have the Sensors 2016, 16, 1416; doi:10.3390/s16091416

www.mdpi.com/journal/sensors

Sensors 2016, 16, 1416

2 of 13

advantages of low cost, high speed, accuracy and adequate precision. In comparison of the accuracies offered by MR and optical scales, the optical scale using the reflection principle could achieve a resolution higher than the MR scale, but the MR scale requires much lower costs for components and manufacturing. Much effort was recently made by researchers [4–8] to design successfully and to fabricate an MR scale with a new MR electrode layout and material, aiming to increase the sensing range and resolution of the magnetic scale to the level compatible with the optical scale. A typical MR sensor is shown in Figure 1, which consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple S and N magnets, while another is 16, an1416 “MR reader” stage with multiple MR grid electrodes and moving on the rails of Sensors 2016, 2 ofthe 13 base. With the stage in motion, the magnetic interaction between the moving reader and the scale base especially scales [2–10], have the advantages low cost, highThe speed, accuracy adequate causes the optical variation of the magneto-resistances of the of grid electrodes. electrodes areand designed in a precision. In comparison of Figure the accuracies offeredsinusoids by MR and scales, at theoutputs opticalAscale using particular way, as shown in 2b, to generate andoptical co-sinusoids ± and B± the principle achieve avariations resolutionthrough higher than the MR scale, but as theshown MR scale requires thatreflection are proportional tocould the resistance a Wheatstone bridge, in Figure 2a. much lower costs for components and manufacturing. Much effort was recently made by The resulted sinusoids and co-sinusoids in Figure 2b can next be deciphered by a succeeding readout researchers [4–8]the to design fabricate an MR scalein with a new to MR electrode chip to acquire movingsuccessfully distance ofand the to reader [2–11]. In fact, addition the design layout of MR and material, aiming to increase the sensing range and resolution of the magnetic scale to the electrodes, another critical technology involved in magnetic scales is the readout IC, which needs level to be compatible with the optical scale. variations of MR electrodes to digits in a high signal-to-noise ratio capable of converting the resistance A typical MR sensor is showndigital in Figure 1, which of two major one is its base and then deciphering the resulting harmonics to consists reader positions. Basedparts: on the principles of structure, also called the magnetic scale, which is embedded with multiple S and N magnets, while the IC circuit design, the performance of the readout circuit for sensing reader position in real time another is an “MR stage and withspeed multiple MRfront-end grid electrodes on thereadout, rails of the highly depends on reader” the accuracy of the readout.and In moving the front-end base. With the stage in motion, the magnetic interaction between the moving reader and theoffsets scale input harmonic signals from the MR scale need to be amplified to full dynamic range, with zero base causes the variation of the magneto-resistances of the grid electrodes. The electrodes are and no phase error between sinusoids and co-sinusoids [5–12] before entering the analog-to-digital designed a particular way, as shown in Figurethe 2b,processing to generate sinusoids co-sinusoids at outputs converter in ADC for high accuracy. Furthermore, speed of theand ADC has to be high enough A± and B± that are proportional to the resistance variations through a Wheatstone bridge, as shown to cope with the high moving speeds of the reader as opposed to the MR scale base. in Figure The aresulted sinusoids and Figure 2b canbynext be electrodes decipheredofby a In this2a. study, magneto-resistive (MR)co-sinusoids linear scale in sensor realized planar MR succeeding readout chip to front-end acquire the moving distance theelectrodes reader [2–11]. fact, in to material is designed for the readout circuit. Theof MR in theIn sensor areaddition connected the of MR another critical technology in magnetic scales is the readout as indesign a structure of electrodes, a Wheatstone bridge, as shown in Figureinvolved 2a. Succeeding the MR Wheatstone bridge IC, needs to be capable of converting the resistance variations of MRfrom electrodes digits and in a is awhich front-end readout circuit proposed to extract the sine/cosine signals the MRtosensor high signal-to-noise ratio and then deciphering the resulting digital harmonics to reader positions. then converted to digital values by a newly-designed 12-bit hybrid successive approximation register Based on theThe principles offabricated the IC circuit design, the performance Manufacturing of the readout circuit for sensing (SAR) ADC. chip was by the Taiwan Semiconductor Company—TSMC reader position in real highly depends on the accuracy and speed of the front-end readout. In (Hsinchu, Taiwan) and time corresponds to the TSMC 0.35-micron CMOS technology, which was used for the front-end readout, the input harmonic signals from the MR scale need to be amplified to full verification purposes. A digital decoder is orchestrated and implemented by field programmable gate dynamic range, with offsets no phase error between sinusoids and co-sinusoids [5–12] array (FPGA) codes to zero decipher the and harmonic outputs from the ADC via the technique of interpolation before entering the analog-to-digital ADC accuracy. Furthermore, processing to the actual position of the moving converter reader stage in for realhigh time. It was found that thethe displacement speed of the ADC has to be±high to cope with high speeds of the reader as measurement error is within 15 µmenough for a measuring rangethe of 10 mmmoving as compared to the measurement opposed to thelaser MR scale base. by a precision displacement sensor.

MR reader Magnetic Scale Base

Figure Figure 1. 1. Operation Operation principles principles of of aa magnetic magnetic linear linear scale. scale. 0.5

VCC B

A A3

A2 A+

A-

B3

B2 B+

B-

0.5

0.5

A1 B1 A2 B2 A3 B3 A4 B4

MR reader Magnetic Scale Base

Sensors 2016, 16, 1416

3 of 13

Figure 1. Operation principles of a magnetic linear scale. 0.5

VCC B

A

A+ A1

A-

B+ A4

A1 B1 A2 B2 A3 B3 A4 B4

B3

B2 B-

B1

B4

GND

Resistance (Ohm)

A3

A2

0.5

0.5

sinusoid

co-sinusoid Text

Distance (mm)

(a)

(b)

Figure 2. (a) Wheatstone bridge; (b) electrode layout and resulting harmonic resistance variation. Figure 2. (a) Wheatstone bridge; (b) electrode layout and resulting harmonic resistance variation.

The rest of the paper is organized as follows. Section 2 describes the design concept and architecture of the circuit. Section 3 shows the experiment results. Conclusions are given in Section 4. 2. Chip Architecture Design The readout chip for MR sensors proposed in this study consists of two programmable gain amplifiers (PGAs) with common-mode feedbacks for zero DC offset, two 12-bit analog-to-digital converters (ADCs) and a comparator circuit. The readout chip is aimed to extract signals from an MR sensor and then processing it to accurate digital displacement of the moving reader stage in 12 bits. 2.1. Programmable Gain Amplifier The MR sensor provides two output signals for varying MR resistances. One is sinusoid, while another is the associated co-sinusoids expected to be in a phase difference of 90◦ relative to the sinusoid. The resistances of the MR sensor are small around 100 kΩ, even with the material of boron mixed in the magneto-resistive material. Thus, in the readout, a programmable gain amplifier (PGA) of input high impedance and adequate gain is first designed [13–17]. The gain of this amplifier is expected to amplify the incoming sinusoids and co-sinusoids to the full dynamic range for the maximum signal-to-noise ratio (SNR) and also zeroing the DC offset. The proposed PGA is shown in Figure 3, which is in a topology of a differential instrumentation amplifier (IA) for large gain tuning ranges. This PGA in fact consists of three operational amplifiers (OPs), which are two identical single-input op-amps and one fully-differential folded cascade. The overall gain of this IA is: Ry Vout 2R = (1 + 1 ) × Vin RX R2

(1)

where Rx and Ry are realized by on-chip resistor arrays of MOS switches, as illustrated in Figure 4, to realize tunable gains with the aim to reach full dynamic range at the outputs for sinusoid and the associated co-sinusoids. Rx is tunable in two digital bits and responsible for coarse tuning, while Ry is in four bits and responsible for fine tuning. Ry is automatically adjusted in an on-line fashion based on the output, Vout ±, while Rx is tuned externally by two bits given by an external FPGA module. As a result, the differential output voltage is expected to be amplified successfully to full dynamic ranges at Vout ±. Since the performance of this PGA mainly depends on op-amps, thus, high performance op-amps are required, especially for OPout at the out stage of the IA, in Figure 4. For this OPout , a fully-differential folded cascade is proposed and shown in Figure 5. A folded cascade op-amp uses cascading in the output stage combined with a special implementation of differential amplifier to achieve favorable input common-mode input range. This folded cascade op-amp is expected to offer self-compensation, good input common-mode range and a large gain of a two-stage op-amp. To these aims, it is composed of a p-channel differential input pair (M1 , M2 ), followed by the common-gates stage (M5 , M6 ) and the current source (M3 , M4 ). Bias voltages Vbias1 –Vbias4 are provided to M3 –M10 in order to meet

Sensors 2016, 16, 1416

4 of 13

the current specifications at the cascode stage, so as to keep all transistors in the saturation region. The small-signal voltage gain of this circuit is then: Sensors 2016, 16, 1416

4 of 13

AV = Gm1 Ro

Sensors 2016, 16, 1416 Sensors 2016, 16, 1416

4 of 13 4 of 13

(2)

AV  Gm1Ro (2) where Gm1 is the overall transconductance of the output AV folded  Gm1Ro cascade amplifier in Figure 5; Ro is the (2) AV as:  Gm1Rocascade amplifier in Figure 5; Ro is the output (2) whereofGm1 is amplifier, the overall which transconductance of the folded resistance the can be derived resistance which can be derived as: cascade amplifier in Figure 5; Ro is the output where Gm1ofisthe theamplifier, overall transconductance of the folded where Gm1 is the overall transconductance of the folded cascade amplifier in Figure 5; Ro is the output resistance of the amplifier, which be)rderived as: )]//[( g + g )r r )] Ro = [(R gm5 + can gmb5 o5 (ro1 //r m7 mb o7 o9 gmbderived / roo3 resistance of the amplifier, which (3) o  [( gcan m5 be 5 )ro5 (ro1 /as: 3 )]/ /[( gm7  gmb )ro 7 ro9 )] Ro  [( gm5  gmb5 )ro5 (ro1 / / ro3 )]/ /[( gm7  gmb )ro7ro9 )] (3) Ro  [( gm5  gmb5 )ro5 (ro1 / / ro3 )]/ /[( gm7  gmb )ro7ro9 )] (3) OP+

Vin+ Vin+ Vin+

OP+ OP+

Resistor array Resistor array Resistor array

VinVinVin-

OPout OPout

RX RX RX

R2 R2 R2

R1 R1 R1

OPOPOP-

Resistor array Resistor arrayRy Resistor array Ry OPout Ry

R2 R2 R2

R1 R1 R1

Vout+ VV out+ outVout+ V outVout-

Ry Resistor array Ry Resistor array Ry Resistor array

Figure 3. The programmable gain amplifier (PGA).

Figure 3. 3. The gainamplifier amplifier (PGA). Figure Theprogrammable programmable gain (PGA). Figure 3. TheCtr1 programmable gain amplifier (PGA). Ctr1 Ctr1

Ctr2 Ctr2 Ctr2 Ctr3 Ctr3 Ctr3 Ctr16 Ctr16 Ctr16 Vi Vi

R1 R1

Vi

R2 R2

R3 R3

R R44

Vo Vo

R R1616

Vo

R3 R4 array in the R16PGA. Figure switch resistor R1 4. TheRon-chip 2 Figure 4. The on-chip switch resistor array in the PGA.

Figure 4. The on-chip switch resistor array in the PGA. Figure 4. The on-chip switch resistor array in the PGA.

V VDD DD VDD

VVin1 in1 Vin1

M M11 11

M99 M M9 M77 M M7

V Vin2 in2

M11 M M11 M M22 V in2 M1 M2

M55

M5

M10 10 M Vbias1 bias1 M10V M88 Vbias1 M Vbias2 M Vbias2 8

Vbias2 Vbias3 bias3 V

M66 M Vbias3 M6 Vbias4 V bias4

M3

M44 Vbias4 M

M3

M4

Figure 5. 5. The folded cascade amplifier Figure amplifier circuit. circuit.

Figure Thefolded folded cascade cascade amplifier Figure 5.5.The amplifiercircuit. circuit.

out1 VVout1 Vout2 V out2 V out1

Vout2

(3)

Sensors 2016, 16, 1416

5 of 13

Sensors 2016, 16, 1416

5 of 13

Despite the previously-designed fully-differential circuit being implemented along with some Despite the previously-designed fully-differential circuit being implemented along with some advantages, the common-mode (CM) loop gain from the external feedback loop around the advantages, the common-mode (CM) loop gain from the external feedback loop around the fully-differential op-amp is quite small, and the CM voltage is not precisely stably defined. fully-differential op-amp is quite small, and the CM voltage is not precisely stably defined. Without Without proper control, the output CM voltage tends to drift to the supply rails due to power proper control, the output CM voltage tends to drift to the supply rails due to power supply supply variations, process variation, offsets, etc. Thus, an additional continuous-time common-mode variations, process variation, offsets, etc. Thus, an additional continuous-time common-mode feedback (CMFB) sub-circuit is applied herein to stabilize the common-mode voltage of the feedback (CMFB) sub-circuit is applied herein to stabilize the common-mode voltage of the amplifier amplifier in Figure 5. Note that the CMFB circuit is utilized in a fully-differential op-amp to in Figure 5. Note that the CMFB circuit is utilized in a fully-differential op-amp to keep the op-amp keep the op-amp outputs balanced around a known CM voltage VCM . In order to reduce power outputs balanced around a known CM voltage VCM. In order to reduce power consumption, a consumption, a switched-capacitor common-mode feedback (SC-CMFB) [18–20] in conjunction with switched-capacitor common-mode feedback (SC-CMFB) [18–20] in conjunction with the the previously-designed folded cascade amplifier in Figure 5 is designed and shown in Figure 6. previously-designed folded cascade amplifier in Figure 5 is designed and shown in Figure 6. The The input stage, shown in a box, consists of a p-type metal-oxide-semiconductor (PMOS) differential input stage, shown in a box, consists of a p-type metal-oxide-semiconductor (PMOS) differential pair pair with the drains of PMOSs connected to the sources of n-type metal-oxide-semiconductors (NMOSs) with the drains of PMOSs connected to the sources of n-type metal-oxide-semiconductors (NMOSs) (M5 , M6 ). The rest of the elements in Figure 5 constitute the SC-CMFB circuit. The main advantages of (M5, M6). The rest of the elements in Figure 5 constitute the SC-CMFB circuit. The main advantages SC-CMFB are that they impose no restrictions on the maximum allowable differential input signals, no of SC-CMFB are that they impose no restrictions on the maximum allowable differential input signals, additional parasitic poles in the common mode loop and high linearity. For stability consideration, no additional parasitic poles in the common mode loop and high linearity. For stability consideration, substantial effort has been devoted to ensure fast enough common-mode detection in order to ensure substantial effort has been devoted to ensure fast enough common-mode detection in order to ensure the stability of the whole amplifier. In addition, the CMFB amplifier is designed with adequate gain the stability of the whole amplifier. In addition, the CMFB amplifier is designed with adequate gain to make and the detected common mode to make sure sure good good tracking tracking between between common common mode mode voltage voltage V VCM CM and the detected common mode voltage at and VBias4x determine all bias currents for the voltage at the the outputs. outputs. Finally, Finally, the the voltages voltages VVBias4 Bias4 and VBias4x determine all bias currents for the SC-CMFB circuit. SC-CMFB circuit. VDD

MS1

MS3

VCMO VBias4 MB1

MS2

MS4

M5

Input Vout2 Stage M6

M3

M4

Vout1

VBias4x

MS5

MS7 VCMO

VBias4 MS6

MS8

Figure 6. 6. The The switched-capacitor switched-capacitor common common mode mode feedback feedback circuit. circuit. Figure

Switch Resistor Array and Decoder Block Circuit 2.2. Switch control forfor the the nearnear full dynamic rangerange at the at outthe of the in Figure 3, To facilitate facilitatedigital digitalgain gain control full dynamic outPGA of the PGA in variable3,resistor Rx arrays and RyR’sx are using linear resistors series with the MOSFET Figure variablearrays resistor andimplemented Ry’s are implemented using linear in resistors in series with the switches biased in biased the triode region, shownasinshown Figurein3.Figure The variable resistorsresistors in the PGA acquire MOSFET switches in the triodeasregion, 3. The variable in the PGA feedbackfeedback from thefrom analog-to-digital converter (ADC) output through digital feedback control acquire the analog-to-digital converter (ADC) stage output stage through digital feedback to adjust gain and automatically choose a suitable gain forforvarying control to adjust gainthen and then automatically choose a suitable gain varyingvoltage voltageoutputs outputs from The PGA, PGA, as as mentioned mentioned in in Section Section 2.2, is facilitated with an internal the considered MR sensor. The common-mode feedback (CMFB) circuit to stabilize the output voltage level before the signals reach two modes forfor gaingain control: fine fine and coarse tunings. In fineIntune the subsequent subsequentADC. ADC.There Thereare are two modes control: and coarse tunings. finemode, tune a four-bit decoderdecoder is designed to specifyto16specify gain levels for R theRother a two-bit decoder for mode, a four-bit is designed 16 gain levels y. Onhand, the other hand, a two-bit y . Onfor coarse tune adopted . The circuit for implementing tunable resistances R and R ’s is shown decoder for is coarse tunefor is Radopted for R x . The circuit for implementing tunable resistances R x and x x y iny’s Figure 6. in Figure 6. R is shown

2.3. Hysteresis Comparator Design To generate transistor-transistor logic (TTL) signals for inputting into a digital block circuit to compute succeeding interpolation for deciphering reader stage position, two hysteresis comparator circuits accepting input sinusoids and co-sinusoids from the MR sensor are forged with

Sensors 2016, 16, 1416

6 of 13

2.3. Hysteresis Comparator Design To generate transistor-transistor logic (TTL) signals for inputting into a digital block circuit to compute succeeding interpolation for deciphering reader stage position, two hysteresis Sensors 2016, 16, 1416 6 of 13 comparator circuits accepting input sinusoids and co-sinusoids from the MR sensor are forged with specially-designed pre-amplifiers inside for substantial noise reduction, both of which are in the same specially-designed pre-amplifiers inside for substantial noise reduction, both of which are in the same topology as shown in Figure 7a. Hysteresis consideration is designed in many comparators [20–23]. topology as shown in Figure 7a. Hysteresis consideration is designed in many comparators [20–23]. The inherent hysteresis with pre-designated distinct positive and negative switching voltage levels The inherent hysteresis with pre-designated distinct positive and negative switching voltage levels as illustrated by Figure 7b helps the comparator to avoid ripples at the output due to small amounts as illustrated by Figure 7b helps the comparator to avoid ripples at the output due to small amounts of parasitic feedbacks and noises. A two-stage comparator is adopted herein with the first stage as of parasitic feedbacks and noises. A two-stage comparator is adopted herein with the first stage as a a low-gain pre-amplifier. The input pair MOSs are designed in small sizes and operated in a slow low-gain pre-amplifier. The input pair MOSs are designed in small sizes and operated in a slow slew slew rate to minimize kickback noise. The resulting positive and negative switching voltage can be rate to minimize kickback noise. The resulting positive and negative switching voltage can be prescribed by the same equation as: prescribed by the same equation as: s s 22II 22 2 I12I1 (4) VTRP±V= V  VGS −2VGS1 VGS1= +VVt2−  V− Vt1 (4) TRP  GS2 β22 t 2 1 β1 t1

InEquation Equation(4), (4),when whenthe thedifferential differentialinput inputvoltage voltage(V (VGS2 GS2 −− VV GS1 ) is) in increase, M8M opens as the In is an in an increase, as 8 opens GS1 (i11) (ibecomes equal to the current through the MOS M 6 (i 6 ); i.e., current flowing through thethe MOS M1M the current flowing through MOS ) becomes equal to the current through the MOS M (i 1 6 6 ); as positive triptrip point voltage (V(V GS2GS2 − V−GS1V) GS1 ≥ V On the hand,hand, when (VGS2(V−GS2 VGS1 keeps i.e., as positive point voltage ) TRP+ ≥ V. TRP+ . Onother the other when −) V GS1 ) decreasing and then a negative trip point (VTRP−), (V theTRP comparator changes state. The keeps decreasing andreaching then reaching a negative tripvoltage point voltage changes − ), the comparator current through pairs of the MOSs (MMOSs 2 and M 7 and 3,7M 6 and 1) 6are off. state. Theflows current flows these through these pairs of the (M4,2 M and M4M ,M and M3M ,M and M1 ) are off.

(a)

(b)

Figure 7. (a) The hysteresis comparator with pre-amplifier; (b) positive and negative trip voltages. Figure 7. (a) The hysteresis comparator with pre-amplifier; (b) positive and negative trip voltages.

2.4. Successive Approximation Register ADC 2.4. Successive Approximation Register ADC The output signal from the PGA is connected to an analog-to-digital (ADC) block to convert The output signal from the PGA is connected to an analog-to-digital (ADC) block to convert analog-to-digital signals before being analyzed in a digital block [21–27]. The complete topology of analog-to-digital signals before being analyzed in a digital block [21–27]. The complete topology of the the designed 12-bit SAR-ADC, which includes a sample and hold (S/H) circuit, a digital to analog designed 12-bit SAR-ADC, which includes a sample and hold (S/H) circuit, a digital to analog converter, converter, a comparator circuit and a successive approximation register, is shown in Figure 8a. The a comparator circuit and a successive approximation register, is shown in Figure 8a. The SAR-ADC SAR-ADC design approach is proposed as a hybrid of resistors and capacitors, such that the design approach is proposed as a hybrid of resistors and capacitors, such that the performance performance is improved, thus being able to increase the sampling rate and reduce the negative is improved, thus being able to increase the sampling rate and reduce the negative effects of the effects of the fabrication process tolerance [25–27]. In Figure 8b, the circuits in green and blue blocks fabrication process tolerance [25–27]. In Figure 8b, the circuits in green and blue blocks constitute the constitute the 12-bit digital-to-analog converter, using a binary-weighted capacitor array and 12-bit digital-to-analog converter, using a binary-weighted capacitor array and resistors in an R-string, resistors in an R-string, whose number of bits is 9 bit and 3 bit, respectively. The unit capacitance whose of bits is 9 bit and 3 bit, respectively. The unit of capacitance 10 fF. Thisvalue adopted used isnumber 10 fF. This adopted architecture owns the advantages a reducedused total is capacitance and architecture owns the advantages of a reduced total capacitance value and small proportion error, small proportion error, while the R-string DAC has high linearity and a low least significant bit (LSB), leading to increasing the resolution significantly. Besides the D/A converter, the comparator has a crucial influence on the overall performance in the SAR ADC. In this study, the topology of the comparator for SAR-ADC is designed and then shown in Figure 9. This comparator adopts differential inputs of PMOSs to reduce flicker noises and operated on the weak inversion area to increase the highest gain. The PMOSs are connected to the source and

Sensors 2016, 16, 1416

7 of 13

Sensors 2016, 16, 1416 of 13 Sensors 2016, 1416 of7313 opened, and16,the comparator is in the comparison state. On the contrary, when the Clk is high,7 M and

M4 are closed, and the comparator is in the reset state. The comparator requires high a bandwidth opened, and the comparator is in the comparison state. On the contrary, when the Clk is high, M3 and and high gain to increase thehigh switch speedand andareduce thesignificant return time, it consumes more power. while theclosed, R-string DAC linearity least bitbut (LSB), leading to increasing M4 are and the has comparator is in the resetlow state. The comparator requires high a bandwidth Thus, an effort has been dedicated herein to achieve a comprise between speedon and the resolution Besides D/A converter, thereturn comparator has a crucial influence the and high gainsignificantly. to increase the switchthe speed and reduce the time, but it consumes more power. power consumption. overall in the SARdedicated ADC. In this study, topology the comparator SAR-ADC Thus, performance an effort has been herein tothe achieve a of comprise betweenforspeed and is designed and then Vshown in Figure 9. power consumption. ref

B0

Vref

B0

B1 B1

B0

B2 B0 B0 B2 B0

B1

B0 B0

Vdd B1

C9+

Vi-

Vi+

Vref B0

Vi+

B0 B1

B0 B0

B0

C7+

C6+

C+ C+ C+ Bootstrapped switch Bootstrapped switch

Vi-

Vref

Vdd

C8+

C9+

8

7

C9B3 C9B3

C8B4 C8B4

C7B5

6

C7B5

C6B6

C6B6

C5+

C4+

C5+

C4+

C5B7

C5B7

C4B8

C4B8

C3+ C3+

C2+ C2+

C3B9

C3B9

C2B10

C2B10

C1+ C1+

C1B11

B2 B2

Vdd

Control

SAR logic CLK

CLK

SAR logic

SAR logic

Vdd

9-bit Capacitor 9-bit Capacitor DAC DAC

B1

Control

C1B11

SAR logic

Output Output

B0

B0 B0

3-bit Resisor 3-bitDAC Resisor DAC

(a)

(a)

B2

B2

C9+ C9+

C8+ C8+

C+

C77+

C+

C5+5

C+

C4+4

CC6-6-

CC 5-5-

C4C- 4-

6 C6+

C+

C+

C3+ 3

C2+ C +C1+ 1

C2+

Bootstrapped Bootstrapped switch VVi-iCC99-B3 B3

C8B4

C C77-B5 B5

B6 B6

B7 B7

B8B8

C3C - 3-

C2-C2-

C1- C1-

B9B9

B10 B10

B11B11

9-bit 9-bitCapacitor Capacitor DAC DAC (b) (b) Figure 8. (a) The topology of the 12-bit SAR ADC; (b) a bootstrapped and partial DAC of the ADC. Figure 8. 8. (a) The topology topology of of the the 12-bit 12-bit SAR SAR ADC; ADC; (b) (b) aa bootstrapped bootstrapped and and partial partial DAC DAC of of the the ADC. ADC. Figure

Figure 9. Comparator circuit implemented in the 12-bit hybrid SAR ADC.

Figure 9. 9. Comparator Comparator circuit circuit implemented implemented in in the the 12-bit 12-bit hybrid hybrid SAR SAR ADC. ADC. Figure

Sensors 2016, 16, 1416

8 of 13

This comparator adopts differential inputs of PMOSs to reduce flicker noises and operated on the weak inversion area to increase the highest gain. The PMOSs are connected to the source and drain to avoid body effects. It can also strengthen the input common mode range (ICMR) and the common mode rejection ration (CMRR). When the input Clk of the comparator is low, M3 and M4 are opened, and the comparator is in the comparison state. On the contrary, when the Clk is high, M3 and M4 are closed, and the comparator is in the reset state. The comparator requires high a bandwidth and high gain to increase the switch speed and reduce the return time, but it consumes more power. Thus, an Sensors 2016, 16, 1416 8 of 13 effort has been dedicated herein to achieve a comprise between speed and power consumption. Sensors 2016, 16, 1416

8 of 13

3. Experimental Results 3. Experimental Results 3. Experimental Results Functions in blocks, connections and I/Os of the designed chip are illustrated by Figure 10. With Functions in blocks, connections and I/Os of the designed chip are illustrated by Figure 10. Functions in blocks,confirming connectionsthe and I/Os of the designed chip are the illustrated by Figure With simulations successfully expected chip performances, designed chip is10. fabricated With simulations successfully confirming the expected chip performances, the designed chip is simulations successfully confirming the expected chip performances, the designed chip is fabricated via the TSMC 0.35-µm CMOS process. A die photo of the proposed chip is shown in Figure 11. The fabricated via the TSMC 0.35-µm CMOS process. A die photo of the proposed chip is shown in viaarea the TSMC CMOSthe process. die photo of the proposed chip is shown in Figure 11. Thefor chip is 6.610.35-µm mm2, while powerAconsumption is 56 mW. Measurements are conducted Figure 11. The chip area is 6.61 mm2 , while the power consumption is 56 mW. Measurements are 2 chip areathe is 6.61 mm , while consumption 56 mW.output Measurements conducted for of validating performance ofthe thepower proposed chip. Theis sensor has threeare different levels conducted forthe validating the performance of the proposed chip. output The sensor output has three different validating performance of the proposed chip. The sensor has three different levels of output voltage to the PGA, e.g., 120 mVp-p, 250 mVp-p and 330 mVp-p, which are amplified successfully levels of output voltage to the PGA, e.g.,p-p,120 mV 250 mVp-p p-p and 330 mV , whichsuccessfully are amplified p-p, p-p output voltage to the PGA, e.g., 120 mV 250 mV p-p and 330 mV , which are amplified by the designed PGA with 1 mVp-p at the output with adequate precision. successfully by thePGA designed 1 mV theadequate output with adequate precision. p-p at by the designed with 1PGA mVp-pwith at the output with precision. VDD VDD GND

Supply voltage Supply voltage (Analog)

VDD1 VDD1 GND1

Supply voltage Supply voltage (Digital)

GND1

Pcos

Pcos

Ncos

Compactor

Compactor (1) (1)

(Digital)

PGA(1)

PGA(1)

Ncos

Fine Finetuning tuning Ctrl. Ctrl.Signal Signal Psin Psin Nsin Nsin

Cosine

(Analog)

GND

PGA(2) PGA(2)

SAR-ADC

Coarse tuning Ctrl. Signal Coarse tuning Ctrl. Signal

Ain Ain Bin

Bout

Bout

Cos_A2D

Cos_A2D Bus Bus

Digital feedback Digital feedback control control (Cell-based) (Cell-based) Coarse tuning Ctrl. Ctrl.Signal Signal SAR-ADC SAR-ADC Coarse tuning (2) (2) Compactor Compactor (2) (2)

R0R0 R1R1 R2R2 Pref. Pref. Nref. Nref.

SAR-ADC (1) (1)

Cosine monitor monitor

Sin_A2D Sin_A2D Bus Bus Aout Aout Sine Sine monitor monitor

Amplifier Amplifier Ref.Signal Signal Ref.

Compactor Compactor (3) (3)

Logic Logic (And (Andgate) gate)

Zout Zout

Bin

Figure10. 10.Architecture Architecture of of the Figure the adaptive adaptive encoder IC. adaptiveencoder encoderIC. IC.

Figure 11. Die photo of the fabricated encoder IC.

Figure 11. Die photo of the fabricated encoder IC. Figure 11. Die photo of the fabricated encoder IC.

The measured result of the PGA is shown in Figure 12, where the sinusoids associated with co-sinusoids are amplified reaching to 1 V12, p-p. Figure the power spectral The measured result ofwith the amplitudes PGA is shown in Figure where 13 theshows sinusoids associated with density of the PGA output, the noise of which is clearly controlled well below −80.2 dB with noise co-sinusoids are amplified with amplitudes reaching to 1 Vp-p. Figure 13 shows the powera spectral floor level −90 dB/Hz. Following the PGA circuits, two comparators implemented to density of theunder PGA output, the noise of which is clearly controlled well beloware −80.2 dB with a noise generate transistor-transistor logic (TTL) signals for determining the MR reader position, as well as floor level under −90 dB/Hz. Following the PGA circuits, two comparators are implemented to direction. The result of the comparator circuit is shown in Figure 14. Furthermore, it can be seen in

generate transistor-transistor logic (TTL) signals for determining the MR reader position, as well as

Sensors 2016, 16, 1416

9 of 13

The measured result of the PGA is shown in Figure 12, where the sinusoids associated with co-sinusoids are amplified with amplitudes reaching to 1 Vp-p . Figure 13 shows the power spectral density of the PGA output, the noise of which is clearly controlled well below −80.2 dB with a noise floor level under −90 dB/Hz. Following the PGA circuits, two comparators are implemented to generate transistor-transistor logic (TTL) signals for determining the MR reader position, as well as direction. The result of the comparator circuit is shown in Figure 14. Furthermore, it can be seen in Figure 14 that the TTL output is used to determine in which quadrants the MR sensor is. These data are used to specify the director of the MR sensor movement. To compute the position of the sensor, an algorithm was implemented by FPGA to calculate interpolation. The algorithm employed in FPGA is able to determine precise MR reader positions with the capability to compensate the offset and gain errors of the sin/cosine analog signals. In addition to the PGA, the designed 12-bit hybrid analog-to-digital converter (ADC) is successfully realized in the tape-out chip for converting the PGA outputs of sinusoids and co-sinusoids in near full-dynamic ranges to digital values in 12-bits. The 12-bit hybrid SAR ADC was designed as stated in Section 2.4, whose sampling rate is up to 5 MHz. It can successfully convert a sinusoidal input with the required precision at a frequency up to 300 kHz. The measured INL is −0.79–0.95 LSB, while the DNL is −0.68–0.72 LSB, as shown in Figure 15, where the linearity of the ADC achieves a good performance (±1 LSB) in input range 1 Vp-p . The ENOB and all other values to validate the designed 12-bit ADC are shown in Figure 16, where an experimental spectrum on ADC output is calculated and shown. Based on this spectrum, the ENOB is validated as 10.86, which is good enough to convert the input analog signals to digital values for conducting the ensuing interpolation. By utilizing a motor to move the reader stage in the magnetic scale, the readout circuit can successfully extract the output signals from the sensor, and then, the algorithm employed in FPGA computes the position of the sensor2016, precisely. is Sensors 16, 1416 Measurement results show that the position error of the magnetic scale in 10 mm 9 of 13 successfully controlled within ±15 µm, as shown in Figure 17. The summary performance compared toable other is given in Table 1, where it is seen that present to design offers larger interpolation is toworks determine precise MR reader positions with thethe capability compensate the offset and gain digits in small chip area and signals. via the relative conventional 0.35-µm process, thus also at low cost. errors of athe sin/cosine analog

(a)

(b)

Figure 12. Measured result of the PGA: (a) sin/cosine inputs; (b) sin/cosine outputs. Figure 12. Measured result of the PGA: (a) sin/cosine inputs; (b) sin/cosine outputs. Single-Sided Power Spectral Density -20 -30 -40

(b)

Sensors 2016, 16, 1416

10 of 13

Figure 12. Measured result of the PGA: (a) sin/cosine inputs; (b) sin/cosine outputs. Single-Sided Power Spectral Density -20 -30

Sensors 2016, 16, 1416 Sensors 2016, 16, 1416

PSD (dB/Hz)

-40 -50 10 of 13

-60

10 of 13

output is calculated and-70shown. Based on this spectrum, the ENOB is validated as 10.86, which is good enough to convert the input analog signals to digital values for conducting the ensuing output is calculated and -80 shown. Based on this spectrum, the ENOB is validated as 10.86, which is interpolation. By utilizing a motor to move the reader stage in the magnetic scale, the readout circuit good enough to convert the input analog signals to digital values for conducting the ensuing can successfully extract the output signals from the sensor, and then, the algorithm employed in interpolation. By utilizing-90 a motor to move the reader stage in the magnetic scale, the readout circuit FPGA computes the position of the sensor precisely. Measurement results show that the position can successfully extract the output signals from the sensor, and then, the algorithm employed in -100 in 10 mm is successfully controlled within ±15 µm, as shown in Figure 17. error of the magnetic scale 0 of the sensor 1 2 3 4 results show 5 FPGA computes the position precisely. Measurement that the position 5 Frequency The summary performance compared to other works(MHz) is given in Table x1,10where it is seen that the error of the magnetic scale in 10 mm is successfully controlled within ±15 µm, as shown in Figure 17. present design offers larger interpolation digits in a small chip area and via the relative conventional The summary performanceFigure compared otherspectral worksdensity is given inPGA Table 1, where it is seen that the 13. Theto power of the output. Figure 13. The power spectral density of the PGA output. 0.35-µm process, thus also at low cost. present design offers larger interpolation digits in a small chip area and via the relative conventional 0.35-µm process, thustoalso low cost. In addition theatPGA, the designed 12-bit hybrid analog-to-digital converter (ADC) is successfully realized in the tape-out chip for converting the PGA outputs of sinusoids and co-sinusoids in near full-dynamic ranges to digital values in 12-bits. The 12-bit hybrid SAR ADC was designed as stated in Section 2.4, whose sampling rate is up to 5 MHz. It can successfully convert a sinusoidal input with the required precision at a frequency up to 300 kHz. The measured INL is −0.79–0.95 LSB, while the DNL is −0.68–0.72 LSB, as shown in Figure 15, where the linearity of the ADC achieves a good performance (±1 LSB) in input range 1 Vp-p. The ENOB and all other values to validate the designed 12-bit ADC are shown in Figure 16, where an experimental spectrum on ADC

Figure 14. The result of comparator output to determine the direction of the MR sensor. Figure 14. The result of comparator output to determine the direction of the MR sensor. Figure 14. The result of comparator output to determine the direction of the MR sensor.

(a)

(b)

(b) SAR ADC. Figure 15.(a) Performance of (a) INL and (b) DNL of the 12-bit hybrid Figure 15. Performance of (a) INL and (b) DNL of the 12-bit hybrid SAR ADC. Figure 15. Performance of (a) INL and (b) DNL of the 12-bit hybrid SAR ADC. Table 1. Performance comparison with other interpolation methods. [5] [29] methods. Table 1. Performance comparison [28] with other interpolation Technology Interpolation Method Technology SamplingMethod Rate Interpolation

This Work N/A 0.35-µm CMOS 0.5-µm CMOS 2P2M 0.35-µm CMOS 2P4M [5] Adaptive [28] [29] This Work Advanced ADC Comparator-based ADC and comparator N/A 0.35-µm CMOS 0.5-µm CMOS 2P2M 0.35-µm CMOS 2P4M Phase-locked loop AdvancedN/A Adaptive 100 kS/s Not needed kS/s ADC Comparator-based ADC and600 comparator Phase-locked loop

Sensors 2016, 16, 1416

11 of 13

Sensors 2016, 16, 1416

11 of 13

Spectrum of ADC output signal

Sensors 2016, 16, 1416

11 of 13

0 Spectrum of ADC output signal

-20

-20

-40

-40

Amplitude(dB)

Amplitude(dB)

Fs = 6 MHz Fin = 300 kHz Fs = 6 MHz SNDR = 67 Fin = 300 kHz SFDR SNDR== 82.1 67 ENOB = 10.86 SFDR = 82.1

0

-60

ENOB = 10.86

-60

-80

-80

-100 -100

-120

0-120

0.5

0

1

0.5

1.5 2 1 1.5 2 Frequency (MHz)

2.5

3

2.5

3

Frequency (MHz)

16. The result ofofthe FigureFigure analysis 16. spectrum The spectrum analysis result the12-bit 12-bitADC ADC output. output.

50

50

40

40

30

30 20

Error ( m)

Error ( m)

20 10

0 -10

10 0 -10 -20

-20

-30

-30

-40

-40

-50

-50

0

0

2

2

4 6 Actual Distance (mm)

4

6

8

8

Figure 17. The result of the displacement Actual Distance (mm)error in 10 mm.

10

10

4. Conclusions

Figure 17. The error in in 10 10 mm. mm. Figure 17. The result result of of the the displacement displacement error A front-end readout circuit is proposed by this study, which can be applied to a magnetic scale 4. Conclusions for different product The chip has been successfully designed and fabricated via the Table 1. specifications. Performance comparison with other interpolation methods. 2, while the power consumption is TSMC 0.35-µm 2P4M CMOS technology. The chip area is 6.61 mm A front-end readout circuit is proposed by this study, which can be applied to a magnetic scale [29]PGA successfullyThis Work the 56 mW under a 5-V power[5]supply. Experiment[28] results show that the amplifies for different product specifications. The chip has been successfully designed and fabricated via the MR electrode outputs of three different voltage 120 2mV p-p,2P2M 250 mVp-p , 330CMOS mVp-p , to Technology N/A 0.35-µm CMOSlevels, 0.5-µm CMOS 0.35-µm 2P4M TSMC 0.35-µm 2P4M CMOS technology. The chip area is 6.61 mm , while the power consumption is 1 mVp-p at the output with adequate precision. This is achieved primarily via auto-adjusting by an Advanced Adaptive Interpolation ADC Comparator-based ADC andamplifies comparator the 56 mW underMethod atunable 5-V power supply. Experiment show PGA successfully Phase-locked loop on-chip feedback resistance to controlresults the PGA gain.that Thethe chip is also validated such that the MR electrode of three voltage mV p-p, 250 mVp-p, 600 330kS/s mVp-p, to Sampling N/A different 100 Not needed output Rate ofoutputs the differential signals is stable. As forkS/s thelevels, designed120 ADC following the PGA, the measured 1 mVInterpolation p-pINL at the output with adequate precision. This is achieved via ADC auto-adjusting Factor 200 the DNL 5, 10,primarily 40of (optional) 1000 (magnetic) by an is −0.79–0.95 LSB, while is −0.68–0.72 LSB. The ENOB the 12-bit experimentally Output Formatfeedback resistance Sine signal to controlCounter code gain. The Pulse stream Counter codethat the on-chip tunable the PGA chip is also validated such 2 2 2 Chip Area N/A mmdesigned ADC3following mm mm output of the differential signals is stable. As for1.7the the PGA,6.61 the measured Power N/A 90 mW 56 mW INL is −0.79–0.95 LSB, while the DNL is −0.68–0.72 LSB. The ENOB50ofmW the 12-bit ADC experimentally

Sensors 2016, 16, 1416

12 of 13

4. Conclusions A front-end readout circuit is proposed by this study, which can be applied to a magnetic scale for different product specifications. The chip has been successfully designed and fabricated via the TSMC 0.35-µm 2P4M CMOS technology. The chip area is 6.61 mm2 , while the power consumption is 56 mW under a 5-V power supply. Experiment results show that the PGA successfully amplifies the MR electrode outputs of three different voltage levels, 120 mVp-p , 250 mVp-p , 330 mVp-p , to 1 mVp-p at the output with adequate precision. This is achieved primarily via auto-adjusting by an on-chip tunable feedback resistance to control the PGA gain. The chip is also validated such that the output of the differential signals is stable. As for the designed ADC following the PGA, the measured INL is −0.79–0.95 LSB, while the DNL is −0.68–0.72 LSB. The ENOB of the 12-bit ADC experimentally reaches 10.86, while the linearity of the ADC has been achieved as ±1 LSB in the input range of 0.5–2.5 V. With the above achieved performance of the PGA and ADC, the fabricated readout chip is next connected to a digital interpolation chip for deciphering the MR reader position in realistic digits. Based on the experimental results, the displacement error is validated to be as small as other works, ±15 µm, at a distance of 10 mm in length. Finally, as compared to other similar chip designs and based on the experimental results, the present readout design offers larger precision interpolation digits at the output in a small chip area and via the relatively conventional 0.35-µm process, thus also at low cost. Acknowledgments: The authors appreciate the support from the National Chip Implementation Center and Ministry of Science and Technology of Taiwan, R.O.C., under Grant Nos. MOST 104-2923-M-009-002 and 105-2623-E-009-009-D. The work was also supported in part by the Novel Bioengineering and Technological Approaches to Solve Two Major Health Problems in Taiwan sponsored by the Taiwan Ministry of Science and Technology Academic Excellence Program under Grant Number MOST 105-2633-B-009-003. Author Contributions: Paul Chang-Po Chao performed the design and fabrication related to the designed chip. Trong-Hieu Tran designed the electronic circuits for testing the proposed chip and wrote the manuscript. Ping-Chieh Chien proposed the idea and the direction of this research. All authors of the article provided substantive comments. All authors read and approved the manuscript. Conflicts of Interest: The authors declare no conflict of interest.

References 1. 2. 3.

4. 5.

6. 7. 8. 9.

Bazzi, A.M.; Dominguez-Garcia, A.; Krein, P.T. Markov reliability modeling for induction motor drives under field-oriented control. IEEE Trans. Power Electron. 2012, 27, 534–546. [CrossRef] Kung, Y.S. Design and implementation of a high-performance PMLSM drives using DSP chip. IEEE Trans. Ind. Electron. 2008, 55, 1341–1351. [CrossRef] Mihalachi, M.; Mutschler, P. Position acquisition for long primary linear drives with passive vehicles. In Proceedings of the IEEE Industry Applications Society Annual Meeting, IAS’08, Edmonton, AL, Canada, 5–9 October 2008; pp. 501–504. Emura, T.; Wang, L. A High-Resolution Interpolator for Incremental Encoders Based on the Quadrature PLL Method. IEEE Trans. Ind. Electron. 2000, 47, 84–90. [CrossRef] Hoang, H.V.; Le, H.T.; Jeon, J.W. A new approach based-on advanced adaptive digital PLL for improving the resolution and accuracy of magnetic encoders. In Proceedings of the IEEE/RSJ International Conference Intelligent Robots and Systems, Nice, France, 22–26 September 2008; pp. 3318–3323. Hagiwara, N.; Suzuki, Y.; Murase, H. A method of improving the resolution and accuracy of rotary encoders using a code compensation technique. IEEE Trans. Instrum. Meas. 1992, 41, 98–101. [CrossRef] Kim, J.C.; Hwang, S.H.; Kim, J.M.; Kim, C.U.; Choi, C. Ultra precise position estimation of servomotor using analog quadrature encoder. J. Power Electron. 2006, 6, 139–145. Mayer, J.R.R. High-resolution of rotary encoder analog quadrature signals. IEEE Trans. Instrum. Meas. 1994, 43, 494–498. [CrossRef] Xiao, K.; Wang, L. Analysis and error compensation of electric sine/cosine encoder. In Proceedings of the the Ninth International Conference on Electronic Measurement & Instruments, ICEMI 2009, Beijing, China, 16–19 August 2009; pp. 87–90.

Sensors 2016, 16, 1416

10. 11.

12. 13. 14. 15.

16. 17. 18. 19. 20. 21. 22. 23. 24. 25.

26.

27.

28.

29.

13 of 13

Ben-brahim, L.; Benammar, M.; Alhamadi, M.A. A novel converter for sinusoidal encoders. In Proceedings of the 5th IEEE Conference on Sensors, Daegu, Korea, 22–25 October 2006; pp. 1415–1418. Krau, M.; Leuschner, U.; Schniek, H.G. A 5V CMOS chip for interpolation of sine/cosine signals. In Proceedings of the 23rd European Solid-State Circuits Conference, ESSCIRC ‘97, Southampton, UK, 16–18 September 1997; pp. 336–339. Yien, C. Incremental encoder errors: Causes and methods to reduce them. In Proceedings of the PCIM’92, Nürnberg, Germany, 28–30 April 1992; pp. 110–121. Tan, K.K.; Zhou, H.X.; Lee, T.H. New interpolation method for quadrature encoder signals. IEEE Trans. Instrum. Meas. 2002, 51, 1073–1079. [CrossRef] Hsu, C.C.; Wu, J.T. A highly linear 125-MHz CMOS switched-resistor programmable gain amplifier. IEEE J. Solid-State Circuits 2003, 38, 1663–1670. Watanable, O.; Otaka, S.; Ashida, M.; Itakura, T. A 380-MHz CMOS linear-in-dB signal-summing variable gain amplifier with gain compensation techniques for CDMA systems. In Proceedings of the Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13–15 June 2002; pp. 136–139. Khoury, J.M. On the design of constant settling time AGC circuits. IEEE Trans. Circuits Syst. 1998, 45, 283–294. [CrossRef] Gomez, R.; Abidi, A. A 50 MHz CMOS variable gain amplifier for magnetic data storage systems. IEEE J. Solid-State Circuits 1992, 27, 935–939. [CrossRef] Castello, R.; Gray, P.R. A high-performance micropower switch-capacitor filter. IEEE J. Solid-State Circuits 1982, 20, 1122–1132. [CrossRef] Garrity, D.; Rakers, P. Common-Mode Output Sensing Circuits. U.S. Patent 5 894 284, 13 April 1999. Carusone, T.C.; Johns, D.A.; Martin, K.W. Analog Integrated Circuit Design, 2nd ed.; John Wiley & Sons, Inc.: Hoboken, NJ, USA, 1997. Promitzer, G. 12-bit low power fully differential switched capacitor non-calibrating successive approximation ADC with 1MS/s. IEEE J. Solid-State Circuits 2001, 36, 1138–1143. [CrossRef] Abo, A.M.; Gray, P.R. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits 1999, 34, 599–606. [CrossRef] Yu, L.; Zhang, J.Y.; Wang, L.; Lu, J.G. A 12-bit Fully Differential SAR ADC with Dynamic Latch Comparator for Portable Physiological Monitoring Applications. Bull. Adv. Technol. Res. 2011, 5, 576–579. Liu, C.C. A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure. IEEE J. Solid-State Circuits 2010, 45, 731–740. [CrossRef] Fang, X.; Srinivasan, V. CMOS 12 bits 50kS/s Micropower SAR and Dual-Slope Hybrid ADC. In Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS ‘09, Cancun, Mexico, 2–5 August 2009; pp. 180–183. Balasubramaniam, H.; Galjan, W. 12-bit Hybrid C2C DAC based SAR ADC with Floating Voltage Shield. In Proceedings of the International Conference on Circuits and Systems, Medenine, Tunisia, 6–8 November 2009; pp. 1–5. Hsieh, S.E.; Ho, C.K.; Hsieh, C.C. A 1.2V 1MS/s 7.65fJ/Conversion-step 12-bit Hybrid, SAR ADC with time-to-Digital Converter. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24–27 May 2015; pp. 2429–2432. Baschirotto, A.; Dallago, E.; Malcovati, P.; Marchesi, M.; Melissano, E.; Morelli, M.; Siciliano, P.; Venchi, G. An Integrated Micro-Fluxgate Magnetic Sensor with Front-End Circuitry. IEEE Trans Instrum. Meas. 2009, 58, 3269–3275. [CrossRef] Chiang, C.-T.; Hsieh, K.-C.; Huang, Y.-C. Design of a CMOS phase to digital transducer for optical incremental sensors. Sens. Actuators A Phys. 2011, 170, 106–113. [CrossRef] © 2016 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC-BY) license (http://creativecommons.org/licenses/by/4.0/).