IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 9, SEPTEMBER 2003
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Three-Transistor One-Time Programmable (OTP) ROM Cell Array Using Standard CMOS Gate Oxide Antifuse Jinbong Kim and Kwyro Lee, Senior Member, IEEE
Abstract—A three-transistor (3-T) cell CMOS one-time programmable (OTP) ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high-voltage blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option of high-density CMOS OTP ROM array for modern digital as well as analog circuits. Index Terms—CMOS antifuse, CMOS OTP, gate-oxide breakdown, OTP ROM.
I. INTRODUCTION
A
MONG various memory types, the one-time programmable (OTP) ROM is one of the cheapest nonvolatile memories in comparison with EEPROM based on charge retention because of its additional processes [1]. The OTP ROM using a CMOS antifuse (AF) is widely applicable to overall CMOS circuits such as high-density memory cell repair, trimming ROM for CMOS analog/RF circuits, program ROM for CMOS digital logics and so on. Above all, using a redundancy memory for DRAM/SRAM cell repair, the CMOS AF ROM is more cost-effective than the conventional laser fusing method that has also a limitation only to be done on wafer test. Polyfusing OTP using joule heating has also been tried for CMOS analog circuits of on-chip ROM to compensate for the process variations and so on [2], but this is not reliable enough to be used for manufacturing. AF elements are more reliable and have been adopted successfully in some commercial circuits such as the via AF used in field programmable gate array (FPGA) from Actel [3] and oxide-nitride-oxide AF proposed for DRAM cell repairing at package level [4], [5]. Even though, they have very reliable AF characteristics, they are not directly applicable to the standard CMOS products because of additional processes. In this letter, we report three–transistor (3-T) OTP cell based on thin gate oxide AF. Not only this AF is reliable [6], but the 3-T cell does not require high-voltage (HV) switching circuitry, making it fully Manuscript received May 5, 2003; revised June 9, 2003. The review of this letter was arranged by Editor S. S. Chung. The authors are with the Department of Electrical Engineering and Computer Science, KAIST, Daejon, Korea. They are also with MICROS Research Center, Taejon 305-701, Republic of Korea (e-mail:
[email protected]). Digital Object Identifier 10.1109/LED.2003.815429
nMOS AF cumulative distributions of R (at V = 2:0 V, = 1:5 k ; V = 2:5 V, and R = 3:0 k ) the cross section of read mode. (The physical oxide thicknesses of = 32 A for 0.18 m and T = 55 A for 0.25 m CMOS process technology.)
Fig. 1.
R and T
compatible with standard CMOS process. Due to the continued scaling and its reliability, we are now in a position to consider AF based on gate oxide. II. CMOS ANTIFUSE To measure the CMOS AF, source and drain nodes are grounded and the program high voltage (HV) is applied to the gate of nMOS AF. The equivalent circuit and the location of ruptured oxide are similar to those of previous results [7]. Before breakdown (BD) of gate oxide, channel is inverted and the gate tunneling current flows through large resistance of ( G at ). However, gate oxide is broken down in the channel or source/drain overlapped regions when exceeds the the voltage applied to the gate of nMOS AF . The values of for manufacturer A BD voltage of m CMOS, ) and manufacturer B ( m CMOS, ) are about 5.8 and ( 8.8 V, respectively. During the BD of oxide, the on-state reduces [8] and the current increases up to resistance the compliance of 1 mA. It is found that the similar phenomena occur in the pMOS AF. Fig. 1 shows the cumulative distribufor each 100-sample of nMOS AFs. The tions of is measured with ruptured AF which has already been produring programming duty grammed with constant HV of V, V; ms, of (
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IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 9, SEPTEMBER 2003
Fig. 2. Three-transistor cell OTP ROM using MA CMOS process. (a) Proposed 3-T cell. (b) Selected cell for programming. (c) Nonselected cell with broken AF. (d) and (e) Nonselected cells with unbroken AFs. (f) Microphotograph for 4-bit OTP ROM array.
s). With the serially connected blocking resis, the is acquired with Ohm’s law at the ( k k ; V, V). To take care of wide , especially anomalously spread in the distributions of , we choose sufficiently large long tail for of 50 k and of 5 k , in our OTP array design. SPICE simulation results show that these large RON values slow down sensing time a little bit, but the cell of 50 k is large enough to current of 36.7 A at the use a conventional current sense amplifier [9]. tance of voltage of
III. THREE-TRANSISTOR CELL CMOS OTP ROM ARRAY To use CMOS AF for an OTP ROM array, we propose 3-T OTP ROM cell as shown in Fig. 2(a), which is composed of an AF, a HV blocking nMOS (BM), and a cell access transistor (AT). In the program mode, externally supplied HV is applied to node) though single external tied gates of all nMOS AFs ( pin, and only one of AF selected by corresponding word-line (WL) and bit-line (BL), is ruptured. In the read mode, is applied to the node, instead. This alleviates the use of HV switching, making it compatible with standard CMOS technology. The reading current flows through the AF to BL at the programmed cell, which is detected by the BL sense amplifier, pA) flows at the nonwhile very small tunneling current ( programmed cell. Fig. 2(b)–(e) shows various operating conditions during program mode for selected/nonselected cells to explain possible
disturbances. In the selected cell shown in Fig. 2(b), after AF programmed, HV would be applied between the drain of BM and P-substrate in case of small . In order to avoid these is inserted in series with phenomena, a blocking resistor HV node, which also helps to keep constant current level for uniform rupturing. For the nonselected cell with already broken AF as shown in Fig. 2(c), HV is now applied directly to the drainsubstrate junction of BM, which cannot also be destructive, because the AT is now in OFF-state. Only small gate induced drain leakage (GIDL) current of BM flows through drain-toA at V, substrate junction ( V for 0.18 m technology and A at V, V for 0.25 m technology), which is nondestructive during long programming duration. To acquire more reliable BM operation for longer ducan be taken into conration, the gate biasing of BM by in Fig. 2. From sideration as the half of biasing, mean time to dielectric BD of BM is expected times longer than that of AF [10]. In the nonsto be about elected cell with unbroken AF shown in Fig. 2(d) and (e), we have found no disturbance problems. HV is divided between and the off-stated BM retwo resistors, namely, the AF sistance. It has been known from measurement results that the nonselected and unbroken AFs have not been ruptured for the above 10 V. The 4-bit cell measurements are shown in Fig. 3. The selected cells (“cell 1, 0” and “cell 1, 1”) are programmed with input signals of “BLS1, WL1” and “BLS0, WL1,” respec-
KIM AND LEE: THREE-T OTP ROM CELL ARRAY
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Fig. 3. Measurement results of 4-bit OTP ROM array using MA CMOS process. (a) Program mode current and voltage. (b) Read mode I/O signals [refer to the measurement schematic: Fig. 2(b)–(e)].
tively. When AFs are ruptured, the gate voltage of AF is gone down to 4.7 V and supplied currents are about 1.3 mA for both cells. In the read mode, the output value of previously programmed cell(cell 1, 0) is 0 V and that of nonprogrammed , respectively. The microphotograph of cell(cell 0, 0) is 4-bit OTP ROM array is shown in Fig. 2(f) and the cell area of the proposed 3-T OTP ROM is about 21 m for 1-bit. To implement a high-density OTP ROM, we propose a unit ROM and several tens or hundreds of OTP block which has a cells, to avoid the program HV drop from GIDL current in program mode. The group of unit blocks composes a high-density OTP ROM. IV. CONCLUSION In this letter, we have proposed and measured CMOS AF electrical characteristics, before and after programming, which . shows high enough fresh gate oxide resistance and low Based on this CMOS AFs, we have also proposed 3-T cell OTP ROM using standard CMOS process, which can be a viable technology option for modern digital and analog circuits. ACKNOWLEDGMENT The authors appreciate useful discussion with Dr. K. Kim at Samsung Electronics Co. Ltd. and careful reviewers’ comment.
REFERENCES [1] K.-H. Kim and K. Lee, “An 8 b resolution 360 us write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS),” in Proc. IEEE Int. Solid-State Circuit Conf., 1998, pp. 336–337, 459. [2] O. Kim, C. J. Oh, and K. S. Kim, “CMOS trimming circuit based on polysilicon fusing,” Electron. Lett., vol. 34, no. 4, pp. 355–356, Feb. 1998. [3] Actels Antifuse FPGAs product brochure.pdf" [Online]. Available: http://www.actel.com/products/antifuse.html [4] J.-S. Choi, J.-K. Wee, H.-Y. Choi, P.-J. Kim, J.-K. Oh, C.-H. Lee, J.-Y. Chung, S.-C. Kim, and W. yang, “Antifuse EPROM circuit for field programmable DRAM,” in Proc. IEEE Int. Solid-State Circuit Conf., 2000, pp. 406–407. [5] J.-K. Wee, J.-H. Kook, S.-H. Hong, and J.-H. Ahn, “Antifuse circuits and their applications to post-package of DRAMs,” J. Semicond. Technol. Sci., vol. 1, no. 4, pp. 216–231, Dec. 2001. [6] P. Candelier, N. Villani, J.-P. Schoellkopf, and P. Mortini, “One time programmable drift antifuse cell reliability,” in Proc. IEEE Int. Reliabil. Phys. Symp., 2000, pp. 169–173. [7] B. Kaczer, R. Degraeve, A. De Keersgieter, K. Van de Mieroop, V. Simons, and G. Groeseneken, “Consistent model for short-channel nMOSFET after hard gate oxide breakdown,” IEEE Trans. Electron Devices, vol. 49, pp. 507–513, Mar. 2002. [8] B. P. Linder, J. H. Stathis, R. A. Wachnik, E. Wu, S. A. Cohen, A. Ray, and A. Vayshenker, “Gate oxide breakdown under current limited constant voltage stress,” in Symp. VLSI Technol. Dig., 2000, pp. 214–215. [9] C. Papaix and J. M. Daga, “A new single ended sense amplifier for low voltage embedded EEPROM non volatile memories,” in Proc. MTDT, 2002, pp. 149–153. [10] J. C. Lee, I.-C. Chen, and C. Hu, “Modeling and characterization of gate oxide reliability,” IEEE Trans. Electron Devices, vol. 35, pp. 2268–2278, Dec. 1988.
